1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Runyang Chen <runyang.chen@mediatek.com> 5 */ 6 7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 8 #define _DT_BINDINGS_RESET_CONTROLLER_MT8186 9 10 /* TOPRGU resets */ 11 #define MT8186_TOPRGU_INFRA_SW_RST 0 12 #define MT8186_TOPRGU_MM_SW_RST 1 13 #define MT8186_TOPRGU_MFG_SW_RST 2 14 #define MT8186_TOPRGU_VENC_SW_RST 3 15 #define MT8186_TOPRGU_VDEC_SW_RST 4 16 #define MT8186_TOPRGU_IMG_SW_RST 5 17 #define MT8186_TOPRGU_DDR_SW_RST 6 18 #define MT8186_TOPRGU_INFRA_AO_SW_RST 8 19 #define MT8186_TOPRGU_CONNSYS_SW_RST 9 20 #define MT8186_TOPRGU_APMIXED_SW_RST 10 21 #define MT8186_TOPRGU_PWRAP_SW_RST 11 22 #define MT8186_TOPRGU_CONN_MCU_SW_RST 12 23 #define MT8186_TOPRGU_IPNNA_SW_RST 13 24 #define MT8186_TOPRGU_WPE_SW_RST 14 25 #define MT8186_TOPRGU_ADSP_SW_RST 15 26 #define MT8186_TOPRGU_AUDIO_SW_RST 17 27 #define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 28 #define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 29 #define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 30 #define MT8186_TOPRGU_IPE_SW_RST 21 31 #define MT8186_TOPRGU_IMG2_SW_RST 22 32 #define MT8186_TOPRGU_SW_RST_NUM 23 33 34 /* MMSYS resets */ 35 #define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 36 37 /* INFRA resets */ 38 #define MT8186_INFRA_THERMAL_CTRL_RST 0 39 #define MT8186_INFRA_PTP_CTRL_RST 1 40 41 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ 42
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