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Linux/scripts/dtc/include-prefixes/dt-bindings/thermal/mediatek,lvts-thermal.h

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  1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*
  3  * Copyright (c) 2023 MediaTek Inc.
  4  * Author: Balsam CHIHI <bchihi@baylibre.com>
  5  */
  6 
  7 #ifndef __MEDIATEK_LVTS_DT_H
  8 #define __MEDIATEK_LVTS_DT_H
  9 
 10 #define MT7988_CPU_0            0
 11 #define MT7988_CPU_1            1
 12 #define MT7988_ETH2P5G_0        2
 13 #define MT7988_ETH2P5G_1        3
 14 #define MT7988_TOPS_0           4
 15 #define MT7988_TOPS_1           5
 16 #define MT7988_ETHWARP_0        6
 17 #define MT7988_ETHWARP_1        7
 18 
 19 #define MT8186_LITTLE_CPU0      0
 20 #define MT8186_LITTLE_CPU1      1
 21 #define MT8186_LITTLE_CPU2      2
 22 #define MT8186_CAM              3
 23 #define MT8186_BIG_CPU0 4
 24 #define MT8186_BIG_CPU1 5
 25 #define MT8186_NNA              6
 26 #define MT8186_ADSP             7
 27 #define MT8186_GPU              8
 28 
 29 #define MT8188_MCU_LITTLE_CPU0  0
 30 #define MT8188_MCU_LITTLE_CPU1  1
 31 #define MT8188_MCU_LITTLE_CPU2  2
 32 #define MT8188_MCU_LITTLE_CPU3  3
 33 #define MT8188_MCU_BIG_CPU0     4
 34 #define MT8188_MCU_BIG_CPU1     5
 35 
 36 #define MT8188_AP_APU           0
 37 #define MT8188_AP_GPU0          1
 38 #define MT8188_AP_GPU1          2
 39 #define MT8188_AP_ADSP          3
 40 #define MT8188_AP_VDO           4
 41 #define MT8188_AP_INFRA         5
 42 #define MT8188_AP_CAM1          6
 43 #define MT8188_AP_CAM2          7
 44 
 45 #define MT8195_MCU_BIG_CPU0     0
 46 #define MT8195_MCU_BIG_CPU1     1
 47 #define MT8195_MCU_BIG_CPU2     2
 48 #define MT8195_MCU_BIG_CPU3     3
 49 #define MT8195_MCU_LITTLE_CPU0  4
 50 #define MT8195_MCU_LITTLE_CPU1  5
 51 #define MT8195_MCU_LITTLE_CPU2  6
 52 #define MT8195_MCU_LITTLE_CPU3  7
 53 
 54 #define MT8195_AP_VPU0  8
 55 #define MT8195_AP_VPU1  9
 56 #define MT8195_AP_GPU0  10
 57 #define MT8195_AP_GPU1  11
 58 #define MT8195_AP_VDEC  12
 59 #define MT8195_AP_IMG   13
 60 #define MT8195_AP_INFRA 14
 61 #define MT8195_AP_CAM0  15
 62 #define MT8195_AP_CAM1  16
 63 
 64 #define MT8192_MCU_BIG_CPU0     0
 65 #define MT8192_MCU_BIG_CPU1     1
 66 #define MT8192_MCU_BIG_CPU2     2
 67 #define MT8192_MCU_BIG_CPU3     3
 68 #define MT8192_MCU_LITTLE_CPU0  4
 69 #define MT8192_MCU_LITTLE_CPU1  5
 70 #define MT8192_MCU_LITTLE_CPU2  6
 71 #define MT8192_MCU_LITTLE_CPU3  7
 72 
 73 #define MT8192_AP_VPU0  8
 74 #define MT8192_AP_VPU1  9
 75 #define MT8192_AP_GPU0  10
 76 #define MT8192_AP_GPU1  11
 77 #define MT8192_AP_INFRA 12
 78 #define MT8192_AP_CAM   13
 79 #define MT8192_AP_MD0   14
 80 #define MT8192_AP_MD1   15
 81 #define MT8192_AP_MD2   16
 82 
 83 #endif /* __MEDIATEK_LVTS_DT_H */
 84 

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