1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
5 */
6
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus: cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
19
20 cpu0: cpu@0 {
21 compatible = "thead,c906", "riscv";
22 device_type = "cpu";
23 reg = <0>;
24 d-cache-block-size = <64>;
25 d-cache-sets = <512>;
26 d-cache-size = <65536>;
27 i-cache-block-size = <64>;
28 i-cache-sets = <128>;
29 i-cache-size = <32768>;
30 mmu-type = "riscv,sv39";
31 riscv,isa = "rv64imafdc";
32 riscv,isa-base = "rv64i";
33 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 "zifencei", "zihpm";
35
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 };
41 };
42 };
43
44 osc: oscillator {
45 compatible = "fixed-clock";
46 clock-output-names = "osc_25m";
47 #clock-cells = <0>;
48 };
49
50 soc {
51 compatible = "simple-bus";
52 interrupt-parent = <&plic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
55 dma-noncoherent;
56 ranges;
57
58 clk: clock-controller@3002000 {
59 reg = <0x03002000 0x1000>;
60 clocks = <&osc>;
61 #clock-cells = <1>;
62 };
63
64 gpio0: gpio@3020000 {
65 compatible = "snps,dw-apb-gpio";
66 reg = <0x3020000 0x1000>;
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 porta: gpio-controller@0 {
71 compatible = "snps,dw-apb-gpio-port";
72 gpio-controller;
73 #gpio-cells = <2>;
74 ngpios = <32>;
75 reg = <0>;
76 interrupt-controller;
77 #interrupt-cells = <2>;
78 interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
79 };
80 };
81
82 gpio1: gpio@3021000 {
83 compatible = "snps,dw-apb-gpio";
84 reg = <0x3021000 0x1000>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87
88 portb: gpio-controller@0 {
89 compatible = "snps,dw-apb-gpio-port";
90 gpio-controller;
91 #gpio-cells = <2>;
92 ngpios = <32>;
93 reg = <0>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
97 };
98 };
99
100 gpio2: gpio@3022000 {
101 compatible = "snps,dw-apb-gpio";
102 reg = <0x3022000 0x1000>;
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 portc: gpio-controller@0 {
107 compatible = "snps,dw-apb-gpio-port";
108 gpio-controller;
109 #gpio-cells = <2>;
110 ngpios = <32>;
111 reg = <0>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
115 };
116 };
117
118 gpio3: gpio@3023000 {
119 compatible = "snps,dw-apb-gpio";
120 reg = <0x3023000 0x1000>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 portd: gpio-controller@0 {
125 compatible = "snps,dw-apb-gpio-port";
126 gpio-controller;
127 #gpio-cells = <2>;
128 ngpios = <32>;
129 reg = <0>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
133 };
134 };
135
136 i2c0: i2c@4000000 {
137 compatible = "snps,designware-i2c";
138 reg = <0x04000000 0x10000>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
142 clock-names = "ref", "pclk";
143 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
144 status = "disabled";
145 };
146
147 i2c1: i2c@4010000 {
148 compatible = "snps,designware-i2c";
149 reg = <0x04010000 0x10000>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
153 clock-names = "ref", "pclk";
154 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
155 status = "disabled";
156 };
157
158 i2c2: i2c@4020000 {
159 compatible = "snps,designware-i2c";
160 reg = <0x04020000 0x10000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
164 clock-names = "ref", "pclk";
165 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
166 status = "disabled";
167 };
168
169 i2c3: i2c@4030000 {
170 compatible = "snps,designware-i2c";
171 reg = <0x04030000 0x10000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
175 clock-names = "ref", "pclk";
176 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
177 status = "disabled";
178 };
179
180 i2c4: i2c@4040000 {
181 compatible = "snps,designware-i2c";
182 reg = <0x04040000 0x10000>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
186 clock-names = "ref", "pclk";
187 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
188 status = "disabled";
189 };
190
191 uart0: serial@4140000 {
192 compatible = "snps,dw-apb-uart";
193 reg = <0x04140000 0x100>;
194 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
196 clock-names = "baudclk", "apb_pclk";
197 reg-shift = <2>;
198 reg-io-width = <4>;
199 status = "disabled";
200 };
201
202 uart1: serial@4150000 {
203 compatible = "snps,dw-apb-uart";
204 reg = <0x04150000 0x100>;
205 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
207 clock-names = "baudclk", "apb_pclk";
208 reg-shift = <2>;
209 reg-io-width = <4>;
210 status = "disabled";
211 };
212
213 uart2: serial@4160000 {
214 compatible = "snps,dw-apb-uart";
215 reg = <0x04160000 0x100>;
216 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
218 clock-names = "baudclk", "apb_pclk";
219 reg-shift = <2>;
220 reg-io-width = <4>;
221 status = "disabled";
222 };
223
224 uart3: serial@4170000 {
225 compatible = "snps,dw-apb-uart";
226 reg = <0x04170000 0x100>;
227 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
229 clock-names = "baudclk", "apb_pclk";
230 reg-shift = <2>;
231 reg-io-width = <4>;
232 status = "disabled";
233 };
234
235 spi0: spi@4180000 {
236 compatible = "snps,dw-apb-ssi";
237 reg = <0x04180000 0x10000>;
238 #address-cells = <1>;
239 #size-cells = <0>;
240 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
241 clock-names = "ssi_clk", "pclk";
242 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
243 status = "disabled";
244 };
245
246 spi1: spi@4190000 {
247 compatible = "snps,dw-apb-ssi";
248 reg = <0x04190000 0x10000>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
252 clock-names = "ssi_clk", "pclk";
253 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
254 status = "disabled";
255 };
256
257 spi2: spi@41a0000 {
258 compatible = "snps,dw-apb-ssi";
259 reg = <0x041a0000 0x10000>;
260 #address-cells = <1>;
261 #size-cells = <0>;
262 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
263 clock-names = "ssi_clk", "pclk";
264 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
265 status = "disabled";
266 };
267
268 spi3: spi@41b0000 {
269 compatible = "snps,dw-apb-ssi";
270 reg = <0x041b0000 0x10000>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
274 clock-names = "ssi_clk", "pclk";
275 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
276 status = "disabled";
277 };
278
279 uart4: serial@41c0000 {
280 compatible = "snps,dw-apb-uart";
281 reg = <0x041c0000 0x100>;
282 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
284 clock-names = "baudclk", "apb_pclk";
285 reg-shift = <2>;
286 reg-io-width = <4>;
287 status = "disabled";
288 };
289
290 sdhci0: mmc@4310000 {
291 compatible = "sophgo,cv1800b-dwcmshc";
292 reg = <0x4310000 0x1000>;
293 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&clk CLK_AXI4_SD0>,
295 <&clk CLK_SD0>;
296 clock-names = "core", "bus";
297 status = "disabled";
298 };
299
300 dmac: dma-controller@4330000 {
301 compatible = "snps,axi-dma-1.01a";
302 reg = <0x04330000 0x1000>;
303 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
305 clock-names = "core-clk", "cfgr-clk";
306 #dma-cells = <1>;
307 dma-channels = <8>;
308 snps,block-size = <1024 1024 1024 1024
309 1024 1024 1024 1024>;
310 snps,priority = <0 1 2 3 4 5 6 7>;
311 snps,dma-masters = <2>;
312 snps,data-width = <4>;
313 status = "disabled";
314 };
315
316 plic: interrupt-controller@70000000 {
317 reg = <0x70000000 0x4000000>;
318 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
319 interrupt-controller;
320 #address-cells = <0>;
321 #interrupt-cells = <2>;
322 riscv,ndev = <101>;
323 };
324
325 clint: timer@74000000 {
326 reg = <0x74000000 0x10000>;
327 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
328 };
329 };
330 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.