1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
4 */
5
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
12
13 #include "sg2042-cpus.dtsi"
14
15 / {
16 compatible = "sophgo,sg2042";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 dma-noncoherent;
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 cgi_main: oscillator0 {
26 compatible = "fixed-clock";
27 clock-output-names = "cgi_main";
28 #clock-cells = <0>;
29 };
30
31 cgi_dpll0: oscillator1 {
32 compatible = "fixed-clock";
33 clock-output-names = "cgi_dpll0";
34 #clock-cells = <0>;
35 };
36
37 cgi_dpll1: oscillator2 {
38 compatible = "fixed-clock";
39 clock-output-names = "cgi_dpll1";
40 #clock-cells = <0>;
41 };
42
43 soc: soc {
44 compatible = "simple-bus";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 interrupt-parent = <&intc>;
48 ranges;
49
50 i2c0: i2c@7030005000 {
51 compatible = "snps,designware-i2c";
52 reg = <0x70 0x30005000 0x0 0x1000>;
53 #address-cells = <1>;
54 #size-cells = <0>;
55 clocks = <&clkgen GATE_CLK_APB_I2C>;
56 clock-names = "ref";
57 clock-frequency = <100000>;
58 interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
59 resets = <&rstgen RST_I2C0>;
60 status = "disabled";
61 };
62
63 i2c1: i2c@7030006000 {
64 compatible = "snps,designware-i2c";
65 reg = <0x70 0x30006000 0x0 0x1000>;
66 #address-cells = <1>;
67 #size-cells = <0>;
68 clocks = <&clkgen GATE_CLK_APB_I2C>;
69 clock-names = "ref";
70 clock-frequency = <100000>;
71 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
72 resets = <&rstgen RST_I2C1>;
73 status = "disabled";
74 };
75
76 i2c2: i2c@7030007000 {
77 compatible = "snps,designware-i2c";
78 reg = <0x70 0x30007000 0x0 0x1000>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81 clocks = <&clkgen GATE_CLK_APB_I2C>;
82 clock-names = "ref";
83 clock-frequency = <100000>;
84 interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
85 resets = <&rstgen RST_I2C2>;
86 status = "disabled";
87 };
88
89 i2c3: i2c@7030008000 {
90 compatible = "snps,designware-i2c";
91 reg = <0x70 0x30008000 0x0 0x1000>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 clocks = <&clkgen GATE_CLK_APB_I2C>;
95 clock-names = "ref";
96 clock-frequency = <100000>;
97 interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
98 resets = <&rstgen RST_I2C3>;
99 status = "disabled";
100 };
101
102 gpio0: gpio@7030009000 {
103 compatible = "snps,dw-apb-gpio";
104 reg = <0x70 0x30009000 0x0 0x400>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 clocks = <&clkgen GATE_CLK_APB_GPIO>,
108 <&clkgen GATE_CLK_GPIO_DB>;
109 clock-names = "bus", "db";
110
111 port0a: gpio-controller@0 {
112 compatible = "snps,dw-apb-gpio-port";
113 gpio-controller;
114 #gpio-cells = <2>;
115 ngpios = <32>;
116 reg = <0>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 interrupt-parent = <&intc>;
120 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
121 };
122 };
123
124 gpio1: gpio@703000a000 {
125 compatible = "snps,dw-apb-gpio";
126 reg = <0x70 0x3000a000 0x0 0x400>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 clocks = <&clkgen GATE_CLK_APB_GPIO>,
130 <&clkgen GATE_CLK_GPIO_DB>;
131 clock-names = "bus", "db";
132
133 port1a: gpio-controller@0 {
134 compatible = "snps,dw-apb-gpio-port";
135 gpio-controller;
136 #gpio-cells = <2>;
137 ngpios = <32>;
138 reg = <0>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 interrupt-parent = <&intc>;
142 interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
143 };
144 };
145
146 gpio2: gpio@703000b000 {
147 compatible = "snps,dw-apb-gpio";
148 reg = <0x70 0x3000b000 0x0 0x400>;
149 #address-cells = <1>;
150 #size-cells = <0>;
151 clocks = <&clkgen GATE_CLK_APB_GPIO>,
152 <&clkgen GATE_CLK_GPIO_DB>;
153 clock-names = "bus", "db";
154
155 port2a: gpio-controller@0 {
156 compatible = "snps,dw-apb-gpio-port";
157 gpio-controller;
158 #gpio-cells = <2>;
159 ngpios = <32>;
160 reg = <0>;
161 interrupt-controller;
162 #interrupt-cells = <2>;
163 interrupt-parent = <&intc>;
164 interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
165 };
166 };
167
168 pllclk: clock-controller@70300100c0 {
169 compatible = "sophgo,sg2042-pll";
170 reg = <0x70 0x300100c0 0x0 0x40>;
171 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
172 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
173 #clock-cells = <1>;
174 };
175
176 rpgate: clock-controller@7030010368 {
177 compatible = "sophgo,sg2042-rpgate";
178 reg = <0x70 0x30010368 0x0 0x98>;
179 clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
180 clock-names = "rpgate";
181 #clock-cells = <1>;
182 };
183
184 clkgen: clock-controller@7030012000 {
185 compatible = "sophgo,sg2042-clkgen";
186 reg = <0x70 0x30012000 0x0 0x1000>;
187 clocks = <&pllclk MPLL_CLK>,
188 <&pllclk FPLL_CLK>,
189 <&pllclk DPLL0_CLK>,
190 <&pllclk DPLL1_CLK>;
191 clock-names = "mpll",
192 "fpll",
193 "dpll0",
194 "dpll1";
195 #clock-cells = <1>;
196 };
197
198 clint_mswi: interrupt-controller@7094000000 {
199 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
200 reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
201 interrupts-extended = <&cpu0_intc 3>,
202 <&cpu1_intc 3>,
203 <&cpu2_intc 3>,
204 <&cpu3_intc 3>,
205 <&cpu4_intc 3>,
206 <&cpu5_intc 3>,
207 <&cpu6_intc 3>,
208 <&cpu7_intc 3>,
209 <&cpu8_intc 3>,
210 <&cpu9_intc 3>,
211 <&cpu10_intc 3>,
212 <&cpu11_intc 3>,
213 <&cpu12_intc 3>,
214 <&cpu13_intc 3>,
215 <&cpu14_intc 3>,
216 <&cpu15_intc 3>,
217 <&cpu16_intc 3>,
218 <&cpu17_intc 3>,
219 <&cpu18_intc 3>,
220 <&cpu19_intc 3>,
221 <&cpu20_intc 3>,
222 <&cpu21_intc 3>,
223 <&cpu22_intc 3>,
224 <&cpu23_intc 3>,
225 <&cpu24_intc 3>,
226 <&cpu25_intc 3>,
227 <&cpu26_intc 3>,
228 <&cpu27_intc 3>,
229 <&cpu28_intc 3>,
230 <&cpu29_intc 3>,
231 <&cpu30_intc 3>,
232 <&cpu31_intc 3>,
233 <&cpu32_intc 3>,
234 <&cpu33_intc 3>,
235 <&cpu34_intc 3>,
236 <&cpu35_intc 3>,
237 <&cpu36_intc 3>,
238 <&cpu37_intc 3>,
239 <&cpu38_intc 3>,
240 <&cpu39_intc 3>,
241 <&cpu40_intc 3>,
242 <&cpu41_intc 3>,
243 <&cpu42_intc 3>,
244 <&cpu43_intc 3>,
245 <&cpu44_intc 3>,
246 <&cpu45_intc 3>,
247 <&cpu46_intc 3>,
248 <&cpu47_intc 3>,
249 <&cpu48_intc 3>,
250 <&cpu49_intc 3>,
251 <&cpu50_intc 3>,
252 <&cpu51_intc 3>,
253 <&cpu52_intc 3>,
254 <&cpu53_intc 3>,
255 <&cpu54_intc 3>,
256 <&cpu55_intc 3>,
257 <&cpu56_intc 3>,
258 <&cpu57_intc 3>,
259 <&cpu58_intc 3>,
260 <&cpu59_intc 3>,
261 <&cpu60_intc 3>,
262 <&cpu61_intc 3>,
263 <&cpu62_intc 3>,
264 <&cpu63_intc 3>;
265 };
266
267 clint_mtimer0: timer@70ac004000 {
268 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
269 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
270 reg-names = "mtimecmp";
271 interrupts-extended = <&cpu0_intc 7>,
272 <&cpu1_intc 7>,
273 <&cpu2_intc 7>,
274 <&cpu3_intc 7>;
275 };
276
277 clint_mtimer1: timer@70ac014000 {
278 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
279 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
280 reg-names = "mtimecmp";
281 interrupts-extended = <&cpu4_intc 7>,
282 <&cpu5_intc 7>,
283 <&cpu6_intc 7>,
284 <&cpu7_intc 7>;
285 };
286
287 clint_mtimer2: timer@70ac024000 {
288 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
289 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
290 reg-names = "mtimecmp";
291 interrupts-extended = <&cpu8_intc 7>,
292 <&cpu9_intc 7>,
293 <&cpu10_intc 7>,
294 <&cpu11_intc 7>;
295 };
296
297 clint_mtimer3: timer@70ac034000 {
298 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
299 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
300 reg-names = "mtimecmp";
301 interrupts-extended = <&cpu12_intc 7>,
302 <&cpu13_intc 7>,
303 <&cpu14_intc 7>,
304 <&cpu15_intc 7>;
305 };
306
307 clint_mtimer4: timer@70ac044000 {
308 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
309 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
310 reg-names = "mtimecmp";
311 interrupts-extended = <&cpu16_intc 7>,
312 <&cpu17_intc 7>,
313 <&cpu18_intc 7>,
314 <&cpu19_intc 7>;
315 };
316
317 clint_mtimer5: timer@70ac054000 {
318 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
319 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
320 reg-names = "mtimecmp";
321 interrupts-extended = <&cpu20_intc 7>,
322 <&cpu21_intc 7>,
323 <&cpu22_intc 7>,
324 <&cpu23_intc 7>;
325 };
326
327 clint_mtimer6: timer@70ac064000 {
328 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
329 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
330 reg-names = "mtimecmp";
331 interrupts-extended = <&cpu24_intc 7>,
332 <&cpu25_intc 7>,
333 <&cpu26_intc 7>,
334 <&cpu27_intc 7>;
335 };
336
337 clint_mtimer7: timer@70ac074000 {
338 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
339 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
340 reg-names = "mtimecmp";
341 interrupts-extended = <&cpu28_intc 7>,
342 <&cpu29_intc 7>,
343 <&cpu30_intc 7>,
344 <&cpu31_intc 7>;
345 };
346
347 clint_mtimer8: timer@70ac084000 {
348 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
349 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
350 reg-names = "mtimecmp";
351 interrupts-extended = <&cpu32_intc 7>,
352 <&cpu33_intc 7>,
353 <&cpu34_intc 7>,
354 <&cpu35_intc 7>;
355 };
356
357 clint_mtimer9: timer@70ac094000 {
358 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
359 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
360 reg-names = "mtimecmp";
361 interrupts-extended = <&cpu36_intc 7>,
362 <&cpu37_intc 7>,
363 <&cpu38_intc 7>,
364 <&cpu39_intc 7>;
365 };
366
367 clint_mtimer10: timer@70ac0a4000 {
368 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
369 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
370 reg-names = "mtimecmp";
371 interrupts-extended = <&cpu40_intc 7>,
372 <&cpu41_intc 7>,
373 <&cpu42_intc 7>,
374 <&cpu43_intc 7>;
375 };
376
377 clint_mtimer11: timer@70ac0b4000 {
378 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
379 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
380 reg-names = "mtimecmp";
381 interrupts-extended = <&cpu44_intc 7>,
382 <&cpu45_intc 7>,
383 <&cpu46_intc 7>,
384 <&cpu47_intc 7>;
385 };
386
387 clint_mtimer12: timer@70ac0c4000 {
388 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
389 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
390 reg-names = "mtimecmp";
391 interrupts-extended = <&cpu48_intc 7>,
392 <&cpu49_intc 7>,
393 <&cpu50_intc 7>,
394 <&cpu51_intc 7>;
395 };
396
397 clint_mtimer13: timer@70ac0d4000 {
398 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
399 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
400 reg-names = "mtimecmp";
401 interrupts-extended = <&cpu52_intc 7>,
402 <&cpu53_intc 7>,
403 <&cpu54_intc 7>,
404 <&cpu55_intc 7>;
405 };
406
407 clint_mtimer14: timer@70ac0e4000 {
408 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
409 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
410 reg-names = "mtimecmp";
411 interrupts-extended = <&cpu56_intc 7>,
412 <&cpu57_intc 7>,
413 <&cpu58_intc 7>,
414 <&cpu59_intc 7>;
415 };
416
417 clint_mtimer15: timer@70ac0f4000 {
418 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
419 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
420 reg-names = "mtimecmp";
421 interrupts-extended = <&cpu60_intc 7>,
422 <&cpu61_intc 7>,
423 <&cpu62_intc 7>,
424 <&cpu63_intc 7>;
425 };
426
427 intc: interrupt-controller@7090000000 {
428 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
429 #address-cells = <0>;
430 #interrupt-cells = <2>;
431 reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
432 interrupt-controller;
433 interrupts-extended =
434 <&cpu0_intc 11>, <&cpu0_intc 9>,
435 <&cpu1_intc 11>, <&cpu1_intc 9>,
436 <&cpu2_intc 11>, <&cpu2_intc 9>,
437 <&cpu3_intc 11>, <&cpu3_intc 9>,
438 <&cpu4_intc 11>, <&cpu4_intc 9>,
439 <&cpu5_intc 11>, <&cpu5_intc 9>,
440 <&cpu6_intc 11>, <&cpu6_intc 9>,
441 <&cpu7_intc 11>, <&cpu7_intc 9>,
442 <&cpu8_intc 11>, <&cpu8_intc 9>,
443 <&cpu9_intc 11>, <&cpu9_intc 9>,
444 <&cpu10_intc 11>, <&cpu10_intc 9>,
445 <&cpu11_intc 11>, <&cpu11_intc 9>,
446 <&cpu12_intc 11>, <&cpu12_intc 9>,
447 <&cpu13_intc 11>, <&cpu13_intc 9>,
448 <&cpu14_intc 11>, <&cpu14_intc 9>,
449 <&cpu15_intc 11>, <&cpu15_intc 9>,
450 <&cpu16_intc 11>, <&cpu16_intc 9>,
451 <&cpu17_intc 11>, <&cpu17_intc 9>,
452 <&cpu18_intc 11>, <&cpu18_intc 9>,
453 <&cpu19_intc 11>, <&cpu19_intc 9>,
454 <&cpu20_intc 11>, <&cpu20_intc 9>,
455 <&cpu21_intc 11>, <&cpu21_intc 9>,
456 <&cpu22_intc 11>, <&cpu22_intc 9>,
457 <&cpu23_intc 11>, <&cpu23_intc 9>,
458 <&cpu24_intc 11>, <&cpu24_intc 9>,
459 <&cpu25_intc 11>, <&cpu25_intc 9>,
460 <&cpu26_intc 11>, <&cpu26_intc 9>,
461 <&cpu27_intc 11>, <&cpu27_intc 9>,
462 <&cpu28_intc 11>, <&cpu28_intc 9>,
463 <&cpu29_intc 11>, <&cpu29_intc 9>,
464 <&cpu30_intc 11>, <&cpu30_intc 9>,
465 <&cpu31_intc 11>, <&cpu31_intc 9>,
466 <&cpu32_intc 11>, <&cpu32_intc 9>,
467 <&cpu33_intc 11>, <&cpu33_intc 9>,
468 <&cpu34_intc 11>, <&cpu34_intc 9>,
469 <&cpu35_intc 11>, <&cpu35_intc 9>,
470 <&cpu36_intc 11>, <&cpu36_intc 9>,
471 <&cpu37_intc 11>, <&cpu37_intc 9>,
472 <&cpu38_intc 11>, <&cpu38_intc 9>,
473 <&cpu39_intc 11>, <&cpu39_intc 9>,
474 <&cpu40_intc 11>, <&cpu40_intc 9>,
475 <&cpu41_intc 11>, <&cpu41_intc 9>,
476 <&cpu42_intc 11>, <&cpu42_intc 9>,
477 <&cpu43_intc 11>, <&cpu43_intc 9>,
478 <&cpu44_intc 11>, <&cpu44_intc 9>,
479 <&cpu45_intc 11>, <&cpu45_intc 9>,
480 <&cpu46_intc 11>, <&cpu46_intc 9>,
481 <&cpu47_intc 11>, <&cpu47_intc 9>,
482 <&cpu48_intc 11>, <&cpu48_intc 9>,
483 <&cpu49_intc 11>, <&cpu49_intc 9>,
484 <&cpu50_intc 11>, <&cpu50_intc 9>,
485 <&cpu51_intc 11>, <&cpu51_intc 9>,
486 <&cpu52_intc 11>, <&cpu52_intc 9>,
487 <&cpu53_intc 11>, <&cpu53_intc 9>,
488 <&cpu54_intc 11>, <&cpu54_intc 9>,
489 <&cpu55_intc 11>, <&cpu55_intc 9>,
490 <&cpu56_intc 11>, <&cpu56_intc 9>,
491 <&cpu57_intc 11>, <&cpu57_intc 9>,
492 <&cpu58_intc 11>, <&cpu58_intc 9>,
493 <&cpu59_intc 11>, <&cpu59_intc 9>,
494 <&cpu60_intc 11>, <&cpu60_intc 9>,
495 <&cpu61_intc 11>, <&cpu61_intc 9>,
496 <&cpu62_intc 11>, <&cpu62_intc 9>,
497 <&cpu63_intc 11>, <&cpu63_intc 9>;
498 riscv,ndev = <224>;
499 };
500
501 rstgen: reset-controller@7030013000 {
502 compatible = "sophgo,sg2042-reset";
503 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
504 #reset-cells = <1>;
505 };
506
507 uart0: serial@7040000000 {
508 compatible = "snps,dw-apb-uart";
509 reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
510 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
511 clock-frequency = <500000000>;
512 clocks = <&clkgen GATE_CLK_UART_500M>,
513 <&clkgen GATE_CLK_APB_UART>;
514 clock-names = "baudclk", "apb_pclk";
515 reg-shift = <2>;
516 reg-io-width = <4>;
517 resets = <&rstgen RST_UART0>;
518 status = "disabled";
519 };
520
521 emmc: mmc@704002a000 {
522 compatible = "sophgo,sg2042-dwcmshc";
523 reg = <0x70 0x4002a000 0x0 0x1000>;
524 interrupt-parent = <&intc>;
525 interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clkgen GATE_CLK_EMMC_100M>,
527 <&clkgen GATE_CLK_AXI_EMMC>,
528 <&clkgen GATE_CLK_100K_EMMC>;
529 clock-names = "core",
530 "bus",
531 "timer";
532 status = "disabled";
533 };
534
535 sd: mmc@704002b000 {
536 compatible = "sophgo,sg2042-dwcmshc";
537 reg = <0x70 0x4002b000 0x0 0x1000>;
538 interrupt-parent = <&intc>;
539 interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clkgen GATE_CLK_SD_100M>,
541 <&clkgen GATE_CLK_AXI_SD>,
542 <&clkgen GATE_CLK_100K_SD>;
543 clock-names = "core",
544 "bus",
545 "timer";
546 status = "disabled";
547 };
548 };
549 };
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