1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HD-audio controller helpers
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_register.h>
12 #include "local.h"
13
14 /* clear CORB read pointer properly */
15 static void azx_clear_corbrp(struct hdac_bus *bus)
16 {
17 int timeout;
18
19 for (timeout = 1000; timeout > 0; timeout--) {
20 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
21 break;
22 udelay(1);
23 }
24 if (timeout <= 0)
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
26 snd_hdac_chip_readw(bus, CORBRP));
27
28 snd_hdac_chip_writew(bus, CORBRP, 0);
29 for (timeout = 1000; timeout > 0; timeout--) {
30 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
31 break;
32 udelay(1);
33 }
34 if (timeout <= 0)
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
36 snd_hdac_chip_readw(bus, CORBRP));
37 }
38
39 /**
40 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
41 * @bus: HD-audio core bus
42 */
43 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
44 {
45 WARN_ON_ONCE(!bus->rb.area);
46
47 spin_lock_irq(&bus->reg_lock);
48 /* CORB set up */
49 bus->corb.addr = bus->rb.addr;
50 bus->corb.buf = (__le32 *)bus->rb.area;
51 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
52 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
53
54 /* set the corb size to 256 entries (ULI requires explicitly) */
55 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
56 /* set the corb write pointer to 0 */
57 snd_hdac_chip_writew(bus, CORBWP, 0);
58
59 /* reset the corb hw read pointer */
60 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
61 if (!bus->corbrp_self_clear)
62 azx_clear_corbrp(bus);
63
64 /* enable corb dma */
65 if (!bus->use_pio_for_commands)
66 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
67
68 /* RIRB set up */
69 bus->rirb.addr = bus->rb.addr + 2048;
70 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
71 bus->rirb.wp = bus->rirb.rp = 0;
72 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
73 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
74 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
75
76 /* set the rirb size to 256 entries (ULI requires explicitly) */
77 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
78 /* reset the rirb hw write pointer */
79 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
80 /* set N=1, get RIRB response interrupt for new entry */
81 snd_hdac_chip_writew(bus, RINTCNT, 1);
82 /* enable rirb dma and response irq */
83 if (bus->not_use_interrupts)
84 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
85 else
86 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
87 /* Accept unsolicited responses */
88 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
89 spin_unlock_irq(&bus->reg_lock);
90 }
91 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
92
93 /* wait for cmd dmas till they are stopped */
94 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
95 {
96 unsigned long timeout;
97
98 timeout = jiffies + msecs_to_jiffies(100);
99 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
100 && time_before(jiffies, timeout))
101 udelay(10);
102
103 timeout = jiffies + msecs_to_jiffies(100);
104 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
105 && time_before(jiffies, timeout))
106 udelay(10);
107 }
108
109 /**
110 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
111 * @bus: HD-audio core bus
112 */
113 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
114 {
115 spin_lock_irq(&bus->reg_lock);
116 /* disable ringbuffer DMAs */
117 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
118 snd_hdac_chip_writeb(bus, CORBCTL, 0);
119 spin_unlock_irq(&bus->reg_lock);
120
121 hdac_wait_for_cmd_dmas(bus);
122
123 spin_lock_irq(&bus->reg_lock);
124 /* disable unsolicited responses */
125 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
126 spin_unlock_irq(&bus->reg_lock);
127 }
128 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
129
130 static unsigned int azx_command_addr(u32 cmd)
131 {
132 unsigned int addr = cmd >> 28;
133
134 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
135 addr = 0;
136 return addr;
137 }
138
139 /* receive an Immediate Response with PIO */
140 static int snd_hdac_bus_wait_for_pio_response(struct hdac_bus *bus,
141 unsigned int addr)
142 {
143 int timeout = 50;
144
145 while (timeout--) {
146 /* check IRV bit */
147 if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) {
148 /* reuse rirb.res as the response return value */
149 bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR);
150 return 0;
151 }
152 udelay(1);
153 }
154
155 dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n",
156 snd_hdac_chip_readw(bus, IRS));
157
158 bus->rirb.res[addr] = -1;
159
160 return -EIO;
161 }
162
163 /**
164 * snd_hdac_bus_send_cmd_pio - send a command verb via Immediate Command
165 * @bus: HD-audio core bus
166 * @val: encoded verb value to send
167 *
168 * Returns zero for success or a negative error code.
169 */
170 static int snd_hdac_bus_send_cmd_pio(struct hdac_bus *bus, unsigned int val)
171 {
172 unsigned int addr = azx_command_addr(val);
173 int timeout = 50;
174 int ret = -EIO;
175
176 spin_lock_irq(&bus->reg_lock);
177
178 while (timeout--) {
179 /* check ICB bit */
180 if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) {
181 /* Clear IRV bit */
182 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID);
183 snd_hdac_chip_writel(bus, IC, val);
184 /* Set ICB bit */
185 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY);
186
187 ret = snd_hdac_bus_wait_for_pio_response(bus, addr);
188 goto out;
189 }
190 udelay(1);
191 }
192
193 dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n",
194 snd_hdac_chip_readw(bus, IRS), val);
195
196 out:
197 spin_unlock_irq(&bus->reg_lock);
198
199 return ret;
200 }
201
202 /**
203 * snd_hdac_bus_get_response_pio - receive a response via Immediate Response
204 * @bus: HD-audio core bus
205 * @addr: codec address
206 * @res: pointer to store the value, NULL when not needed
207 *
208 * Returns zero if a value is read, or a negative error code.
209 */
210 static int snd_hdac_bus_get_response_pio(struct hdac_bus *bus,
211 unsigned int addr, unsigned int *res)
212 {
213 if (res)
214 *res = bus->rirb.res[addr];
215
216 return 0;
217 }
218
219 /**
220 * snd_hdac_bus_send_cmd_corb - send a command verb via CORB
221 * @bus: HD-audio core bus
222 * @val: encoded verb value to send
223 *
224 * Returns zero for success or a negative error code.
225 */
226 static int snd_hdac_bus_send_cmd_corb(struct hdac_bus *bus, unsigned int val)
227 {
228 unsigned int addr = azx_command_addr(val);
229 unsigned int wp, rp;
230
231 spin_lock_irq(&bus->reg_lock);
232
233 bus->last_cmd[azx_command_addr(val)] = val;
234
235 /* add command to corb */
236 wp = snd_hdac_chip_readw(bus, CORBWP);
237 if (wp == 0xffff) {
238 /* something wrong, controller likely turned to D3 */
239 spin_unlock_irq(&bus->reg_lock);
240 return -EIO;
241 }
242 wp++;
243 wp %= AZX_MAX_CORB_ENTRIES;
244
245 rp = snd_hdac_chip_readw(bus, CORBRP);
246 if (wp == rp) {
247 /* oops, it's full */
248 spin_unlock_irq(&bus->reg_lock);
249 return -EAGAIN;
250 }
251
252 bus->rirb.cmds[addr]++;
253 bus->corb.buf[wp] = cpu_to_le32(val);
254 snd_hdac_chip_writew(bus, CORBWP, wp);
255
256 spin_unlock_irq(&bus->reg_lock);
257
258 return 0;
259 }
260
261 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
262
263 /**
264 * snd_hdac_bus_update_rirb - retrieve RIRB entries
265 * @bus: HD-audio core bus
266 *
267 * Usually called from interrupt handler.
268 * The caller needs bus->reg_lock spinlock before calling this.
269 */
270 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
271 {
272 unsigned int rp, wp;
273 unsigned int addr;
274 u32 res, res_ex;
275
276 wp = snd_hdac_chip_readw(bus, RIRBWP);
277 if (wp == 0xffff) {
278 /* something wrong, controller likely turned to D3 */
279 return;
280 }
281
282 if (wp == bus->rirb.wp)
283 return;
284 bus->rirb.wp = wp;
285
286 while (bus->rirb.rp != wp) {
287 bus->rirb.rp++;
288 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
289
290 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
291 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
292 res = le32_to_cpu(bus->rirb.buf[rp]);
293 addr = res_ex & 0xf;
294 if (addr >= HDA_MAX_CODECS) {
295 dev_err(bus->dev,
296 "spurious response %#x:%#x, rp = %d, wp = %d",
297 res, res_ex, bus->rirb.rp, wp);
298 snd_BUG();
299 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
300 snd_hdac_bus_queue_event(bus, res, res_ex);
301 else if (bus->rirb.cmds[addr]) {
302 bus->rirb.res[addr] = res;
303 bus->rirb.cmds[addr]--;
304 if (!bus->rirb.cmds[addr] &&
305 waitqueue_active(&bus->rirb_wq))
306 wake_up(&bus->rirb_wq);
307 } else {
308 dev_err_ratelimited(bus->dev,
309 "spurious response %#x:%#x, last cmd=%#08x\n",
310 res, res_ex, bus->last_cmd[addr]);
311 }
312 }
313 }
314 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
315
316 /**
317 * snd_hdac_bus_get_response_rirb - receive a response via RIRB
318 * @bus: HD-audio core bus
319 * @addr: codec address
320 * @res: pointer to store the value, NULL when not needed
321 *
322 * Returns zero if a value is read, or a negative error code.
323 */
324 static int snd_hdac_bus_get_response_rirb(struct hdac_bus *bus,
325 unsigned int addr, unsigned int *res)
326 {
327 unsigned long timeout;
328 unsigned long loopcounter;
329 wait_queue_entry_t wait;
330 bool warned = false;
331
332 init_wait_entry(&wait, 0);
333 timeout = jiffies + msecs_to_jiffies(1000);
334
335 for (loopcounter = 0;; loopcounter++) {
336 spin_lock_irq(&bus->reg_lock);
337 if (!bus->polling_mode)
338 prepare_to_wait(&bus->rirb_wq, &wait,
339 TASK_UNINTERRUPTIBLE);
340 if (bus->polling_mode)
341 snd_hdac_bus_update_rirb(bus);
342 if (!bus->rirb.cmds[addr]) {
343 if (res)
344 *res = bus->rirb.res[addr]; /* the last value */
345 if (!bus->polling_mode)
346 finish_wait(&bus->rirb_wq, &wait);
347 spin_unlock_irq(&bus->reg_lock);
348 return 0;
349 }
350 spin_unlock_irq(&bus->reg_lock);
351 if (time_after(jiffies, timeout))
352 break;
353 #define LOOP_COUNT_MAX 3000
354 if (!bus->polling_mode) {
355 schedule_timeout(msecs_to_jiffies(2));
356 } else if (bus->needs_damn_long_delay ||
357 loopcounter > LOOP_COUNT_MAX) {
358 if (loopcounter > LOOP_COUNT_MAX && !warned) {
359 dev_dbg_ratelimited(bus->dev,
360 "too slow response, last cmd=%#08x\n",
361 bus->last_cmd[addr]);
362 warned = true;
363 }
364 msleep(2); /* temporary workaround */
365 } else {
366 udelay(10);
367 cond_resched();
368 }
369 }
370
371 if (!bus->polling_mode)
372 finish_wait(&bus->rirb_wq, &wait);
373
374 return -EIO;
375 }
376
377 /**
378 * snd_hdac_bus_send_cmd - send a command verb via CORB or PIO
379 * @bus: HD-audio core bus
380 * @val: encoded verb value to send
381 *
382 * Returns zero for success or a negative error code.
383 */
384 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
385 {
386 if (bus->use_pio_for_commands)
387 return snd_hdac_bus_send_cmd_pio(bus, val);
388
389 return snd_hdac_bus_send_cmd_corb(bus, val);
390 }
391 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
392
393 /**
394 * snd_hdac_bus_get_response - receive a response via RIRB or PIO
395 * @bus: HD-audio core bus
396 * @addr: codec address
397 * @res: pointer to store the value, NULL when not needed
398 *
399 * Returns zero if a value is read, or a negative error code.
400 */
401 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
402 unsigned int *res)
403 {
404 if (bus->use_pio_for_commands)
405 return snd_hdac_bus_get_response_pio(bus, addr, res);
406
407 return snd_hdac_bus_get_response_rirb(bus, addr, res);
408 }
409 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
410
411 #define HDAC_MAX_CAPS 10
412 /**
413 * snd_hdac_bus_parse_capabilities - parse capability structure
414 * @bus: the pointer to bus object
415 *
416 * Returns 0 if successful, or a negative error code.
417 */
418 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
419 {
420 unsigned int cur_cap;
421 unsigned int offset;
422 unsigned int counter = 0;
423
424 offset = snd_hdac_chip_readw(bus, LLCH);
425
426 /* Lets walk the linked capabilities list */
427 do {
428 cur_cap = _snd_hdac_chip_readl(bus, offset);
429
430 dev_dbg(bus->dev, "Capability version: 0x%x\n",
431 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
432
433 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
434 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
435
436 if (cur_cap == -1) {
437 dev_dbg(bus->dev, "Invalid capability reg read\n");
438 break;
439 }
440
441 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
442 case AZX_ML_CAP_ID:
443 dev_dbg(bus->dev, "Found ML capability\n");
444 bus->mlcap = bus->remap_addr + offset;
445 break;
446
447 case AZX_GTS_CAP_ID:
448 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
449 bus->gtscap = bus->remap_addr + offset;
450 break;
451
452 case AZX_PP_CAP_ID:
453 /* PP capability found, the Audio DSP is present */
454 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
455 bus->ppcap = bus->remap_addr + offset;
456 break;
457
458 case AZX_SPB_CAP_ID:
459 /* SPIB capability found, handler function */
460 dev_dbg(bus->dev, "Found SPB capability\n");
461 bus->spbcap = bus->remap_addr + offset;
462 break;
463
464 case AZX_DRSM_CAP_ID:
465 /* DMA resume capability found, handler function */
466 dev_dbg(bus->dev, "Found DRSM capability\n");
467 bus->drsmcap = bus->remap_addr + offset;
468 break;
469
470 default:
471 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
472 cur_cap = 0;
473 break;
474 }
475
476 counter++;
477
478 if (counter > HDAC_MAX_CAPS) {
479 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
480 break;
481 }
482
483 /* read the offset of next capability */
484 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
485
486 } while (offset);
487
488 return 0;
489 }
490 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
491
492 /*
493 * Lowlevel interface
494 */
495
496 /**
497 * snd_hdac_bus_enter_link_reset - enter link reset
498 * @bus: HD-audio core bus
499 *
500 * Enter to the link reset state.
501 */
502 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
503 {
504 unsigned long timeout;
505
506 /* reset controller */
507 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
508
509 timeout = jiffies + msecs_to_jiffies(100);
510 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
511 time_before(jiffies, timeout))
512 usleep_range(500, 1000);
513 }
514 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
515
516 /**
517 * snd_hdac_bus_exit_link_reset - exit link reset
518 * @bus: HD-audio core bus
519 *
520 * Exit from the link reset state.
521 */
522 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
523 {
524 unsigned long timeout;
525
526 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
527
528 timeout = jiffies + msecs_to_jiffies(100);
529 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
530 usleep_range(500, 1000);
531 }
532 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
533
534 /* reset codec link */
535 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
536 {
537 if (!full_reset)
538 goto skip_reset;
539
540 /* clear STATESTS if not in reset */
541 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
542 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
543
544 /* reset controller */
545 snd_hdac_bus_enter_link_reset(bus);
546
547 /* delay for >= 100us for codec PLL to settle per spec
548 * Rev 0.9 section 5.5.1
549 */
550 usleep_range(500, 1000);
551
552 /* Bring controller out of reset */
553 snd_hdac_bus_exit_link_reset(bus);
554
555 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
556 usleep_range(1000, 1200);
557
558 skip_reset:
559 /* check to see if controller is ready */
560 if (!snd_hdac_chip_readb(bus, GCTL)) {
561 dev_dbg(bus->dev, "controller not ready!\n");
562 return -EBUSY;
563 }
564
565 /* detect codecs */
566 if (!bus->codec_mask) {
567 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
568 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
569 }
570
571 return 0;
572 }
573 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
574
575 /* enable interrupts */
576 static void azx_int_enable(struct hdac_bus *bus)
577 {
578 /* enable controller CIE and GIE */
579 snd_hdac_chip_updatel(bus, INTCTL,
580 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
581 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
582 }
583
584 /* disable interrupts */
585 static void azx_int_disable(struct hdac_bus *bus)
586 {
587 struct hdac_stream *azx_dev;
588
589 /* disable interrupts in stream descriptor */
590 list_for_each_entry(azx_dev, &bus->stream_list, list)
591 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
592
593 /* disable SIE for all streams & disable controller CIE and GIE */
594 snd_hdac_chip_writel(bus, INTCTL, 0);
595 }
596
597 /* clear interrupts */
598 static void azx_int_clear(struct hdac_bus *bus)
599 {
600 struct hdac_stream *azx_dev;
601
602 /* clear stream status */
603 list_for_each_entry(azx_dev, &bus->stream_list, list)
604 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
605
606 /* clear STATESTS */
607 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
608
609 /* clear rirb status */
610 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
611
612 /* clear int status */
613 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
614 }
615
616 /**
617 * snd_hdac_bus_init_chip - reset and start the controller registers
618 * @bus: HD-audio core bus
619 * @full_reset: Do full reset
620 */
621 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
622 {
623 if (bus->chip_init)
624 return false;
625
626 /* reset controller */
627 snd_hdac_bus_reset_link(bus, full_reset);
628
629 /* clear interrupts */
630 azx_int_clear(bus);
631
632 /* initialize the codec command I/O */
633 snd_hdac_bus_init_cmd_io(bus);
634
635 /* enable interrupts after CORB/RIRB buffers are initialized above */
636 azx_int_enable(bus);
637
638 /* program the position buffer */
639 if (bus->use_posbuf && bus->posbuf.addr) {
640 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
641 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
642 }
643
644 bus->chip_init = true;
645
646 return true;
647 }
648 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
649
650 /**
651 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
652 * @bus: HD-audio core bus
653 */
654 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
655 {
656 if (!bus->chip_init)
657 return;
658
659 /* disable interrupts */
660 azx_int_disable(bus);
661 azx_int_clear(bus);
662
663 /* disable CORB/RIRB */
664 snd_hdac_bus_stop_cmd_io(bus);
665
666 /* disable position buffer */
667 if (bus->posbuf.addr) {
668 snd_hdac_chip_writel(bus, DPLBASE, 0);
669 snd_hdac_chip_writel(bus, DPUBASE, 0);
670 }
671
672 bus->chip_init = false;
673 }
674 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
675
676 /**
677 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
678 * @bus: HD-audio core bus
679 * @status: INTSTS register value
680 * @ack: callback to be called for woken streams
681 *
682 * Returns the bits of handled streams, or zero if no stream is handled.
683 */
684 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
685 void (*ack)(struct hdac_bus *,
686 struct hdac_stream *))
687 {
688 struct hdac_stream *azx_dev;
689 u8 sd_status;
690 int handled = 0;
691
692 list_for_each_entry(azx_dev, &bus->stream_list, list) {
693 if (status & azx_dev->sd_int_sta_mask) {
694 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
695 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
696 handled |= 1 << azx_dev->index;
697 if ((!azx_dev->substream && !azx_dev->cstream) ||
698 !azx_dev->running || !(sd_status & SD_INT_COMPLETE))
699 continue;
700 if (ack)
701 ack(bus, azx_dev);
702 }
703 }
704 return handled;
705 }
706 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
707
708 /**
709 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
710 * @bus: HD-audio core bus
711 *
712 * Call this after assigning the all streams.
713 * Returns zero for success, or a negative error code.
714 */
715 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
716 {
717 struct hdac_stream *s;
718 int num_streams = 0;
719 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
720 int err;
721
722 list_for_each_entry(s, &bus->stream_list, list) {
723 /* allocate memory for the BDL for each stream */
724 err = snd_dma_alloc_pages(dma_type, bus->dev,
725 BDL_SIZE, &s->bdl);
726 num_streams++;
727 if (err < 0)
728 return -ENOMEM;
729 }
730
731 if (WARN_ON(!num_streams))
732 return -EINVAL;
733 /* allocate memory for the position buffer */
734 err = snd_dma_alloc_pages(dma_type, bus->dev,
735 num_streams * 8, &bus->posbuf);
736 if (err < 0)
737 return -ENOMEM;
738 list_for_each_entry(s, &bus->stream_list, list)
739 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
740
741 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
742 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
743 }
744 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
745
746 /**
747 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
748 * @bus: HD-audio core bus
749 */
750 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
751 {
752 struct hdac_stream *s;
753
754 list_for_each_entry(s, &bus->stream_list, list) {
755 if (s->bdl.area)
756 snd_dma_free_pages(&s->bdl);
757 }
758
759 if (bus->rb.area)
760 snd_dma_free_pages(&bus->rb);
761 if (bus->posbuf.area)
762 snd_dma_free_pages(&bus->posbuf);
763 }
764 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);
765
766 /**
767 * snd_hdac_bus_link_power - power up/down codec link
768 * @codec: HD-audio device
769 * @enable: whether to power-up the link
770 */
771 void snd_hdac_bus_link_power(struct hdac_device *codec, bool enable)
772 {
773 if (enable)
774 set_bit(codec->addr, &codec->bus->codec_powered);
775 else
776 clear_bit(codec->addr, &codec->bus->codec_powered);
777 }
778 EXPORT_SYMBOL_GPL(snd_hdac_bus_link_power);
779
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.