1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
5 */
6
7 /*
8 * 2002-07 Benny Sjostrand benny@hostmobility.com
9 */
10
11 #ifdef CONFIG_SND_CS46XX_NEW_DSP /* hack ... */
12 #ifndef __DSP_SPOS_H__
13 #define __DSP_SPOS_H__
14
15 #define DSP_MAX_SYMBOLS 1024
16 #define DSP_MAX_MODULES 64
17
18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
24
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
27
28 /* this instruction types
29 needs to be reallocated when load
30 code into DSP */
31 enum wide_opcode {
32 WIDE_FOR_BEGIN_LOOP = 0x20,
33 WIDE_FOR_BEGIN_LOOP2,
34
35 WIDE_COND_GOTO_ADDR = 0x30,
36 WIDE_COND_GOTO_CALL,
37
38 WIDE_TBEQ_COND_GOTO_ADDR = 0x70,
39 WIDE_TBEQ_COND_CALL_ADDR,
40 WIDE_TBEQ_NCOND_GOTO_ADDR,
41 WIDE_TBEQ_NCOND_CALL_ADDR,
42 WIDE_TBEQ_COND_GOTO1_ADDR,
43 WIDE_TBEQ_COND_CALL1_ADDR,
44 WIDE_TBEQ_NCOND_GOTOI_ADDR,
45 WIDE_TBEQ_NCOND_CALL1_ADDR,
46 };
47
48 /* SAMPLE segment */
49 #define VARI_DECIMATE_BUF1 0x0000
50 #define WRITE_BACK_BUF1 0x0400
51 #define CODEC_INPUT_BUF1 0x0500
52 #define PCM_READER_BUF1 0x0600
53 #define SRC_DELAY_BUF1 0x0680
54 #define VARI_DECIMATE_BUF0 0x0780
55 #define SRC_OUTPUT_BUF1 0x07A0
56 #define ASYNC_IP_OUTPUT_BUFFER1 0x0A00
57 #define OUTPUT_SNOOP_BUFFER 0x0B00
58 #define SPDIFI_IP_OUTPUT_BUFFER1 0x0E00
59 #define SPDIFO_IP_OUTPUT_BUFFER1 0x1000
60 #define MIX_SAMPLE_BUF1 0x1400
61 #define MIX_SAMPLE_BUF2 0x2E80
62 #define MIX_SAMPLE_BUF3 0x2F00
63 #define MIX_SAMPLE_BUF4 0x2F80
64 #define MIX_SAMPLE_BUF5 0x3000
65
66 /* Task stack address */
67 #define HFG_STACK 0x066A
68 #define FG_STACK 0x066E
69 #define BG_STACK 0x068E
70
71 /* SCB's addresses */
72 #define SPOSCB_ADDR 0x070
73 #define BG_TREE_SCB_ADDR 0x635
74 #define NULL_SCB_ADDR 0x000
75 #define TIMINGMASTER_SCB_ADDR 0x010
76 #define CODECOUT_SCB_ADDR 0x020
77 #define PCMREADER_SCB_ADDR 0x030
78 #define WRITEBACK_SCB_ADDR 0x040
79 #define CODECIN_SCB_ADDR 0x080
80 #define MASTERMIX_SCB_ADDR 0x090
81 #define SRCTASK_SCB_ADDR 0x0A0
82 #define VARIDECIMATE_SCB_ADDR 0x0B0
83 #define PCMSERIALIN_SCB_ADDR 0x0C0
84 #define FG_TASK_HEADER_ADDR 0x600
85 #define ASYNCTX_SCB_ADDR 0x0E0
86 #define ASYNCRX_SCB_ADDR 0x0F0
87 #define SRCTASKII_SCB_ADDR 0x100
88 #define OUTPUTSNOOP_SCB_ADDR 0x110
89 #define PCMSERIALINII_SCB_ADDR 0x120
90 #define SPIOWRITE_SCB_ADDR 0x130
91 #define REAR_CODECOUT_SCB_ADDR 0x140
92 #define OUTPUTSNOOPII_SCB_ADDR 0x150
93 #define PCMSERIALIN_PCM_SCB_ADDR 0x160
94 #define RECORD_MIXER_SCB_ADDR 0x170
95 #define REAR_MIXER_SCB_ADDR 0x180
96 #define CLFE_MIXER_SCB_ADDR 0x190
97 #define CLFE_CODEC_SCB_ADDR 0x1A0
98
99 /* hyperforground SCB's*/
100 #define HFG_TREE_SCB 0xBA0
101 #define SPDIFI_SCB_INST 0xBB0
102 #define SPDIFO_SCB_INST 0xBC0
103 #define WRITE_BACK_SPB 0x0D0
104
105 /* offsets */
106 #define AsyncCIOFIFOPointer 0xd
107 #define SPDIFOFIFOPointer 0xd
108 #define SPDIFIFIFOPointer 0xd
109 #define TCBData 0xb
110 #define HFGFlags 0xa
111 #define TCBContextBlk 0x10
112 #define AFGTxAccumPhi 0x4
113 #define SCBsubListPtr 0x9
114 #define SCBfuncEntryPtr 0xA
115 #define SRCCorPerGof 0x2
116 #define SRCPhiIncr6Int26Frac 0xd
117 #define SCBVolumeCtrl 0xe
118
119 /* conf */
120 #define UseASER1Input 1
121
122
123
124 /*
125 * The following defines are for the flags in the rsConfig01/23 registers of
126 * the SP.
127 */
128
129 #define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL
130 #define RSCONFIG_MODULO_16 0x00000001L
131 #define RSCONFIG_MODULO_32 0x00000002L
132 #define RSCONFIG_MODULO_64 0x00000003L
133 #define RSCONFIG_MODULO_128 0x00000004L
134 #define RSCONFIG_MODULO_256 0x00000005L
135 #define RSCONFIG_MODULO_512 0x00000006L
136 #define RSCONFIG_MODULO_1024 0x00000007L
137 #define RSCONFIG_MODULO_4 0x00000008L
138 #define RSCONFIG_MODULO_8 0x00000009L
139 #define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L
140 #define RSCONFIG_SAMPLE_8MONO 0x00000000L
141 #define RSCONFIG_SAMPLE_8STEREO 0x00000040L
142 #define RSCONFIG_SAMPLE_16MONO 0x00000080L
143 #define RSCONFIG_SAMPLE_16STEREO 0x000000C0L
144 #define RSCONFIG_UNDERRUN_ZERO 0x00004000L
145 #define RSCONFIG_DMA_TO_HOST 0x00008000L
146 #define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L
147 #define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L
148 #define RSCONFIG_DMA_ENABLE 0x20000000L
149 #define RSCONFIG_PRIORITY_MASK 0xC0000000L
150 #define RSCONFIG_PRIORITY_HIGH 0x00000000L
151 #define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L
152 #define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L
153 #define RSCONFIG_PRIORITY_LOW 0xC0000000L
154 #define RSCONFIG_STREAM_NUM_SHIFT 16L
155 #define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L
156
157 /* SP constants */
158 #define FG_INTERVAL_TIMER_PERIOD 0x0051
159 #define BG_INTERVAL_TIMER_PERIOD 0x0100
160
161
162 /* Only SP accessible registers */
163 #define SP_ASER_COUNTDOWN 0x8040
164 #define SP_SPDOUT_FIFO 0x0108
165 #define SP_SPDIN_MI_FIFO 0x01E0
166 #define SP_SPDIN_D_FIFO 0x01F0
167 #define SP_SPDIN_STATUS 0x8048
168 #define SP_SPDIN_CONTROL 0x8049
169 #define SP_SPDIN_FIFOPTR 0x804A
170 #define SP_SPDOUT_STATUS 0x804C
171 #define SP_SPDOUT_CONTROL 0x804D
172 #define SP_SPDOUT_CSUV 0x808E
173
174 static inline u8 _wrap_all_bits (u8 val)
175 {
176 u8 wrapped;
177
178 /* wrap all 8 bits */
179 wrapped =
180 ((val & 0x1 ) << 7) |
181 ((val & 0x2 ) << 5) |
182 ((val & 0x4 ) << 3) |
183 ((val & 0x8 ) << 1) |
184 ((val & 0x10) >> 1) |
185 ((val & 0x20) >> 3) |
186 ((val & 0x40) >> 5) |
187 ((val & 0x80) >> 7);
188
189 return wrapped;
190 }
191
192 static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip,
193 struct dsp_scb_descriptor * scb)
194 {
195 /* update nextSCB and subListPtr in SCB */
196 snd_cs46xx_poke(chip,
197 (scb->address + SCBsubListPtr) << 2,
198 (scb->sub_list_ptr->address << 0x10) |
199 (scb->next_scb_ptr->address));
200 scb->updated = 1;
201 }
202
203 static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip,
204 struct dsp_scb_descriptor * scb,
205 u16 left, u16 right)
206 {
207 unsigned int val = ((0xffff - left) << 16 | (0xffff - right));
208
209 snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val);
210 snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val);
211 scb->volume_set = 1;
212 scb->volume[0] = left;
213 scb->volume[1] = right;
214 }
215 #endif /* __DSP_SPOS_H__ */
216 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
217
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