1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * James Courtier-Dutton <James@superbug.co.uk>
5 * Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
6 * Creative Labs, Inc.
7 *
8 * Routines for effect processor FX8010
9 */
10
11 #include <linux/pci.h>
12 #include <linux/capability.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <linux/vmalloc.h>
16 #include <linux/init.h>
17 #include <linux/mutex.h>
18 #include <linux/moduleparam.h>
19 #include <linux/nospec.h>
20
21 #include <sound/core.h>
22 #include <sound/tlv.h>
23 #include <sound/emu10k1.h>
24
25 #if 0 /* for testing purposes - digital out -> capture */
26 #define EMU10K1_CAPTURE_DIGITAL_OUT
27 #endif
28 #if 0 /* for testing purposes - set S/PDIF to AC3 output */
29 #define EMU10K1_SET_AC3_IEC958
30 #endif
31 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
32 #define EMU10K1_CENTER_LFE_FROM_FRONT
33 #endif
34
35 static bool high_res_gpr_volume;
36 module_param(high_res_gpr_volume, bool, 0444);
37 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
38
39 /*
40 * Tables
41 */
42
43 // Playback channel labels; corresponds with the public FXBUS_* defines.
44 // Unlike the tables below, this is not determined by the hardware.
45 const char * const snd_emu10k1_fxbus[32] = {
46 /* 0x00 */ "PCM Left",
47 /* 0x01 */ "PCM Right",
48 /* 0x02 */ "PCM Rear Left",
49 /* 0x03 */ "PCM Rear Right",
50 /* 0x04 */ "MIDI Left",
51 /* 0x05 */ "MIDI Right",
52 /* 0x06 */ "PCM Center",
53 /* 0x07 */ "PCM LFE",
54 /* 0x08 */ "PCM Front Left",
55 /* 0x09 */ "PCM Front Right",
56 /* 0x0a */ NULL,
57 /* 0x0b */ NULL,
58 /* 0x0c */ "MIDI Reverb",
59 /* 0x0d */ "MIDI Chorus",
60 /* 0x0e */ "PCM Side Left",
61 /* 0x0f */ "PCM Side Right",
62 /* 0x10 */ NULL,
63 /* 0x11 */ NULL,
64 /* 0x12 */ NULL,
65 /* 0x13 */ NULL,
66 /* 0x14 */ "Passthrough Left",
67 /* 0x15 */ "Passthrough Right",
68 /* 0x16 */ NULL,
69 /* 0x17 */ NULL,
70 /* 0x18 */ NULL,
71 /* 0x19 */ NULL,
72 /* 0x1a */ NULL,
73 /* 0x1b */ NULL,
74 /* 0x1c */ NULL,
75 /* 0x1d */ NULL,
76 /* 0x1e */ NULL,
77 /* 0x1f */ NULL
78 };
79
80 // Physical inputs; corresponds with the public EXTIN_* defines.
81 const char * const snd_emu10k1_sblive_ins[16] = {
82 /* 0x00 */ "AC97 Left",
83 /* 0x01 */ "AC97 Right",
84 /* 0x02 */ "TTL IEC958 Left",
85 /* 0x03 */ "TTL IEC958 Right",
86 /* 0x04 */ "Zoom Video Left",
87 /* 0x05 */ "Zoom Video Right",
88 /* 0x06 */ "Optical IEC958 Left",
89 /* 0x07 */ "Optical IEC958 Right",
90 /* 0x08 */ "Line/Mic 1 Left",
91 /* 0x09 */ "Line/Mic 1 Right",
92 /* 0x0a */ "Coaxial IEC958 Left",
93 /* 0x0b */ "Coaxial IEC958 Right",
94 /* 0x0c */ "Line/Mic 2 Left",
95 /* 0x0d */ "Line/Mic 2 Right",
96 /* 0x0e */ NULL,
97 /* 0x0f */ NULL
98 };
99
100 // Physical inputs; corresponds with the public A_EXTIN_* defines.
101 const char * const snd_emu10k1_audigy_ins[16] = {
102 /* 0x00 */ "AC97 Left",
103 /* 0x01 */ "AC97 Right",
104 /* 0x02 */ "Audigy CD Left",
105 /* 0x03 */ "Audigy CD Right",
106 /* 0x04 */ "Optical IEC958 Left",
107 /* 0x05 */ "Optical IEC958 Right",
108 /* 0x06 */ NULL,
109 /* 0x07 */ NULL,
110 /* 0x08 */ "Line/Mic 2 Left",
111 /* 0x09 */ "Line/Mic 2 Right",
112 /* 0x0a */ "SPDIF Left",
113 /* 0x0b */ "SPDIF Right",
114 /* 0x0c */ "Aux2 Left",
115 /* 0x0d */ "Aux2 Right",
116 /* 0x0e */ NULL,
117 /* 0x0f */ NULL
118 };
119
120 // Physical outputs; corresponds with the public EXTOUT_* defines.
121 const char * const snd_emu10k1_sblive_outs[32] = {
122 /* 0x00 */ "AC97 Left",
123 /* 0x01 */ "AC97 Right",
124 /* 0x02 */ "Optical IEC958 Left",
125 /* 0x03 */ "Optical IEC958 Right",
126 /* 0x04 */ "Center",
127 /* 0x05 */ "LFE",
128 /* 0x06 */ "Headphone Left",
129 /* 0x07 */ "Headphone Right",
130 /* 0x08 */ "Surround Left",
131 /* 0x09 */ "Surround Right",
132 /* 0x0a */ "PCM Capture Left",
133 /* 0x0b */ "PCM Capture Right",
134 /* 0x0c */ "MIC Capture",
135 /* 0x0d */ "AC97 Surround Left",
136 /* 0x0e */ "AC97 Surround Right",
137 /* 0x0f */ NULL,
138 // This is actually the FXBUS2 range; SB Live! 5.1 only.
139 /* 0x10 */ NULL,
140 /* 0x11 */ "Analog Center",
141 /* 0x12 */ "Analog LFE",
142 /* 0x13 */ NULL,
143 /* 0x14 */ NULL,
144 /* 0x15 */ NULL,
145 /* 0x16 */ NULL,
146 /* 0x17 */ NULL,
147 /* 0x18 */ NULL,
148 /* 0x19 */ NULL,
149 /* 0x1a */ NULL,
150 /* 0x1b */ NULL,
151 /* 0x1c */ NULL,
152 /* 0x1d */ NULL,
153 /* 0x1e */ NULL,
154 /* 0x1f */ NULL,
155 };
156
157 // Physical outputs; corresponds with the public A_EXTOUT_* defines.
158 const char * const snd_emu10k1_audigy_outs[32] = {
159 /* 0x00 */ "Digital Front Left",
160 /* 0x01 */ "Digital Front Right",
161 /* 0x02 */ "Digital Center",
162 /* 0x03 */ "Digital LEF",
163 /* 0x04 */ "Headphone Left",
164 /* 0x05 */ "Headphone Right",
165 /* 0x06 */ "Digital Rear Left",
166 /* 0x07 */ "Digital Rear Right",
167 /* 0x08 */ "Front Left",
168 /* 0x09 */ "Front Right",
169 /* 0x0a */ "Center",
170 /* 0x0b */ "LFE",
171 /* 0x0c */ NULL,
172 /* 0x0d */ NULL,
173 /* 0x0e */ "Rear Left",
174 /* 0x0f */ "Rear Right",
175 /* 0x10 */ "AC97 Front Left",
176 /* 0x11 */ "AC97 Front Right",
177 /* 0x12 */ "ADC Capture Left",
178 /* 0x13 */ "ADC Capture Right",
179 /* 0x14 */ NULL,
180 /* 0x15 */ NULL,
181 /* 0x16 */ NULL,
182 /* 0x17 */ NULL,
183 /* 0x18 */ NULL,
184 /* 0x19 */ NULL,
185 /* 0x1a */ NULL,
186 /* 0x1b */ NULL,
187 /* 0x1c */ NULL,
188 /* 0x1d */ NULL,
189 /* 0x1e */ NULL,
190 /* 0x1f */ NULL,
191 };
192
193 // On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER
194 // and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
195 //
196 // Since only 14 of the 16 EXTINs are used, this is not a big problem.
197 // We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3,
198 // and the rest of the EXTINs to the corresponding FX capture channel.
199 // Multitrack recorders will still see the center/LFE output signal
200 // on the second and third "input" channel.
201 const s8 snd_emu10k1_sblive51_fxbus2_map[16] = {
202 2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1
203 };
204
205 static const u32 bass_table[41][5] = {
206 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
207 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
208 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
209 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
210 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
211 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
212 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
213 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
214 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
215 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
216 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
217 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
218 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
219 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
220 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
221 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
222 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
223 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
224 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
225 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
226 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
227 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
228 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
229 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
230 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
231 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
232 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
233 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
234 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
235 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
236 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
237 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
238 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
239 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
240 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
241 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
242 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
243 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
244 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
245 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
246 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
247 };
248
249 static const u32 treble_table[41][5] = {
250 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
251 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
252 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
253 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
254 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
255 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
256 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
257 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
258 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
259 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
260 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
261 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
262 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
263 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
264 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
265 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
266 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
267 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
268 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
269 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
270 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
271 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
272 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
273 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
274 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
275 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
276 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
277 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
278 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
279 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
280 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
281 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
282 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
283 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
284 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
285 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
286 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
287 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
288 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
289 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
290 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
291 };
292
293 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
294 static const u32 db_table[101] = {
295 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
296 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
297 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
298 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
299 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
300 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
301 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
302 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
303 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
304 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
305 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
306 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
307 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
308 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
309 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
310 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
311 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
312 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
313 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
314 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
315 0x7fffffff,
316 };
317
318 /* EMU10k1/EMU10k2 DSP control db gain */
319 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
320 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
321
322 /* EMU10K1 bass/treble db gain */
323 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
324
325 static const u32 onoff_table[2] = {
326 0x00000000, 0x00000001
327 };
328
329 /*
330 * controls
331 */
332
333 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
334 {
335 struct snd_emu10k1_fx8010_ctl *ctl =
336 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
337
338 if (ctl->min == 0 && ctl->max == 1)
339 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
340 else
341 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
342 uinfo->count = ctl->vcount;
343 uinfo->value.integer.min = ctl->min;
344 uinfo->value.integer.max = ctl->max;
345 return 0;
346 }
347
348 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
349 {
350 struct snd_emu10k1_fx8010_ctl *ctl =
351 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
352 unsigned int i;
353
354 for (i = 0; i < ctl->vcount; i++)
355 ucontrol->value.integer.value[i] = ctl->value[i];
356 return 0;
357 }
358
359 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
360 {
361 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
362 struct snd_emu10k1_fx8010_ctl *ctl =
363 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
364 int nval, val;
365 unsigned int i, j;
366 int change = 0;
367
368 for (i = 0; i < ctl->vcount; i++) {
369 nval = ucontrol->value.integer.value[i];
370 if (nval < ctl->min)
371 nval = ctl->min;
372 if (nval > ctl->max)
373 nval = ctl->max;
374 if (nval != ctl->value[i])
375 change = 1;
376 val = ctl->value[i] = nval;
377 switch (ctl->translation) {
378 case EMU10K1_GPR_TRANSLATION_NONE:
379 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
380 break;
381 case EMU10K1_GPR_TRANSLATION_NEGATE:
382 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val);
383 break;
384 case EMU10K1_GPR_TRANSLATION_TABLE100:
385 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
386 break;
387 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
388 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0,
389 val == 100 ? 0x80000000 : -(int)db_table[val]);
390 break;
391 case EMU10K1_GPR_TRANSLATION_BASS:
392 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
393 change = -EIO;
394 goto __error;
395 }
396 for (j = 0; j < 5; j++)
397 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
398 break;
399 case EMU10K1_GPR_TRANSLATION_TREBLE:
400 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
401 change = -EIO;
402 goto __error;
403 }
404 for (j = 0; j < 5; j++)
405 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
406 break;
407 case EMU10K1_GPR_TRANSLATION_ONOFF:
408 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
409 break;
410 }
411 }
412 __error:
413 return change;
414 }
415
416 /*
417 * Interrupt handler
418 */
419
420 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
421 {
422 struct snd_emu10k1_fx8010_irq *irq, *nirq;
423
424 irq = emu->fx8010.irq_handlers;
425 while (irq) {
426 nirq = irq->next; /* irq ptr can be removed from list */
427 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
428 if (irq->handler)
429 irq->handler(emu, irq->private_data);
430 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
431 }
432 irq = nirq;
433 }
434 }
435
436 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
437 snd_fx8010_irq_handler_t *handler,
438 unsigned char gpr_running,
439 void *private_data,
440 struct snd_emu10k1_fx8010_irq *irq)
441 {
442 unsigned long flags;
443
444 irq->handler = handler;
445 irq->gpr_running = gpr_running;
446 irq->private_data = private_data;
447 irq->next = NULL;
448 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
449 if (emu->fx8010.irq_handlers == NULL) {
450 emu->fx8010.irq_handlers = irq;
451 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
452 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
453 } else {
454 irq->next = emu->fx8010.irq_handlers;
455 emu->fx8010.irq_handlers = irq;
456 }
457 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
458 return 0;
459 }
460
461 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
462 struct snd_emu10k1_fx8010_irq *irq)
463 {
464 struct snd_emu10k1_fx8010_irq *tmp;
465 unsigned long flags;
466
467 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
468 tmp = emu->fx8010.irq_handlers;
469 if (tmp == irq) {
470 emu->fx8010.irq_handlers = tmp->next;
471 if (emu->fx8010.irq_handlers == NULL) {
472 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
473 emu->dsp_interrupt = NULL;
474 }
475 } else {
476 while (tmp && tmp->next != irq)
477 tmp = tmp->next;
478 if (tmp)
479 tmp->next = tmp->next->next;
480 }
481 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
482 return 0;
483 }
484
485 /*************************************************************************
486 * EMU10K1 effect manager
487 *************************************************************************/
488
489 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
490 unsigned int *ptr,
491 u32 op, u32 r, u32 a, u32 x, u32 y)
492 {
493 u_int32_t *code;
494 if (snd_BUG_ON(*ptr >= 512))
495 return;
496 code = icode->code + (*ptr) * 2;
497 set_bit(*ptr, icode->code_valid);
498 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
499 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
500 (*ptr)++;
501 }
502
503 #define OP(icode, ptr, op, r, a, x, y) \
504 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
505
506 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
507 unsigned int *ptr,
508 u32 op, u32 r, u32 a, u32 x, u32 y)
509 {
510 u_int32_t *code;
511 if (snd_BUG_ON(*ptr >= 1024))
512 return;
513 code = icode->code + (*ptr) * 2;
514 set_bit(*ptr, icode->code_valid);
515 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
516 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
517 (*ptr)++;
518 }
519
520 #define A_OP(icode, ptr, op, r, a, x, y) \
521 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
522
523 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
524 {
525 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
526 snd_emu10k1_ptr_write(emu, pc, 0, data);
527 }
528
529 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
530 {
531 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
532 return snd_emu10k1_ptr_read(emu, pc, 0);
533 }
534
535 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
536 struct snd_emu10k1_fx8010_code *icode,
537 bool in_kernel)
538 {
539 int gpr;
540 u32 val;
541
542 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
543 if (!test_bit(gpr, icode->gpr_valid))
544 continue;
545 if (in_kernel)
546 val = icode->gpr_map[gpr];
547 else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr]))
548 return -EFAULT;
549 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
550 }
551 return 0;
552 }
553
554 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
555 struct snd_emu10k1_fx8010_code *icode)
556 {
557 int gpr;
558 u32 val;
559
560 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
561 set_bit(gpr, icode->gpr_valid);
562 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
563 if (put_user(val, (__user u32 *)&icode->gpr_map[gpr]))
564 return -EFAULT;
565 }
566 return 0;
567 }
568
569 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
570 struct snd_emu10k1_fx8010_code *icode,
571 bool in_kernel)
572 {
573 int tram;
574 u32 addr, val;
575
576 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
577 if (!test_bit(tram, icode->tram_valid))
578 continue;
579 if (in_kernel) {
580 val = icode->tram_data_map[tram];
581 addr = icode->tram_addr_map[tram];
582 } else {
583 if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) ||
584 get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram]))
585 return -EFAULT;
586 }
587 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
588 if (!emu->audigy) {
589 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
590 } else {
591 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
592 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
593 }
594 }
595 return 0;
596 }
597
598 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
599 struct snd_emu10k1_fx8010_code *icode)
600 {
601 int tram;
602 u32 val, addr;
603
604 memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
605 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
606 set_bit(tram, icode->tram_valid);
607 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
608 if (!emu->audigy) {
609 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
610 } else {
611 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
612 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
613 }
614 if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) ||
615 put_user(addr, (__user u32 *)&icode->tram_addr_map[tram]))
616 return -EFAULT;
617 }
618 return 0;
619 }
620
621 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
622 struct snd_emu10k1_fx8010_code *icode,
623 bool in_kernel)
624 {
625 u32 pc, lo, hi;
626
627 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
628 if (!test_bit(pc / 2, icode->code_valid))
629 continue;
630 if (in_kernel) {
631 lo = icode->code[pc + 0];
632 hi = icode->code[pc + 1];
633 } else {
634 if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) ||
635 get_user(hi, (__user u32 *)&icode->code[pc + 1]))
636 return -EFAULT;
637 }
638 snd_emu10k1_efx_write(emu, pc + 0, lo);
639 snd_emu10k1_efx_write(emu, pc + 1, hi);
640 }
641 return 0;
642 }
643
644 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
645 struct snd_emu10k1_fx8010_code *icode)
646 {
647 u32 pc;
648
649 memset(icode->code_valid, 0, sizeof(icode->code_valid));
650 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
651 set_bit(pc / 2, icode->code_valid);
652 if (put_user(snd_emu10k1_efx_read(emu, pc + 0),
653 (__user u32 *)&icode->code[pc + 0]))
654 return -EFAULT;
655 if (put_user(snd_emu10k1_efx_read(emu, pc + 1),
656 (__user u32 *)&icode->code[pc + 1]))
657 return -EFAULT;
658 }
659 return 0;
660 }
661
662 static struct snd_emu10k1_fx8010_ctl *
663 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu,
664 struct emu10k1_ctl_elem_id *_id)
665 {
666 struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
667 struct snd_emu10k1_fx8010_ctl *ctl;
668 struct snd_kcontrol *kcontrol;
669
670 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
671 kcontrol = ctl->kcontrol;
672 if (kcontrol->id.iface == id->iface &&
673 kcontrol->id.index == id->index &&
674 !strcmp(kcontrol->id.name, id->name))
675 return ctl;
676 }
677 return NULL;
678 }
679
680 #define MAX_TLV_SIZE 256
681
682 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
683 {
684 unsigned int data[2];
685 unsigned int *tlv;
686
687 if (!_tlv)
688 return NULL;
689 if (in_kernel)
690 memcpy(data, (__force void *)_tlv, sizeof(data));
691 else if (copy_from_user(data, _tlv, sizeof(data)))
692 return NULL;
693 if (data[1] >= MAX_TLV_SIZE)
694 return NULL;
695 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
696 if (!tlv)
697 return NULL;
698 memcpy(tlv, data, sizeof(data));
699 if (in_kernel) {
700 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]);
701 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
702 kfree(tlv);
703 return NULL;
704 }
705 return tlv;
706 }
707
708 static int copy_gctl(struct snd_emu10k1 *emu,
709 struct snd_emu10k1_fx8010_control_gpr *dst,
710 struct snd_emu10k1_fx8010_control_gpr *src,
711 int idx, bool in_kernel)
712 {
713 struct snd_emu10k1_fx8010_control_gpr __user *_src;
714 struct snd_emu10k1_fx8010_control_old_gpr *octl;
715 struct snd_emu10k1_fx8010_control_old_gpr __user *_octl;
716
717 _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src;
718 if (emu->support_tlv) {
719 if (in_kernel)
720 *dst = src[idx];
721 else if (copy_from_user(dst, &_src[idx], sizeof(*src)))
722 return -EFAULT;
723 return 0;
724 }
725
726 octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src;
727 _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl;
728 if (in_kernel)
729 memcpy(dst, &octl[idx], sizeof(*octl));
730 else if (copy_from_user(dst, &_octl[idx], sizeof(*octl)))
731 return -EFAULT;
732 dst->tlv = NULL;
733 return 0;
734 }
735
736 static int copy_gctl_to_user(struct snd_emu10k1 *emu,
737 struct snd_emu10k1_fx8010_control_gpr *dst,
738 struct snd_emu10k1_fx8010_control_gpr *src,
739 int idx)
740 {
741 struct snd_emu10k1_fx8010_control_gpr __user *_dst;
742 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
743
744 _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst;
745 if (emu->support_tlv)
746 return copy_to_user(&_dst[idx], src, sizeof(*src));
747
748 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst;
749 return copy_to_user(&octl[idx], src, sizeof(*octl));
750 }
751
752 static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i,
753 struct emu10k1_ctl_elem_id *ret, bool in_kernel)
754 {
755 struct emu10k1_ctl_elem_id __user *_id =
756 (struct emu10k1_ctl_elem_id __user *)&list[i];
757
758 if (in_kernel)
759 *ret = list[i];
760 else if (copy_from_user(ret, _id, sizeof(*ret)))
761 return -EFAULT;
762 return 0;
763 }
764
765 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
766 struct snd_emu10k1_fx8010_code *icode,
767 bool in_kernel)
768 {
769 unsigned int i;
770 struct emu10k1_ctl_elem_id id;
771 struct snd_emu10k1_fx8010_control_gpr *gctl;
772 struct snd_ctl_elem_id *gctl_id;
773 int err;
774
775 for (i = 0; i < icode->gpr_del_control_count; i++) {
776 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
777 in_kernel);
778 if (err < 0)
779 return err;
780 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
781 return -ENOENT;
782 }
783 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
784 if (! gctl)
785 return -ENOMEM;
786 err = 0;
787 for (i = 0; i < icode->gpr_add_control_count; i++) {
788 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
789 in_kernel)) {
790 err = -EFAULT;
791 goto __error;
792 }
793 if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
794 continue;
795 gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
796 if (snd_ctl_find_id(emu->card, gctl_id)) {
797 err = -EEXIST;
798 goto __error;
799 }
800 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
801 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
802 err = -EINVAL;
803 goto __error;
804 }
805 switch (gctl->translation) {
806 case EMU10K1_GPR_TRANSLATION_NONE:
807 case EMU10K1_GPR_TRANSLATION_NEGATE:
808 break;
809 case EMU10K1_GPR_TRANSLATION_TABLE100:
810 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
811 if (gctl->min != 0 || gctl->max != 100) {
812 err = -EINVAL;
813 goto __error;
814 }
815 break;
816 case EMU10K1_GPR_TRANSLATION_BASS:
817 case EMU10K1_GPR_TRANSLATION_TREBLE:
818 if (gctl->min != 0 || gctl->max != 40) {
819 err = -EINVAL;
820 goto __error;
821 }
822 break;
823 case EMU10K1_GPR_TRANSLATION_ONOFF:
824 if (gctl->min != 0 || gctl->max != 1) {
825 err = -EINVAL;
826 goto __error;
827 }
828 break;
829 default:
830 err = -EINVAL;
831 goto __error;
832 }
833 }
834 for (i = 0; i < icode->gpr_list_control_count; i++) {
835 /* FIXME: we need to check the WRITE access */
836 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
837 in_kernel)) {
838 err = -EFAULT;
839 goto __error;
840 }
841 }
842 __error:
843 kfree(gctl);
844 return err;
845 }
846
847 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
848 {
849 struct snd_emu10k1_fx8010_ctl *ctl;
850
851 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
852 kctl->private_value = 0;
853 list_del(&ctl->list);
854 kfree(ctl);
855 kfree(kctl->tlv.p);
856 }
857
858 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
859 struct snd_emu10k1_fx8010_code *icode,
860 bool in_kernel)
861 {
862 unsigned int i, j;
863 struct snd_emu10k1_fx8010_control_gpr *gctl;
864 struct snd_ctl_elem_id *gctl_id;
865 struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
866 struct snd_kcontrol_new knew;
867 struct snd_kcontrol *kctl;
868 struct snd_ctl_elem_value *val;
869 int err = 0;
870
871 val = kmalloc(sizeof(*val), GFP_KERNEL);
872 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
873 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
874 if (!val || !gctl || !nctl) {
875 err = -ENOMEM;
876 goto __error;
877 }
878
879 for (i = 0; i < icode->gpr_add_control_count; i++) {
880 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
881 in_kernel)) {
882 err = -EFAULT;
883 goto __error;
884 }
885 gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
886 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
887 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
888 err = -EINVAL;
889 goto __error;
890 }
891 if (!*gctl_id->name) {
892 err = -EINVAL;
893 goto __error;
894 }
895 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
896 memset(&knew, 0, sizeof(knew));
897 knew.iface = gctl_id->iface;
898 knew.name = gctl_id->name;
899 knew.index = gctl_id->index;
900 knew.device = gctl_id->device;
901 knew.subdevice = gctl_id->subdevice;
902 knew.info = snd_emu10k1_gpr_ctl_info;
903 knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel);
904 if (knew.tlv.p)
905 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
906 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
907 knew.get = snd_emu10k1_gpr_ctl_get;
908 knew.put = snd_emu10k1_gpr_ctl_put;
909 memset(nctl, 0, sizeof(*nctl));
910 nctl->vcount = gctl->vcount;
911 nctl->count = gctl->count;
912 for (j = 0; j < 32; j++) {
913 nctl->gpr[j] = gctl->gpr[j];
914 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
915 val->value.integer.value[j] = gctl->value[j];
916 }
917 nctl->min = gctl->min;
918 nctl->max = gctl->max;
919 nctl->translation = gctl->translation;
920 if (ctl == NULL) {
921 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
922 if (ctl == NULL) {
923 err = -ENOMEM;
924 kfree(knew.tlv.p);
925 goto __error;
926 }
927 knew.private_value = (unsigned long)ctl;
928 *ctl = *nctl;
929 kctl = snd_ctl_new1(&knew, emu);
930 err = snd_ctl_add(emu->card, kctl);
931 if (err < 0) {
932 kfree(ctl);
933 kfree(knew.tlv.p);
934 goto __error;
935 }
936 kctl->private_free = snd_emu10k1_ctl_private_free;
937 ctl->kcontrol = kctl;
938 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
939 } else {
940 /* overwrite */
941 nctl->list = ctl->list;
942 nctl->kcontrol = ctl->kcontrol;
943 *ctl = *nctl;
944 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
945 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
946 }
947 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
948 }
949 __error:
950 kfree(nctl);
951 kfree(gctl);
952 kfree(val);
953 return err;
954 }
955
956 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
957 struct snd_emu10k1_fx8010_code *icode,
958 bool in_kernel)
959 {
960 unsigned int i;
961 struct emu10k1_ctl_elem_id id;
962 struct snd_emu10k1_fx8010_ctl *ctl;
963 struct snd_card *card = emu->card;
964 int err;
965
966 for (i = 0; i < icode->gpr_del_control_count; i++) {
967 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
968 in_kernel);
969 if (err < 0)
970 return err;
971 ctl = snd_emu10k1_look_for_ctl(emu, &id);
972 if (ctl)
973 snd_ctl_remove(card, ctl->kcontrol);
974 }
975 return 0;
976 }
977
978 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
979 struct snd_emu10k1_fx8010_code *icode)
980 {
981 unsigned int i = 0, j;
982 unsigned int total = 0;
983 struct snd_emu10k1_fx8010_control_gpr *gctl;
984 struct snd_emu10k1_fx8010_ctl *ctl;
985 struct snd_ctl_elem_id *id;
986
987 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
988 if (! gctl)
989 return -ENOMEM;
990
991 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
992 total++;
993 if (icode->gpr_list_controls &&
994 i < icode->gpr_list_control_count) {
995 memset(gctl, 0, sizeof(*gctl));
996 id = &ctl->kcontrol->id;
997 gctl->id.iface = (__force int)id->iface;
998 strscpy(gctl->id.name, id->name, sizeof(gctl->id.name));
999 gctl->id.index = id->index;
1000 gctl->id.device = id->device;
1001 gctl->id.subdevice = id->subdevice;
1002 gctl->vcount = ctl->vcount;
1003 gctl->count = ctl->count;
1004 for (j = 0; j < 32; j++) {
1005 gctl->gpr[j] = ctl->gpr[j];
1006 gctl->value[j] = ctl->value[j];
1007 }
1008 gctl->min = ctl->min;
1009 gctl->max = ctl->max;
1010 gctl->translation = ctl->translation;
1011 if (copy_gctl_to_user(emu, icode->gpr_list_controls,
1012 gctl, i)) {
1013 kfree(gctl);
1014 return -EFAULT;
1015 }
1016 i++;
1017 }
1018 }
1019 icode->gpr_list_control_total = total;
1020 kfree(gctl);
1021 return 0;
1022 }
1023
1024 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
1025 struct snd_emu10k1_fx8010_code *icode,
1026 bool in_kernel)
1027 {
1028 int err = 0;
1029
1030 mutex_lock(&emu->fx8010.lock);
1031 err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
1032 if (err < 0)
1033 goto __error;
1034 strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
1035 /* stop FX processor - this may be dangerous, but it's better to miss
1036 some samples than generate wrong ones - [jk] */
1037 if (emu->audigy)
1038 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
1039 else
1040 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
1041 /* ok, do the main job */
1042 err = snd_emu10k1_del_controls(emu, icode, in_kernel);
1043 if (err < 0)
1044 goto __error;
1045 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
1046 if (err < 0)
1047 goto __error;
1048 err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
1049 if (err < 0)
1050 goto __error;
1051 err = snd_emu10k1_code_poke(emu, icode, in_kernel);
1052 if (err < 0)
1053 goto __error;
1054 err = snd_emu10k1_add_controls(emu, icode, in_kernel);
1055 if (err < 0)
1056 goto __error;
1057 /* start FX processor when the DSP code is updated */
1058 if (emu->audigy)
1059 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
1060 else
1061 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
1062 __error:
1063 mutex_unlock(&emu->fx8010.lock);
1064 return err;
1065 }
1066
1067 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
1068 struct snd_emu10k1_fx8010_code *icode)
1069 {
1070 int err;
1071
1072 mutex_lock(&emu->fx8010.lock);
1073 strscpy(icode->name, emu->fx8010.name, sizeof(icode->name));
1074 /* ok, do the main job */
1075 err = snd_emu10k1_gpr_peek(emu, icode);
1076 if (err >= 0)
1077 err = snd_emu10k1_tram_peek(emu, icode);
1078 if (err >= 0)
1079 err = snd_emu10k1_code_peek(emu, icode);
1080 if (err >= 0)
1081 err = snd_emu10k1_list_controls(emu, icode);
1082 mutex_unlock(&emu->fx8010.lock);
1083 return err;
1084 }
1085
1086 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
1087 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1088 {
1089 unsigned int i;
1090 int err = 0;
1091 struct snd_emu10k1_fx8010_pcm *pcm;
1092
1093 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1094 return -EINVAL;
1095 ipcm->substream = array_index_nospec(ipcm->substream,
1096 EMU10K1_FX8010_PCM_COUNT);
1097 if (ipcm->channels > 32)
1098 return -EINVAL;
1099 pcm = &emu->fx8010.pcm[ipcm->substream];
1100 mutex_lock(&emu->fx8010.lock);
1101 spin_lock_irq(&emu->reg_lock);
1102 if (pcm->opened) {
1103 err = -EBUSY;
1104 goto __error;
1105 }
1106 if (ipcm->channels == 0) { /* remove */
1107 pcm->valid = 0;
1108 } else {
1109 /* FIXME: we need to add universal code to the PCM transfer routine */
1110 if (ipcm->channels != 2) {
1111 err = -EINVAL;
1112 goto __error;
1113 }
1114 pcm->valid = 1;
1115 pcm->opened = 0;
1116 pcm->channels = ipcm->channels;
1117 pcm->tram_start = ipcm->tram_start;
1118 pcm->buffer_size = ipcm->buffer_size;
1119 pcm->gpr_size = ipcm->gpr_size;
1120 pcm->gpr_count = ipcm->gpr_count;
1121 pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
1122 pcm->gpr_ptr = ipcm->gpr_ptr;
1123 pcm->gpr_trigger = ipcm->gpr_trigger;
1124 pcm->gpr_running = ipcm->gpr_running;
1125 for (i = 0; i < pcm->channels; i++)
1126 pcm->etram[i] = ipcm->etram[i];
1127 }
1128 __error:
1129 spin_unlock_irq(&emu->reg_lock);
1130 mutex_unlock(&emu->fx8010.lock);
1131 return err;
1132 }
1133
1134 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
1135 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1136 {
1137 unsigned int i;
1138 int err = 0;
1139 struct snd_emu10k1_fx8010_pcm *pcm;
1140
1141 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1142 return -EINVAL;
1143 ipcm->substream = array_index_nospec(ipcm->substream,
1144 EMU10K1_FX8010_PCM_COUNT);
1145 pcm = &emu->fx8010.pcm[ipcm->substream];
1146 mutex_lock(&emu->fx8010.lock);
1147 spin_lock_irq(&emu->reg_lock);
1148 ipcm->channels = pcm->channels;
1149 ipcm->tram_start = pcm->tram_start;
1150 ipcm->buffer_size = pcm->buffer_size;
1151 ipcm->gpr_size = pcm->gpr_size;
1152 ipcm->gpr_ptr = pcm->gpr_ptr;
1153 ipcm->gpr_count = pcm->gpr_count;
1154 ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
1155 ipcm->gpr_trigger = pcm->gpr_trigger;
1156 ipcm->gpr_running = pcm->gpr_running;
1157 for (i = 0; i < pcm->channels; i++)
1158 ipcm->etram[i] = pcm->etram[i];
1159 ipcm->res1 = ipcm->res2 = 0;
1160 ipcm->pad = 0;
1161 spin_unlock_irq(&emu->reg_lock);
1162 mutex_unlock(&emu->fx8010.lock);
1163 return err;
1164 }
1165
1166 #define SND_EMU10K1_GPR_CONTROLS 44
1167 #define SND_EMU10K1_INPUTS 12
1168 #define SND_EMU10K1_PLAYBACK_CHANNELS 8
1169 #define SND_EMU10K1_CAPTURE_CHANNELS 4
1170
1171 #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1)
1172
1173 static void
1174 snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
1175 const char *name, int gpr, int defval, int defval_hr)
1176 {
1177 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1178 strcpy(ctl->id.name, name);
1179 ctl->vcount = ctl->count = 1;
1180 if (high_res_gpr_volume) {
1181 ctl->min = -1;
1182 ctl->max = 0x7fffffff;
1183 ctl->tlv = snd_emu10k1_db_linear;
1184 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
1185 defval = defval_hr;
1186 } else {
1187 ctl->min = 0;
1188 ctl->max = 100;
1189 ctl->tlv = snd_emu10k1_db_scale1;
1190 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
1191 }
1192 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1193 }
1194 #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \
1195 snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval))
1196
1197 static void
1198 snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
1199 const char *name, int gpr, int defval, int defval_hr)
1200 {
1201 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1202 strcpy(ctl->id.name, name);
1203 ctl->vcount = ctl->count = 2;
1204 if (high_res_gpr_volume) {
1205 ctl->min = -1;
1206 ctl->max = 0x7fffffff;
1207 ctl->tlv = snd_emu10k1_db_linear;
1208 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
1209 defval = defval_hr;
1210 } else {
1211 ctl->min = 0;
1212 ctl->max = 100;
1213 ctl->tlv = snd_emu10k1_db_scale1;
1214 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
1215 }
1216 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1217 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1218 }
1219 #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \
1220 snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval))
1221
1222 static void
1223 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1224 const char *name, int gpr, int defval)
1225 {
1226 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1227 strcpy(ctl->id.name, name);
1228 ctl->vcount = ctl->count = 1;
1229 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1230 ctl->min = 0;
1231 ctl->max = 1;
1232 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1233 }
1234
1235 static void
1236 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1237 const char *name, int gpr, int defval)
1238 {
1239 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1240 strcpy(ctl->id.name, name);
1241 ctl->vcount = ctl->count = 2;
1242 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1243 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1244 ctl->min = 0;
1245 ctl->max = 1;
1246 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1247 }
1248
1249 /*
1250 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA
1251 * to 2 x 16-bit registers in Audigy - their values are read via DMA.
1252 * Conversion is performed by Audigy DSP instructions of FX8010.
1253 */
1254 static void snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1255 struct snd_emu10k1_fx8010_code *icode,
1256 u32 *ptr, int tmp, int bit_shifter16,
1257 int reg_in, int reg_out)
1258 {
1259 // This leaves the low word in place, which is fine,
1260 // as the low bits are completely ignored subsequently.
1261 // reg_out[1] = reg_in
1262 A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000);
1263 // It is fine to read reg_in multiple times.
1264 // tmp = reg_in << 15
1265 A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16));
1266 // Left-shift once more. This is a separate step, as the
1267 // signed multiplication would clobber the MSB.
1268 // reg_out[0] = tmp + ((tmp << 31) >> 31)
1269 A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000);
1270 }
1271
1272 #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1
1273
1274 /*
1275 * initial DSP configuration for Audigy
1276 */
1277
1278 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
1279 {
1280 int err, z, nctl;
1281 enum {
1282 ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS),
1283 ENUM_GPR(stereo_mix, 2),
1284 ENUM_GPR(capture, 2),
1285 ENUM_GPR(bit_shifter16, 1),
1286 // The fixed allocation of these breaks the pattern, but why not.
1287 // Splitting these into left/right is questionable, as it will break
1288 // down for center/lfe. But it works for stereo/quadro, so whatever.
1289 ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients
1290 ENUM_GPR(treble_gpr, 2 * 5),
1291 ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages
1292 ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4),
1293 ENUM_GPR(tmp, 3),
1294 num_static_gprs
1295 };
1296 int gpr = num_static_gprs;
1297 u32 ptr, ptr_skip;
1298 struct snd_emu10k1_fx8010_code *icode = NULL;
1299 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1300 u32 *gpr_map;
1301
1302 err = -ENOMEM;
1303 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1304 if (!icode)
1305 return err;
1306
1307 icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024,
1308 sizeof(u_int32_t), GFP_KERNEL);
1309 if (!icode->gpr_map)
1310 goto __err_gpr;
1311 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1312 sizeof(*controls), GFP_KERNEL);
1313 if (!controls)
1314 goto __err_ctrls;
1315
1316 gpr_map = icode->gpr_map;
1317
1318 icode->tram_data_map = icode->gpr_map + 512;
1319 icode->tram_addr_map = icode->tram_data_map + 256;
1320 icode->code = icode->tram_addr_map + 256;
1321
1322 /* clear free GPRs */
1323 memset(icode->gpr_valid, 0xff, 512 / 8);
1324
1325 /* clear TRAM data & address lines */
1326 memset(icode->tram_valid, 0xff, 256 / 8);
1327
1328 strcpy(icode->name, "Audigy DSP code for ALSA");
1329 ptr = 0;
1330 nctl = 0;
1331 gpr_map[bit_shifter16] = 0x00008000;
1332
1333 #if 1
1334 /* PCM front Playback Volume (independent from stereo mix)
1335 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31
1336 * where gpr contains negated attenuation from corresponding mixer control
1337 * (snd_emu10k1_init_stereo_control)
1338 */
1339 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
1340 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
1341 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
1342 gpr += 2;
1343
1344 /* PCM Surround Playback (independent from stereo mix) */
1345 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
1346 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
1347 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
1348 gpr += 2;
1349
1350 /* PCM Side Playback (independent from stereo mix) */
1351 if (emu->card_capabilities->spk71) {
1352 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
1353 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
1354 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
1355 gpr += 2;
1356 }
1357
1358 /* PCM Center Playback (independent from stereo mix) */
1359 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
1360 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
1361 gpr++;
1362
1363 /* PCM LFE Playback (independent from stereo mix) */
1364 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
1365 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
1366 gpr++;
1367
1368 /*
1369 * Stereo Mix
1370 */
1371 /* Wave (PCM) Playback Volume (will be renamed later) */
1372 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1373 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1374 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
1375 gpr += 2;
1376
1377 /* Synth Playback */
1378 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1379 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1380 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
1381 gpr += 2;
1382
1383 /* Wave (PCM) Capture */
1384 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1385 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1386 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
1387 gpr += 2;
1388
1389 /* Synth Capture */
1390 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1391 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1392 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
1393 gpr += 2;
1394
1395 // We need to double the volume, as we configure the voices for half volume,
1396 // which is necessary for bit-identical reproduction.
1397 { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); }
1398 for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++)
1399 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000);
1400
1401 /*
1402 * inputs
1403 */
1404 #define A_ADD_VOLUME_IN(var,vol,input) \
1405 A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
1406
1407 if (emu->card_capabilities->emu_model) {
1408 /* EMU1010 DSP 0 and DSP 1 Capture */
1409 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB.
1410 if (emu->card_capabilities->ca0108_chip) {
1411 // For unclear reasons, the EMU32IN cannot be the Y operand!
1412 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr));
1413 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
1414 // need to be delayed as well; we use an auxiliary register for that.
1415 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
1416 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000);
1417 } else {
1418 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr));
1419 // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1420 // need to be delayed as well; we use an auxiliary register for that.
1421 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
1422 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
1423 }
1424 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
1425 gpr_map[gpr + 2] = 0x00000000;
1426 gpr += 3;
1427 } else {
1428 if (emu->card_capabilities->ac97_chip) {
1429 /* AC'97 Playback Volume - used only for mic (renamed later) */
1430 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
1431 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
1432 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
1433 gpr += 2;
1434 /* AC'97 Capture Volume - used only for mic */
1435 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
1436 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
1437 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
1438 gpr += 2;
1439
1440 /* mic capture buffer */
1441 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R));
1442 }
1443
1444 /* Audigy CD Playback Volume */
1445 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
1446 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1447 snd_emu10k1_init_stereo_control(&controls[nctl++],
1448 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
1449 gpr, 0);
1450 gpr += 2;
1451 /* Audigy CD Capture Volume */
1452 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
1453 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1454 snd_emu10k1_init_stereo_control(&controls[nctl++],
1455 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
1456 gpr, 0);
1457 gpr += 2;
1458
1459 /* Optical SPDIF Playback Volume */
1460 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
1461 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1462 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
1463 gpr += 2;
1464 /* Optical SPDIF Capture Volume */
1465 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
1466 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1467 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
1468 gpr += 2;
1469
1470 /* Line2 Playback Volume */
1471 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
1472 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
1473 snd_emu10k1_init_stereo_control(&controls[nctl++],
1474 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
1475 gpr, 0);
1476 gpr += 2;
1477 /* Line2 Capture Volume */
1478 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
1479 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
1480 snd_emu10k1_init_stereo_control(&controls[nctl++],
1481 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
1482 gpr, 0);
1483 gpr += 2;
1484
1485 /* Philips ADC Playback Volume */
1486 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
1487 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
1488 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
1489 gpr += 2;
1490 /* Philips ADC Capture Volume */
1491 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
1492 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
1493 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
1494 gpr += 2;
1495
1496 /* Aux2 Playback Volume */
1497 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
1498 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
1499 snd_emu10k1_init_stereo_control(&controls[nctl++],
1500 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
1501 gpr, 0);
1502 gpr += 2;
1503 /* Aux2 Capture Volume */
1504 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
1505 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
1506 snd_emu10k1_init_stereo_control(&controls[nctl++],
1507 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
1508 gpr, 0);
1509 gpr += 2;
1510 }
1511
1512 /* Stereo Mix Front Playback Volume */
1513 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
1514 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1515 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
1516 gpr += 2;
1517
1518 /* Stereo Mix Surround Playback */
1519 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
1520 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1521 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
1522 gpr += 2;
1523
1524 /* Stereo Mix Center Playback */
1525 /* Center = sub = Left/2 + Right/2 */
1526 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1));
1527 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
1528 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
1529 gpr++;
1530
1531 /* Stereo Mix LFE Playback */
1532 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
1533 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
1534 gpr++;
1535
1536 if (emu->card_capabilities->spk71) {
1537 /* Stereo Mix Side Playback */
1538 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
1539 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1540 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
1541 gpr += 2;
1542 }
1543
1544 /*
1545 * outputs
1546 */
1547 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
1548 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
1549 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
1550
1551 #define _A_SWITCH(icode, ptr, dst, src, sw) \
1552 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
1553 #define A_SWITCH(icode, ptr, dst, src, sw) \
1554 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
1555 #define _A_SWITCH_NEG(icode, ptr, dst, src) \
1556 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
1557 #define A_SWITCH_NEG(icode, ptr, dst, src) \
1558 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
1559
1560
1561 /*
1562 * Process tone control
1563 */
1564 ctl = &controls[nctl + 0];
1565 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1566 strcpy(ctl->id.name, "Tone Control - Bass");
1567 ctl->vcount = 2;
1568 ctl->count = 10;
1569 ctl->min = 0;
1570 ctl->max = 40;
1571 ctl->value[0] = ctl->value[1] = 20;
1572 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
1573 ctl = &controls[nctl + 1];
1574 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1575 strcpy(ctl->id.name, "Tone Control - Treble");
1576 ctl->vcount = 2;
1577 ctl->count = 10;
1578 ctl->min = 0;
1579 ctl->max = 40;
1580 ctl->value[0] = ctl->value[1] = 20;
1581 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
1582 for (z = 0; z < 5; z++) {
1583 int j;
1584 for (j = 0; j < 2; j++) {
1585 controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j;
1586 controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j;
1587 }
1588 }
1589 nctl += 2;
1590
1591 A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000);
1592 snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
1593 gpr++;
1594 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr));
1595 ptr_skip = ptr;
1596 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
1597 int j, k, l, d;
1598 for (j = 0; j < 2; j++) { /* left/right */
1599 k = bass_tmp + (z * 8) + (j * 4);
1600 l = treble_tmp + (z * 8) + (j * 4);
1601 d = playback + z * 2 + j;
1602
1603 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j));
1604 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j));
1605 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j));
1606 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j));
1607 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j));
1608 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
1609
1610 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j));
1611 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j));
1612 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j));
1613 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j));
1614 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j));
1615 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
1616
1617 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
1618
1619 if (z == 2) /* center */
1620 break;
1621 }
1622 }
1623 gpr_map[gpr++] = ptr - ptr_skip;
1624
1625 /* Master volume (will be renamed later) */
1626 for (z = 0; z < 8; z++)
1627 A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z));
1628 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
1629 gpr++;
1630
1631 if (emu->card_capabilities->emu_model) {
1632 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
1633 dev_info(emu->card->dev, "EMU outputs on\n");
1634 for (z = 0; z < 8; z++) {
1635 if (emu->card_capabilities->ca0108_chip) {
1636 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
1637 } else {
1638 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
1639 }
1640 }
1641 } else {
1642 /* analog speakers */
1643 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback);
1644 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2);
1645 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4);
1646 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5);
1647 if (emu->card_capabilities->spk71)
1648 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6);
1649
1650 /* headphone */
1651 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback);
1652
1653 /* IEC958 Optical Raw Playback Switch */
1654 gpr_map[gpr++] = 0;
1655 gpr_map[gpr++] = 0x1008;
1656 gpr_map[gpr++] = 0xffff0000;
1657 for (z = 0; z < 2; z++) {
1658 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
1659 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
1660 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
1661 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
1662 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
1663 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
1664 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
1665 if ((z==1) && (emu->card_capabilities->spdif_bug)) {
1666 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
1667 dev_info(emu->card->dev,
1668 "Installing spdif_bug patch: %s\n",
1669 emu->card_capabilities->name);
1670 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
1671 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1672 } else {
1673 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1674 }
1675 }
1676 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
1677 gpr += 2;
1678
1679 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2);
1680 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4);
1681 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5);
1682 }
1683
1684 /* ADC buffer */
1685 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
1686 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback);
1687 #else
1688 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
1689 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
1690 #endif
1691
1692 if (emu->card_capabilities->emu_model) {
1693 /* Capture 16 channels of S32_LE sound. */
1694 if (emu->card_capabilities->ca0108_chip) {
1695 dev_info(emu->card->dev, "EMU2 inputs on\n");
1696 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */
1697
1698 snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1699 icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0));
1700 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
1701 // need to be delayed as well; we use an auxiliary register for that.
1702 for (z = 1; z < 0x10; z++) {
1703 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
1704 bit_shifter16,
1705 A_GPR(gpr),
1706 A_FXBUS2(z*2) );
1707 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000);
1708 gpr_map[gpr++] = 0x00000000;
1709 }
1710 } else {
1711 dev_info(emu->card->dev, "EMU inputs on\n");
1712 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */
1713
1714 /*
1715 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
1716 gpr, tmp);
1717 */
1718 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
1719 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1720 * will need to also be delayed; we use an auxiliary register for that. */
1721 for (z = 1; z < 0x10; z++) {
1722 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
1723 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
1724 gpr_map[gpr++] = 0x00000000;
1725 }
1726 }
1727
1728 #if 0
1729 for (z = 4; z < 8; z++) {
1730 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1731 }
1732 for (z = 0xc; z < 0x10; z++) {
1733 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1734 }
1735 #endif
1736 } else {
1737 /* EFX capture - capture the 16 EXTINs */
1738 /* Capture 16 channels of S16_LE sound */
1739 for (z = 0; z < 16; z++) {
1740 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
1741 }
1742 }
1743
1744 #endif /* JCD test */
1745 /*
1746 * ok, set up done..
1747 */
1748
1749 if (gpr > 512) {
1750 snd_BUG();
1751 err = -EIO;
1752 goto __err;
1753 }
1754
1755 /* clear remaining instruction memory */
1756 while (ptr < 0x400)
1757 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
1758
1759 icode->gpr_add_control_count = nctl;
1760 icode->gpr_add_controls = controls;
1761 emu->support_tlv = 1; /* support TLV */
1762 err = snd_emu10k1_icode_poke(emu, icode, true);
1763 emu->support_tlv = 0; /* clear again */
1764
1765 __err:
1766 kfree(controls);
1767 __err_ctrls:
1768 kfree(icode->gpr_map);
1769 __err_gpr:
1770 kfree(icode);
1771 return err;
1772 }
1773
1774
1775 /*
1776 * initial DSP configuration for Emu10k1
1777 */
1778
1779 /* Volumes are in the [-2^31, 0] range, zero being mute. */
1780 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1781 {
1782 OP(icode, ptr, iMAC1, dst, C_00000000, src, vol);
1783 }
1784 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1785 {
1786 OP(icode, ptr, iMAC1, dst, dst, src, vol);
1787 }
1788
1789 #define VOLUME(icode, ptr, dst, src, vol) \
1790 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1791 #define VOLUME_IN(icode, ptr, dst, src, vol) \
1792 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1793 #define VOLUME_ADD(icode, ptr, dst, src, vol) \
1794 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1795 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
1796 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1797 #define VOLUME_OUT(icode, ptr, dst, src, vol) \
1798 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1799 #define _SWITCH(icode, ptr, dst, src, sw) \
1800 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1801 #define SWITCH(icode, ptr, dst, src, sw) \
1802 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1803 #define SWITCH_IN(icode, ptr, dst, src, sw) \
1804 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1805 #define _SWITCH_NEG(icode, ptr, dst, src) \
1806 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1807 #define SWITCH_NEG(icode, ptr, dst, src) \
1808 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1809
1810
1811 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
1812 {
1813 int err, i, z, gpr, tmp, playback, capture;
1814 u32 ptr, ptr_skip;
1815 struct snd_emu10k1_fx8010_code *icode;
1816 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
1817 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1818 u32 *gpr_map;
1819
1820 err = -ENOMEM;
1821 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1822 if (!icode)
1823 return err;
1824
1825 icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512,
1826 sizeof(u_int32_t), GFP_KERNEL);
1827 if (!icode->gpr_map)
1828 goto __err_gpr;
1829
1830 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1831 sizeof(struct snd_emu10k1_fx8010_control_gpr),
1832 GFP_KERNEL);
1833 if (!controls)
1834 goto __err_ctrls;
1835
1836 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
1837 if (!ipcm)
1838 goto __err_ipcm;
1839
1840 gpr_map = icode->gpr_map;
1841
1842 icode->tram_data_map = icode->gpr_map + 256;
1843 icode->tram_addr_map = icode->tram_data_map + 160;
1844 icode->code = icode->tram_addr_map + 160;
1845
1846 /* clear free GPRs */
1847 memset(icode->gpr_valid, 0xff, 256 / 8);
1848
1849 /* clear TRAM data & address lines */
1850 memset(icode->tram_valid, 0xff, 160 / 8);
1851
1852 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
1853 ptr = 0; i = 0;
1854 /* we have 12 inputs */
1855 playback = SND_EMU10K1_INPUTS;
1856 /* we have 6 playback channels and tone control doubles */
1857 capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS;
1858 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
1859 tmp = 0x88; /* we need 4 temporary GPR */
1860 /* from 0x8c to 0xff is the area for tone control */
1861
1862 /*
1863 * Process FX Buses
1864 */
1865 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008);
1866 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008);
1867 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008);
1868 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008);
1869 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008);
1870 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008);
1871 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008);
1872 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008);
1873 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
1874 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
1875 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008);
1876 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008);
1877
1878 /* Raw S/PDIF PCM */
1879 ipcm->substream = 0;
1880 ipcm->channels = 2;
1881 ipcm->tram_start = 0;
1882 ipcm->buffer_size = (64 * 1024) / 2;
1883 ipcm->gpr_size = gpr++;
1884 ipcm->gpr_ptr = gpr++;
1885 ipcm->gpr_count = gpr++;
1886 ipcm->gpr_tmpcount = gpr++;
1887 ipcm->gpr_trigger = gpr++;
1888 ipcm->gpr_running = gpr++;
1889 ipcm->etram[0] = 0;
1890 ipcm->etram[1] = 1;
1891
1892 gpr_map[gpr + 0] = 0xfffff000;
1893 gpr_map[gpr + 1] = 0xffff0000;
1894 gpr_map[gpr + 2] = 0x70000000;
1895 gpr_map[gpr + 3] = 0x00000007;
1896 gpr_map[gpr + 4] = 0x001f << 11;
1897 gpr_map[gpr + 5] = 0x001c << 11;
1898 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
1899 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
1900 gpr_map[gpr + 8] = 0x2000000 + (2<<11);
1901 gpr_map[gpr + 9] = 0x4000000 + (2<<11);
1902 gpr_map[gpr + 10] = 1<<11;
1903 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
1904 gpr_map[gpr + 12] = 0;
1905
1906 /* if the trigger flag is not set, skip */
1907 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
1908 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
1909 /* if the running flag is set, we're running */
1910 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
1911 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
1912 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
1913 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
1914 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
1915 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
1916 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
1917
1918 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
1919 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
1920 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
1921 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
1922
1923 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
1924 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1925 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1926 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1927 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
1928
1929 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
1930 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1931 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1932 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1933 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
1934
1935 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
1936 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
1937 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
1938 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
1939 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
1940
1941 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
1942 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1943 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
1944 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
1945 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
1946
1947 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
1948 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
1949
1950 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
1951 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
1952
1953 /* 24: */
1954 gpr += 13;
1955
1956 /* Wave Playback Volume */
1957 for (z = 0; z < 2; z++)
1958 VOLUME(icode, &ptr, playback + z, z, gpr + z);
1959 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
1960 gpr += 2;
1961
1962 /* Wave Surround Playback Volume */
1963 for (z = 0; z < 2; z++)
1964 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
1965 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
1966 gpr += 2;
1967
1968 /* Wave Center/LFE Playback Volume */
1969 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
1970 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004);
1971 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
1972 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
1973 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
1974 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
1975
1976 /* Wave Capture Volume + Switch */
1977 for (z = 0; z < 2; z++) {
1978 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
1979 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
1980 }
1981 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
1982 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
1983 gpr += 4;
1984
1985 /* Synth Playback Volume */
1986 for (z = 0; z < 2; z++)
1987 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
1988 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
1989 gpr += 2;
1990
1991 /* Synth Capture Volume + Switch */
1992 for (z = 0; z < 2; z++) {
1993 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
1994 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1995 }
1996 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
1997 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
1998 gpr += 4;
1999
2000 /* Surround Digital Playback Volume (renamed later without Digital) */
2001 for (z = 0; z < 2; z++)
2002 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
2003 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
2004 gpr += 2;
2005
2006 /* Surround Capture Volume + Switch */
2007 for (z = 0; z < 2; z++) {
2008 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
2009 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2010 }
2011 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
2012 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
2013 gpr += 4;
2014
2015 /* Center Playback Volume (renamed later without Digital) */
2016 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
2017 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
2018
2019 /* LFE Playback Volume + Switch (renamed later without Digital) */
2020 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
2021 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
2022
2023 /* Front Playback Volume */
2024 for (z = 0; z < 2; z++)
2025 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
2026 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
2027 gpr += 2;
2028
2029 /* Front Capture Volume + Switch */
2030 for (z = 0; z < 2; z++) {
2031 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
2032 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2033 }
2034 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
2035 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
2036 gpr += 3;
2037
2038 /*
2039 * Process inputs
2040 */
2041
2042 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
2043 /* AC'97 Playback Volume */
2044 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
2045 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
2046 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
2047 /* AC'97 Capture Volume */
2048 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
2049 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
2050 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
2051 }
2052
2053 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
2054 /* IEC958 TTL Playback Volume */
2055 for (z = 0; z < 2; z++)
2056 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
2057 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
2058 gpr += 2;
2059
2060 /* IEC958 TTL Capture Volume + Switch */
2061 for (z = 0; z < 2; z++) {
2062 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
2063 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2064 }
2065 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
2066 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
2067 gpr += 4;
2068 }
2069
2070 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
2071 /* Zoom Video Playback Volume */
2072 for (z = 0; z < 2; z++)
2073 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
2074 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
2075 gpr += 2;
2076
2077 /* Zoom Video Capture Volume + Switch */
2078 for (z = 0; z < 2; z++) {
2079 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
2080 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2081 }
2082 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
2083 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
2084 gpr += 4;
2085 }
2086
2087 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
2088 /* IEC958 Optical Playback Volume */
2089 for (z = 0; z < 2; z++)
2090 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
2091 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
2092 gpr += 2;
2093
2094 /* IEC958 Optical Capture Volume */
2095 for (z = 0; z < 2; z++) {
2096 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
2097 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2098 }
2099 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
2100 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
2101 gpr += 4;
2102 }
2103
2104 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
2105 /* Line LiveDrive Playback Volume */
2106 for (z = 0; z < 2; z++)
2107 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
2108 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
2109 gpr += 2;
2110
2111 /* Line LiveDrive Capture Volume + Switch */
2112 for (z = 0; z < 2; z++) {
2113 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
2114 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2115 }
2116 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
2117 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
2118 gpr += 4;
2119 }
2120
2121 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
2122 /* IEC958 Coax Playback Volume */
2123 for (z = 0; z < 2; z++)
2124 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
2125 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
2126 gpr += 2;
2127
2128 /* IEC958 Coax Capture Volume + Switch */
2129 for (z = 0; z < 2; z++) {
2130 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
2131 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2132 }
2133 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
2134 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
2135 gpr += 4;
2136 }
2137
2138 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
2139 /* Line LiveDrive Playback Volume */
2140 for (z = 0; z < 2; z++)
2141 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
2142 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
2143 controls[i-1].id.index = 1;
2144 gpr += 2;
2145
2146 /* Line LiveDrive Capture Volume */
2147 for (z = 0; z < 2; z++) {
2148 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
2149 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2150 }
2151 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
2152 controls[i-1].id.index = 1;
2153 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
2154 controls[i-1].id.index = 1;
2155 gpr += 4;
2156 }
2157
2158 /*
2159 * Process tone control
2160 */
2161 ctl = &controls[i + 0];
2162 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
2163 strcpy(ctl->id.name, "Tone Control - Bass");
2164 ctl->vcount = 2;
2165 ctl->count = 10;
2166 ctl->min = 0;
2167 ctl->max = 40;
2168 ctl->value[0] = ctl->value[1] = 20;
2169 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2170 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
2171 ctl = &controls[i + 1];
2172 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
2173 strcpy(ctl->id.name, "Tone Control - Treble");
2174 ctl->vcount = 2;
2175 ctl->count = 10;
2176 ctl->min = 0;
2177 ctl->max = 40;
2178 ctl->value[0] = ctl->value[1] = 20;
2179 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2180 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
2181
2182 #define BASS_GPR 0x8c
2183 #define TREBLE_GPR 0x96
2184
2185 for (z = 0; z < 5; z++) {
2186 int j;
2187 for (j = 0; j < 2; j++) {
2188 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
2189 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
2190 }
2191 }
2192 i += 2;
2193
2194 OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000);
2195 snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
2196 gpr++;
2197 OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr));
2198 ptr_skip = ptr;
2199 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
2200 int j, k, l, d;
2201 for (j = 0; j < 2; j++) { /* left/right */
2202 k = 0xa0 + (z * 8) + (j * 4);
2203 l = 0xd0 + (z * 8) + (j * 4);
2204 d = playback + z * 2 + j;
2205
2206 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
2207 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
2208 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
2209 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
2210 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
2211 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
2212
2213 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
2214 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
2215 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
2216 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
2217 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
2218 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
2219
2220 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
2221
2222 if (z == 2) /* center */
2223 break;
2224 }
2225 }
2226 gpr_map[gpr++] = ptr - ptr_skip;
2227
2228 #undef BASS_GPR
2229 #undef TREBLE_GPR
2230
2231 /*
2232 * Process outputs
2233 */
2234 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
2235 /* AC'97 Playback Volume */
2236
2237 for (z = 0; z < 2; z++)
2238 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000);
2239 }
2240
2241 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
2242 /* IEC958 Optical Raw Playback Switch */
2243
2244 for (z = 0; z < 2; z++) {
2245 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
2246 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
2247 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2248 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2249 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
2250 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2251 #endif
2252 }
2253
2254 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
2255 gpr += 2;
2256 }
2257
2258 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
2259 /* Headphone Playback Volume */
2260
2261 for (z = 0; z < 2; z++) {
2262 SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z);
2263 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
2264 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2265 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2266 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
2267 }
2268
2269 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
2270 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
2271 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
2272 controls[i-1].id.index = 1;
2273 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
2274 controls[i-1].id.index = 1;
2275
2276 gpr += 4;
2277 }
2278
2279 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
2280 for (z = 0; z < 2; z++)
2281 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
2282
2283 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
2284 for (z = 0; z < 2; z++)
2285 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
2286
2287 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
2288 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2289 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000);
2290 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000);
2291 #else
2292 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000);
2293 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000);
2294 #endif
2295 }
2296
2297 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
2298 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2299 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000);
2300 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000);
2301 #else
2302 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000);
2303 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000);
2304 #endif
2305 }
2306
2307 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
2308 for (z = 0; z < 2; z++)
2309 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
2310 #endif
2311
2312 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
2313 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
2314
2315 /* EFX capture - capture the 16 EXTINS */
2316 if (emu->card_capabilities->sblive51) {
2317 for (z = 0; z < 16; z++) {
2318 s8 c = snd_emu10k1_sblive51_fxbus2_map[z];
2319 if (c != -1)
2320 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c));
2321 }
2322 } else {
2323 for (z = 0; z < 16; z++)
2324 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2325 }
2326
2327
2328 if (gpr > tmp) {
2329 snd_BUG();
2330 err = -EIO;
2331 goto __err;
2332 }
2333 if (i > SND_EMU10K1_GPR_CONTROLS) {
2334 snd_BUG();
2335 err = -EIO;
2336 goto __err;
2337 }
2338
2339 /* clear remaining instruction memory */
2340 while (ptr < 0x200)
2341 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
2342
2343 err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size);
2344 if (err < 0)
2345 goto __err;
2346 icode->gpr_add_control_count = i;
2347 icode->gpr_add_controls = controls;
2348 emu->support_tlv = 1; /* support TLV */
2349 err = snd_emu10k1_icode_poke(emu, icode, true);
2350 emu->support_tlv = 0; /* clear again */
2351 if (err >= 0)
2352 err = snd_emu10k1_ipcm_poke(emu, ipcm);
2353 __err:
2354 kfree(ipcm);
2355 __err_ipcm:
2356 kfree(controls);
2357 __err_ctrls:
2358 kfree(icode->gpr_map);
2359 __err_gpr:
2360 kfree(icode);
2361 return err;
2362 }
2363
2364 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
2365 {
2366 spin_lock_init(&emu->fx8010.irq_lock);
2367 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
2368 if (emu->audigy)
2369 return _snd_emu10k1_audigy_init_efx(emu);
2370 else
2371 return _snd_emu10k1_init_efx(emu);
2372 }
2373
2374 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
2375 {
2376 /* stop processor */
2377 if (emu->audigy)
2378 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
2379 else
2380 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
2381 }
2382
2383 #if 0 /* FIXME: who use them? */
2384 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
2385 {
2386 if (output < 0 || output >= 6)
2387 return -EINVAL;
2388 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
2389 return 0;
2390 }
2391
2392 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
2393 {
2394 if (output < 0 || output >= 6)
2395 return -EINVAL;
2396 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
2397 return 0;
2398 }
2399 #endif
2400
2401 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
2402 {
2403 u8 size_reg = 0;
2404
2405 /* size is in samples */
2406 if (size != 0) {
2407 size = (size - 1) >> 13;
2408
2409 while (size) {
2410 size >>= 1;
2411 size_reg++;
2412 }
2413 size = 0x2000 << size_reg;
2414 }
2415 if ((emu->fx8010.etram_pages.bytes / 2) == size)
2416 return 0;
2417 spin_lock_irq(&emu->emu_lock);
2418 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2419 spin_unlock_irq(&emu->emu_lock);
2420 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
2421 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
2422 if (emu->fx8010.etram_pages.area != NULL) {
2423 snd_dma_free_pages(&emu->fx8010.etram_pages);
2424 emu->fx8010.etram_pages.area = NULL;
2425 emu->fx8010.etram_pages.bytes = 0;
2426 }
2427
2428 if (size > 0) {
2429 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev,
2430 size * 2, &emu->fx8010.etram_pages) < 0)
2431 return -ENOMEM;
2432 memset(emu->fx8010.etram_pages.area, 0, size * 2);
2433 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2434 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2435 spin_lock_irq(&emu->emu_lock);
2436 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2437 spin_unlock_irq(&emu->emu_lock);
2438 }
2439
2440 return 0;
2441 }
2442
2443 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
2444 {
2445 return 0;
2446 }
2447
2448 static void copy_string(char *dst, const char *src, const char *null, int idx)
2449 {
2450 if (src == NULL)
2451 sprintf(dst, "%s %02X", null, idx);
2452 else
2453 strcpy(dst, src);
2454 }
2455
2456 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
2457 struct snd_emu10k1_fx8010_info *info)
2458 {
2459 const char * const *fxbus, * const *extin, * const *extout;
2460 unsigned short extin_mask, extout_mask;
2461 int res;
2462
2463 info->internal_tram_size = emu->fx8010.itram_size;
2464 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
2465 fxbus = snd_emu10k1_fxbus;
2466 extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins;
2467 extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs;
2468 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask;
2469 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask;
2470 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
2471 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res);
2472 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
2473 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2474 }
2475 for (res = 16; res < 32; res++, extout++)
2476 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2477 info->gpr_controls = emu->fx8010.gpr_count;
2478 }
2479
2480 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
2481 {
2482 struct snd_emu10k1 *emu = hw->private_data;
2483 struct snd_emu10k1_fx8010_info *info;
2484 struct snd_emu10k1_fx8010_code *icode;
2485 struct snd_emu10k1_fx8010_pcm_rec *ipcm;
2486 unsigned int addr;
2487 void __user *argp = (void __user *)arg;
2488 int res;
2489
2490 switch (cmd) {
2491 case SNDRV_EMU10K1_IOCTL_PVERSION:
2492 emu->support_tlv = 1;
2493 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
2494 case SNDRV_EMU10K1_IOCTL_INFO:
2495 info = kzalloc(sizeof(*info), GFP_KERNEL);
2496 if (!info)
2497 return -ENOMEM;
2498 snd_emu10k1_fx8010_info(emu, info);
2499 if (copy_to_user(argp, info, sizeof(*info))) {
2500 kfree(info);
2501 return -EFAULT;
2502 }
2503 kfree(info);
2504 return 0;
2505 case SNDRV_EMU10K1_IOCTL_CODE_POKE:
2506 if (!capable(CAP_SYS_ADMIN))
2507 return -EPERM;
2508
2509 icode = memdup_user(argp, sizeof(*icode));
2510 if (IS_ERR(icode))
2511 return PTR_ERR(icode);
2512 res = snd_emu10k1_icode_poke(emu, icode, false);
2513 kfree(icode);
2514 return res;
2515 case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
2516 icode = memdup_user(argp, sizeof(*icode));
2517 if (IS_ERR(icode))
2518 return PTR_ERR(icode);
2519 res = snd_emu10k1_icode_peek(emu, icode);
2520 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
2521 kfree(icode);
2522 return -EFAULT;
2523 }
2524 kfree(icode);
2525 return res;
2526 case SNDRV_EMU10K1_IOCTL_PCM_POKE:
2527 ipcm = memdup_user(argp, sizeof(*ipcm));
2528 if (IS_ERR(ipcm))
2529 return PTR_ERR(ipcm);
2530 res = snd_emu10k1_ipcm_poke(emu, ipcm);
2531 kfree(ipcm);
2532 return res;
2533 case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
2534 ipcm = memdup_user(argp, sizeof(*ipcm));
2535 if (IS_ERR(ipcm))
2536 return PTR_ERR(ipcm);
2537 res = snd_emu10k1_ipcm_peek(emu, ipcm);
2538 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
2539 kfree(ipcm);
2540 return -EFAULT;
2541 }
2542 kfree(ipcm);
2543 return res;
2544 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
2545 if (!capable(CAP_SYS_ADMIN))
2546 return -EPERM;
2547 if (get_user(addr, (unsigned int __user *)argp))
2548 return -EFAULT;
2549 mutex_lock(&emu->fx8010.lock);
2550 res = snd_emu10k1_fx8010_tram_setup(emu, addr);
2551 mutex_unlock(&emu->fx8010.lock);
2552 return res;
2553 case SNDRV_EMU10K1_IOCTL_STOP:
2554 if (!capable(CAP_SYS_ADMIN))
2555 return -EPERM;
2556 if (emu->audigy)
2557 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2558 else
2559 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2560 return 0;
2561 case SNDRV_EMU10K1_IOCTL_CONTINUE:
2562 if (!capable(CAP_SYS_ADMIN))
2563 return -EPERM;
2564 if (emu->audigy)
2565 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
2566 else
2567 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
2568 return 0;
2569 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
2570 if (!capable(CAP_SYS_ADMIN))
2571 return -EPERM;
2572 if (emu->audigy)
2573 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
2574 else
2575 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
2576 udelay(10);
2577 if (emu->audigy)
2578 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2579 else
2580 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2581 return 0;
2582 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
2583 if (!capable(CAP_SYS_ADMIN))
2584 return -EPERM;
2585 if (get_user(addr, (unsigned int __user *)argp))
2586 return -EFAULT;
2587 if (emu->audigy) {
2588 if (addr > A_DBG_STEP_ADDR)
2589 return -EINVAL;
2590 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2591 udelay(10);
2592 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr);
2593 } else {
2594 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR)
2595 return -EINVAL;
2596 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2597 udelay(10);
2598 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr);
2599 }
2600 return 0;
2601 case SNDRV_EMU10K1_IOCTL_DBG_READ:
2602 if (emu->audigy)
2603 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
2604 else
2605 addr = snd_emu10k1_ptr_read(emu, DBG, 0);
2606 if (put_user(addr, (unsigned int __user *)argp))
2607 return -EFAULT;
2608 return 0;
2609 }
2610 return -ENOTTY;
2611 }
2612
2613 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
2614 {
2615 return 0;
2616 }
2617
2618 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
2619 {
2620 struct snd_hwdep *hw;
2621 int err;
2622
2623 err = snd_hwdep_new(emu->card, "FX8010", device, &hw);
2624 if (err < 0)
2625 return err;
2626 strcpy(hw->name, "EMU10K1 (FX8010)");
2627 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
2628 hw->ops.open = snd_emu10k1_fx8010_open;
2629 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
2630 hw->ops.release = snd_emu10k1_fx8010_release;
2631 hw->private_data = emu;
2632 return 0;
2633 }
2634
2635 #ifdef CONFIG_PM_SLEEP
2636 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
2637 {
2638 int len;
2639
2640 len = emu->audigy ? 0x200 : 0x100;
2641 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
2642 if (! emu->saved_gpr)
2643 return -ENOMEM;
2644 len = emu->audigy ? 0x100 : 0xa0;
2645 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
2646 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
2647 if (! emu->tram_val_saved || ! emu->tram_addr_saved)
2648 return -ENOMEM;
2649 len = emu->audigy ? 2 * 1024 : 2 * 512;
2650 emu->saved_icode = vmalloc(array_size(len, 4));
2651 if (! emu->saved_icode)
2652 return -ENOMEM;
2653 return 0;
2654 }
2655
2656 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
2657 {
2658 kfree(emu->saved_gpr);
2659 kfree(emu->tram_val_saved);
2660 kfree(emu->tram_addr_saved);
2661 vfree(emu->saved_icode);
2662 }
2663
2664 /*
2665 * save/restore GPR, TRAM and codes
2666 */
2667 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
2668 {
2669 int i, len;
2670
2671 len = emu->audigy ? 0x200 : 0x100;
2672 for (i = 0; i < len; i++)
2673 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
2674
2675 len = emu->audigy ? 0x100 : 0xa0;
2676 for (i = 0; i < len; i++) {
2677 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
2678 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
2679 if (emu->audigy) {
2680 emu->tram_addr_saved[i] >>= 12;
2681 emu->tram_addr_saved[i] |=
2682 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
2683 }
2684 }
2685
2686 len = emu->audigy ? 2 * 1024 : 2 * 512;
2687 for (i = 0; i < len; i++)
2688 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
2689 }
2690
2691 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
2692 {
2693 int i, len;
2694
2695 /* set up TRAM */
2696 if (emu->fx8010.etram_pages.bytes > 0) {
2697 unsigned size, size_reg = 0;
2698 size = emu->fx8010.etram_pages.bytes / 2;
2699 size = (size - 1) >> 13;
2700 while (size) {
2701 size >>= 1;
2702 size_reg++;
2703 }
2704 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2705 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2706 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2707 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2708 }
2709
2710 if (emu->audigy)
2711 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
2712 else
2713 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
2714
2715 len = emu->audigy ? 0x200 : 0x100;
2716 for (i = 0; i < len; i++)
2717 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
2718
2719 len = emu->audigy ? 0x100 : 0xa0;
2720 for (i = 0; i < len; i++) {
2721 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
2722 emu->tram_val_saved[i]);
2723 if (! emu->audigy)
2724 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2725 emu->tram_addr_saved[i]);
2726 else {
2727 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2728 emu->tram_addr_saved[i] << 12);
2729 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2730 emu->tram_addr_saved[i] >> 20);
2731 }
2732 }
2733
2734 len = emu->audigy ? 2 * 1024 : 2 * 512;
2735 for (i = 0; i < len; i++)
2736 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
2737
2738 /* start FX processor when the DSP code is updated */
2739 if (emu->audigy)
2740 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2741 else
2742 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2743 }
2744 #endif
2745
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