1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/time.h>
24 #include <linux/string.h>
25 #include <linux/pm_runtime.h>
26
27 #include <sound/core.h>
28 #include <sound/initval.h>
29
30 #include <sound/hda_codec.h>
31 #include "hda_controller.h"
32
33 /* Defines for Nvidia Tegra HDA support */
34 #define HDA_BAR0 0x8000
35
36 #define HDA_CFG_CMD 0x1004
37 #define HDA_CFG_BAR0 0x1010
38
39 #define HDA_ENABLE_IO_SPACE (1 << 0)
40 #define HDA_ENABLE_MEM_SPACE (1 << 1)
41 #define HDA_ENABLE_BUS_MASTER (1 << 2)
42 #define HDA_ENABLE_SERR (1 << 8)
43 #define HDA_DISABLE_INTR (1 << 10)
44 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
45 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
46
47 /* IPFS */
48 #define HDA_IPFS_CONFIG 0x180
49 #define HDA_IPFS_EN_FPCI 0x1
50
51 #define HDA_IPFS_FPCI_BAR0 0x80
52 #define HDA_FPCI_BAR0_START 0x40
53
54 #define HDA_IPFS_INTR_MASK 0x188
55 #define HDA_IPFS_EN_INTR (1 << 16)
56
57 /* FPCI */
58 #define FPCI_DBG_CFG_2 0x10F4
59 #define FPCI_GCAP_NSDO_SHIFT 18
60 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
61
62 /* max number of SDs */
63 #define NUM_CAPTURE_SD 1
64 #define NUM_PLAYBACK_SD 1
65
66 /*
67 * Tegra194 does not reflect correct number of SDO lines. Below macro
68 * is used to update the GCAP register to workaround the issue.
69 */
70 #define TEGRA194_NUM_SDO_LINES 4
71
72 struct hda_tegra_soc {
73 bool has_hda2codec_2x_reset;
74 bool has_hda2hdmi;
75 };
76
77 struct hda_tegra {
78 struct azx chip;
79 struct device *dev;
80 struct reset_control_bulk_data resets[3];
81 struct clk_bulk_data clocks[3];
82 unsigned int nresets;
83 unsigned int nclocks;
84 void __iomem *regs;
85 struct work_struct probe_work;
86 const struct hda_tegra_soc *soc;
87 };
88
89 #ifdef CONFIG_PM
90 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
91 module_param(power_save, bint, 0644);
92 MODULE_PARM_DESC(power_save,
93 "Automatic power-saving timeout (in seconds, 0 = disable).");
94 #else
95 #define power_save 0
96 #endif
97
98 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
99
100 static void hda_tegra_init(struct hda_tegra *hda)
101 {
102 u32 v;
103
104 /* Enable PCI access */
105 v = readl(hda->regs + HDA_IPFS_CONFIG);
106 v |= HDA_IPFS_EN_FPCI;
107 writel(v, hda->regs + HDA_IPFS_CONFIG);
108
109 /* Enable MEM/IO space and bus master */
110 v = readl(hda->regs + HDA_CFG_CMD);
111 v &= ~HDA_DISABLE_INTR;
112 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
113 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
114 writel(v, hda->regs + HDA_CFG_CMD);
115
116 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
117 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
118 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
119
120 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
121 v |= HDA_IPFS_EN_INTR;
122 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
123 }
124
125 /*
126 * power management
127 */
128 static int __maybe_unused hda_tegra_suspend(struct device *dev)
129 {
130 struct snd_card *card = dev_get_drvdata(dev);
131 int rc;
132
133 rc = pm_runtime_force_suspend(dev);
134 if (rc < 0)
135 return rc;
136 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
137
138 return 0;
139 }
140
141 static int __maybe_unused hda_tegra_resume(struct device *dev)
142 {
143 struct snd_card *card = dev_get_drvdata(dev);
144 int rc;
145
146 rc = pm_runtime_force_resume(dev);
147 if (rc < 0)
148 return rc;
149 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
150
151 return 0;
152 }
153
154 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
155 {
156 struct snd_card *card = dev_get_drvdata(dev);
157 struct azx *chip = card->private_data;
158 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
159
160 if (chip && chip->running) {
161 /* enable controller wake up event */
162 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
163 STATESTS_INT_MASK);
164
165 azx_stop_chip(chip);
166 azx_enter_link_reset(chip);
167 }
168 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
169
170 return 0;
171 }
172
173 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
174 {
175 struct snd_card *card = dev_get_drvdata(dev);
176 struct azx *chip = card->private_data;
177 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
178 int rc;
179
180 if (!chip->running) {
181 rc = reset_control_bulk_assert(hda->nresets, hda->resets);
182 if (rc)
183 return rc;
184 }
185
186 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
187 if (rc != 0)
188 return rc;
189 if (chip->running) {
190 hda_tegra_init(hda);
191 azx_init_chip(chip, 1);
192 /* disable controller wake up event*/
193 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
194 ~STATESTS_INT_MASK);
195 } else {
196 usleep_range(10, 100);
197
198 rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
199 if (rc)
200 return rc;
201 }
202
203 return 0;
204 }
205
206 static const struct dev_pm_ops hda_tegra_pm = {
207 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
208 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
209 hda_tegra_runtime_resume,
210 NULL)
211 };
212
213 static int hda_tegra_dev_disconnect(struct snd_device *device)
214 {
215 struct azx *chip = device->device_data;
216
217 chip->bus.shutdown = 1;
218 return 0;
219 }
220
221 /*
222 * destructor
223 */
224 static int hda_tegra_dev_free(struct snd_device *device)
225 {
226 struct azx *chip = device->device_data;
227 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
228
229 cancel_work_sync(&hda->probe_work);
230 if (azx_bus(chip)->chip_init) {
231 azx_stop_all_streams(chip);
232 azx_stop_chip(chip);
233 }
234
235 azx_free_stream_pages(chip);
236 azx_free_streams(chip);
237 snd_hdac_bus_exit(azx_bus(chip));
238
239 return 0;
240 }
241
242 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
243 {
244 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
245 struct hdac_bus *bus = azx_bus(chip);
246 struct resource *res;
247
248 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
249 if (IS_ERR(hda->regs))
250 return PTR_ERR(hda->regs);
251
252 bus->remap_addr = hda->regs + HDA_BAR0;
253 bus->addr = res->start + HDA_BAR0;
254
255 hda_tegra_init(hda);
256
257 return 0;
258 }
259
260 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
261 {
262 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
263 struct hdac_bus *bus = azx_bus(chip);
264 struct snd_card *card = chip->card;
265 int err;
266 unsigned short gcap;
267 int irq_id = platform_get_irq(pdev, 0);
268 const char *sname, *drv_name = "tegra-hda";
269 struct device_node *np = pdev->dev.of_node;
270
271 if (irq_id < 0)
272 return irq_id;
273
274 err = hda_tegra_init_chip(chip, pdev);
275 if (err)
276 return err;
277
278 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
279 IRQF_SHARED, KBUILD_MODNAME, chip);
280 if (err) {
281 dev_err(chip->card->dev,
282 "unable to request IRQ %d, disabling device\n",
283 irq_id);
284 return err;
285 }
286 bus->irq = irq_id;
287 bus->dma_stop_delay = 100;
288 card->sync_irq = bus->irq;
289
290 /*
291 * Tegra194 has 4 SDO lines and the STRIPE can be used to
292 * indicate how many of the SDO lines the stream should be
293 * striped. But GCAP register does not reflect the true
294 * capability of HW. Below workaround helps to fix this.
295 *
296 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
297 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
298 */
299 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
300 u32 val;
301
302 dev_info(card->dev, "Override SDO lines to %u\n",
303 TEGRA194_NUM_SDO_LINES);
304
305 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
306 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
307 writel(val, hda->regs + FPCI_DBG_CFG_2);
308 }
309
310 gcap = azx_readw(chip, GCAP);
311 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
312
313 chip->align_buffer_size = 1;
314
315 /* read number of streams from GCAP register instead of using
316 * hardcoded value
317 */
318 chip->capture_streams = (gcap >> 8) & 0x0f;
319
320 /* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
321 * but the HW output stream descriptor programming should start with
322 * offset 0x20*4 from base stream descriptor address. This will be a
323 * problem while calculating the offset for output stream descriptor
324 * which will be considering input stream also. So here output stream
325 * starts with offset 0 which is wrong as HW register for output stream
326 * offset starts with 4.
327 */
328 if (of_device_is_compatible(np, "nvidia,tegra234-hda"))
329 chip->capture_streams = 4;
330
331 chip->playback_streams = (gcap >> 12) & 0x0f;
332 if (!chip->playback_streams && !chip->capture_streams) {
333 /* gcap didn't give any info, switching to old method */
334 chip->playback_streams = NUM_PLAYBACK_SD;
335 chip->capture_streams = NUM_CAPTURE_SD;
336 }
337 chip->capture_index_offset = 0;
338 chip->playback_index_offset = chip->capture_streams;
339 chip->num_streams = chip->playback_streams + chip->capture_streams;
340
341 /* initialize streams */
342 err = azx_init_streams(chip);
343 if (err < 0) {
344 dev_err(card->dev, "failed to initialize streams: %d\n", err);
345 return err;
346 }
347
348 err = azx_alloc_stream_pages(chip);
349 if (err < 0) {
350 dev_err(card->dev, "failed to allocate stream pages: %d\n",
351 err);
352 return err;
353 }
354
355 /* initialize chip */
356 azx_init_chip(chip, 1);
357
358 /*
359 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
360 * 4 SDO lines due to legacy design limitation. Following
361 * is, from HD Audio Specification (Revision 1.0a), used to
362 * control striping of the stream across multiple SDO lines
363 * for sample rates <= 48K.
364 *
365 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
366 *
367 * Due to legacy design issue it is recommended that above
368 * ratio must be greater than 8. Since number of SDO lines is
369 * in powers of 2, next available ratio is 16 which can be
370 * used as a limiting factor here.
371 */
372 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
373 chip->bus.core.sdo_limit = 16;
374
375 /* codec detection */
376 if (!bus->codec_mask) {
377 dev_err(card->dev, "no codecs found!\n");
378 return -ENODEV;
379 }
380
381 /* driver name */
382 strscpy(card->driver, drv_name, sizeof(card->driver));
383 /* shortname for card */
384 sname = of_get_property(np, "nvidia,model", NULL);
385 if (!sname)
386 sname = drv_name;
387 if (strlen(sname) > sizeof(card->shortname))
388 dev_info(card->dev, "truncating shortname for card\n");
389 strscpy(card->shortname, sname, sizeof(card->shortname));
390
391 /* longname for card */
392 snprintf(card->longname, sizeof(card->longname),
393 "%s at 0x%lx irq %i",
394 card->shortname, bus->addr, bus->irq);
395
396 return 0;
397 }
398
399 /*
400 * constructor
401 */
402
403 static void hda_tegra_probe_work(struct work_struct *work);
404
405 static int hda_tegra_create(struct snd_card *card,
406 unsigned int driver_caps,
407 struct hda_tegra *hda)
408 {
409 static const struct snd_device_ops ops = {
410 .dev_disconnect = hda_tegra_dev_disconnect,
411 .dev_free = hda_tegra_dev_free,
412 };
413 struct azx *chip;
414 int err;
415
416 chip = &hda->chip;
417
418 mutex_init(&chip->open_mutex);
419 chip->card = card;
420 chip->ops = &hda_tegra_ops;
421 chip->driver_caps = driver_caps;
422 chip->driver_type = driver_caps & 0xff;
423 chip->dev_index = 0;
424 chip->jackpoll_interval = msecs_to_jiffies(5000);
425 INIT_LIST_HEAD(&chip->pcm_list);
426
427 chip->codec_probe_mask = -1;
428
429 chip->single_cmd = false;
430 chip->snoop = true;
431
432 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
433
434 err = azx_bus_init(chip, NULL);
435 if (err < 0)
436 return err;
437
438 chip->bus.core.sync_write = 0;
439 chip->bus.core.needs_damn_long_delay = 1;
440 chip->bus.core.aligned_mmio = 1;
441 chip->bus.jackpoll_in_suspend = 1;
442
443 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
444 if (err < 0) {
445 dev_err(card->dev, "Error creating device\n");
446 return err;
447 }
448
449 return 0;
450 }
451
452 static const struct hda_tegra_soc tegra30_data = {
453 .has_hda2codec_2x_reset = true,
454 .has_hda2hdmi = true,
455 };
456
457 static const struct hda_tegra_soc tegra194_data = {
458 .has_hda2codec_2x_reset = false,
459 .has_hda2hdmi = true,
460 };
461
462 static const struct hda_tegra_soc tegra234_data = {
463 .has_hda2codec_2x_reset = true,
464 .has_hda2hdmi = false,
465 };
466
467 static const struct of_device_id hda_tegra_match[] = {
468 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
469 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
470 { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
471 {},
472 };
473 MODULE_DEVICE_TABLE(of, hda_tegra_match);
474
475 static int hda_tegra_probe(struct platform_device *pdev)
476 {
477 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
478 AZX_DCAPS_PM_RUNTIME |
479 AZX_DCAPS_4K_BDLE_BOUNDARY;
480 struct snd_card *card;
481 struct azx *chip;
482 struct hda_tegra *hda;
483 int err;
484
485 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
486 if (!hda)
487 return -ENOMEM;
488 hda->dev = &pdev->dev;
489 chip = &hda->chip;
490
491 hda->soc = of_device_get_match_data(&pdev->dev);
492
493 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
494 THIS_MODULE, 0, &card);
495 if (err < 0) {
496 dev_err(&pdev->dev, "Error creating card!\n");
497 return err;
498 }
499
500 hda->resets[hda->nresets++].id = "hda";
501
502 /*
503 * "hda2hdmi" is not applicable for Tegra234. This is because the
504 * codec is separate IP and not under display SOR partition now.
505 */
506 if (hda->soc->has_hda2hdmi)
507 hda->resets[hda->nresets++].id = "hda2hdmi";
508
509 /*
510 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
511 * be updated to reflect this, but to have backward compatibility
512 * below is necessary.
513 */
514 if (hda->soc->has_hda2codec_2x_reset)
515 hda->resets[hda->nresets++].id = "hda2codec_2x";
516
517 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
518 hda->resets);
519 if (err)
520 goto out_free;
521
522 hda->clocks[hda->nclocks++].id = "hda";
523 if (hda->soc->has_hda2hdmi)
524 hda->clocks[hda->nclocks++].id = "hda2hdmi";
525 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
526
527 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
528 if (err < 0)
529 goto out_free;
530
531 err = hda_tegra_create(card, driver_flags, hda);
532 if (err < 0)
533 goto out_free;
534 card->private_data = chip;
535
536 dev_set_drvdata(&pdev->dev, card);
537
538 pm_runtime_enable(hda->dev);
539 if (!azx_has_pm_runtime(chip))
540 pm_runtime_forbid(hda->dev);
541
542 schedule_work(&hda->probe_work);
543
544 return 0;
545
546 out_free:
547 snd_card_free(card);
548 return err;
549 }
550
551 static void hda_tegra_probe_work(struct work_struct *work)
552 {
553 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
554 struct azx *chip = &hda->chip;
555 struct platform_device *pdev = to_platform_device(hda->dev);
556 int err;
557
558 pm_runtime_get_sync(hda->dev);
559 err = hda_tegra_first_init(chip, pdev);
560 if (err < 0)
561 goto out_free;
562
563 /* create codec instances */
564 err = azx_probe_codecs(chip, 8);
565 if (err < 0)
566 goto out_free;
567
568 err = azx_codec_configure(chip);
569 if (err < 0)
570 goto out_free;
571
572 err = snd_card_register(chip->card);
573 if (err < 0)
574 goto out_free;
575
576 chip->running = 1;
577 snd_hda_set_power_save(&chip->bus, power_save * 1000);
578
579 out_free:
580 pm_runtime_put(hda->dev);
581 return; /* no error return from async probe */
582 }
583
584 static void hda_tegra_remove(struct platform_device *pdev)
585 {
586 snd_card_free(dev_get_drvdata(&pdev->dev));
587 pm_runtime_disable(&pdev->dev);
588 }
589
590 static void hda_tegra_shutdown(struct platform_device *pdev)
591 {
592 struct snd_card *card = dev_get_drvdata(&pdev->dev);
593 struct azx *chip;
594
595 if (!card)
596 return;
597 chip = card->private_data;
598 if (chip && chip->running)
599 azx_stop_chip(chip);
600 }
601
602 static struct platform_driver tegra_platform_hda = {
603 .driver = {
604 .name = "tegra-hda",
605 .pm = &hda_tegra_pm,
606 .of_match_table = hda_tegra_match,
607 },
608 .probe = hda_tegra_probe,
609 .remove_new = hda_tegra_remove,
610 .shutdown = hda_tegra_shutdown,
611 };
612 module_platform_driver(tegra_platform_hda);
613
614 MODULE_DESCRIPTION("Tegra HDA bus driver");
615 MODULE_LICENSE("GPL v2");
616
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