1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
4 *
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8
9 #ifndef __CS8409_PATCH_H
10 #define __CS8409_PATCH_H
11
12 #include <linux/pci.h>
13 #include <sound/tlv.h>
14 #include <linux/workqueue.h>
15 #include <sound/cs42l42.h>
16 #include <sound/hda_codec.h>
17 #include "hda_local.h"
18 #include "hda_auto_parser.h"
19 #include "hda_jack.h"
20 #include "hda_generic.h"
21
22 /* CS8409 Specific Definitions */
23
24 enum cs8409_pins {
25 CS8409_PIN_ROOT,
26 CS8409_PIN_AFG,
27 CS8409_PIN_ASP1_OUT_A,
28 CS8409_PIN_ASP1_OUT_B,
29 CS8409_PIN_ASP1_OUT_C,
30 CS8409_PIN_ASP1_OUT_D,
31 CS8409_PIN_ASP1_OUT_E,
32 CS8409_PIN_ASP1_OUT_F,
33 CS8409_PIN_ASP1_OUT_G,
34 CS8409_PIN_ASP1_OUT_H,
35 CS8409_PIN_ASP2_OUT_A,
36 CS8409_PIN_ASP2_OUT_B,
37 CS8409_PIN_ASP2_OUT_C,
38 CS8409_PIN_ASP2_OUT_D,
39 CS8409_PIN_ASP2_OUT_E,
40 CS8409_PIN_ASP2_OUT_F,
41 CS8409_PIN_ASP2_OUT_G,
42 CS8409_PIN_ASP2_OUT_H,
43 CS8409_PIN_ASP1_IN_A,
44 CS8409_PIN_ASP1_IN_B,
45 CS8409_PIN_ASP1_IN_C,
46 CS8409_PIN_ASP1_IN_D,
47 CS8409_PIN_ASP1_IN_E,
48 CS8409_PIN_ASP1_IN_F,
49 CS8409_PIN_ASP1_IN_G,
50 CS8409_PIN_ASP1_IN_H,
51 CS8409_PIN_ASP2_IN_A,
52 CS8409_PIN_ASP2_IN_B,
53 CS8409_PIN_ASP2_IN_C,
54 CS8409_PIN_ASP2_IN_D,
55 CS8409_PIN_ASP2_IN_E,
56 CS8409_PIN_ASP2_IN_F,
57 CS8409_PIN_ASP2_IN_G,
58 CS8409_PIN_ASP2_IN_H,
59 CS8409_PIN_DMIC1,
60 CS8409_PIN_DMIC2,
61 CS8409_PIN_ASP1_TRANSMITTER_A,
62 CS8409_PIN_ASP1_TRANSMITTER_B,
63 CS8409_PIN_ASP1_TRANSMITTER_C,
64 CS8409_PIN_ASP1_TRANSMITTER_D,
65 CS8409_PIN_ASP1_TRANSMITTER_E,
66 CS8409_PIN_ASP1_TRANSMITTER_F,
67 CS8409_PIN_ASP1_TRANSMITTER_G,
68 CS8409_PIN_ASP1_TRANSMITTER_H,
69 CS8409_PIN_ASP2_TRANSMITTER_A,
70 CS8409_PIN_ASP2_TRANSMITTER_B,
71 CS8409_PIN_ASP2_TRANSMITTER_C,
72 CS8409_PIN_ASP2_TRANSMITTER_D,
73 CS8409_PIN_ASP2_TRANSMITTER_E,
74 CS8409_PIN_ASP2_TRANSMITTER_F,
75 CS8409_PIN_ASP2_TRANSMITTER_G,
76 CS8409_PIN_ASP2_TRANSMITTER_H,
77 CS8409_PIN_ASP1_RECEIVER_A,
78 CS8409_PIN_ASP1_RECEIVER_B,
79 CS8409_PIN_ASP1_RECEIVER_C,
80 CS8409_PIN_ASP1_RECEIVER_D,
81 CS8409_PIN_ASP1_RECEIVER_E,
82 CS8409_PIN_ASP1_RECEIVER_F,
83 CS8409_PIN_ASP1_RECEIVER_G,
84 CS8409_PIN_ASP1_RECEIVER_H,
85 CS8409_PIN_ASP2_RECEIVER_A,
86 CS8409_PIN_ASP2_RECEIVER_B,
87 CS8409_PIN_ASP2_RECEIVER_C,
88 CS8409_PIN_ASP2_RECEIVER_D,
89 CS8409_PIN_ASP2_RECEIVER_E,
90 CS8409_PIN_ASP2_RECEIVER_F,
91 CS8409_PIN_ASP2_RECEIVER_G,
92 CS8409_PIN_ASP2_RECEIVER_H,
93 CS8409_PIN_DMIC1_IN,
94 CS8409_PIN_DMIC2_IN,
95 CS8409_PIN_BEEP_GEN,
96 CS8409_PIN_VENDOR_WIDGET
97 };
98
99 enum cs8409_coefficient_index_registers {
100 CS8409_DEV_CFG1,
101 CS8409_DEV_CFG2,
102 CS8409_DEV_CFG3,
103 CS8409_ASP1_CLK_CTRL1,
104 CS8409_ASP1_CLK_CTRL2,
105 CS8409_ASP1_CLK_CTRL3,
106 CS8409_ASP2_CLK_CTRL1,
107 CS8409_ASP2_CLK_CTRL2,
108 CS8409_ASP2_CLK_CTRL3,
109 CS8409_DMIC_CFG,
110 CS8409_BEEP_CFG,
111 ASP1_RX_NULL_INS_RMV,
112 ASP1_Rx_RATE1,
113 ASP1_Rx_RATE2,
114 ASP1_Tx_NULL_INS_RMV,
115 ASP1_Tx_RATE1,
116 ASP1_Tx_RATE2,
117 ASP2_Rx_NULL_INS_RMV,
118 ASP2_Rx_RATE1,
119 ASP2_Rx_RATE2,
120 ASP2_Tx_NULL_INS_RMV,
121 ASP2_Tx_RATE1,
122 ASP2_Tx_RATE2,
123 ASP1_SYNC_CTRL,
124 ASP2_SYNC_CTRL,
125 ASP1_A_TX_CTRL1,
126 ASP1_A_TX_CTRL2,
127 ASP1_B_TX_CTRL1,
128 ASP1_B_TX_CTRL2,
129 ASP1_C_TX_CTRL1,
130 ASP1_C_TX_CTRL2,
131 ASP1_D_TX_CTRL1,
132 ASP1_D_TX_CTRL2,
133 ASP1_E_TX_CTRL1,
134 ASP1_E_TX_CTRL2,
135 ASP1_F_TX_CTRL1,
136 ASP1_F_TX_CTRL2,
137 ASP1_G_TX_CTRL1,
138 ASP1_G_TX_CTRL2,
139 ASP1_H_TX_CTRL1,
140 ASP1_H_TX_CTRL2,
141 ASP2_A_TX_CTRL1,
142 ASP2_A_TX_CTRL2,
143 ASP2_B_TX_CTRL1,
144 ASP2_B_TX_CTRL2,
145 ASP2_C_TX_CTRL1,
146 ASP2_C_TX_CTRL2,
147 ASP2_D_TX_CTRL1,
148 ASP2_D_TX_CTRL2,
149 ASP2_E_TX_CTRL1,
150 ASP2_E_TX_CTRL2,
151 ASP2_F_TX_CTRL1,
152 ASP2_F_TX_CTRL2,
153 ASP2_G_TX_CTRL1,
154 ASP2_G_TX_CTRL2,
155 ASP2_H_TX_CTRL1,
156 ASP2_H_TX_CTRL2,
157 ASP1_A_RX_CTRL1,
158 ASP1_A_RX_CTRL2,
159 ASP1_B_RX_CTRL1,
160 ASP1_B_RX_CTRL2,
161 ASP1_C_RX_CTRL1,
162 ASP1_C_RX_CTRL2,
163 ASP1_D_RX_CTRL1,
164 ASP1_D_RX_CTRL2,
165 ASP1_E_RX_CTRL1,
166 ASP1_E_RX_CTRL2,
167 ASP1_F_RX_CTRL1,
168 ASP1_F_RX_CTRL2,
169 ASP1_G_RX_CTRL1,
170 ASP1_G_RX_CTRL2,
171 ASP1_H_RX_CTRL1,
172 ASP1_H_RX_CTRL2,
173 ASP2_A_RX_CTRL1,
174 ASP2_A_RX_CTRL2,
175 ASP2_B_RX_CTRL1,
176 ASP2_B_RX_CTRL2,
177 ASP2_C_RX_CTRL1,
178 ASP2_C_RX_CTRL2,
179 ASP2_D_RX_CTRL1,
180 ASP2_D_RX_CTRL2,
181 ASP2_E_RX_CTRL1,
182 ASP2_E_RX_CTRL2,
183 ASP2_F_RX_CTRL1,
184 ASP2_F_RX_CTRL2,
185 ASP2_G_RX_CTRL1,
186 ASP2_G_RX_CTRL2,
187 ASP2_H_RX_CTRL1,
188 ASP2_H_RX_CTRL2,
189 CS8409_I2C_ADDR,
190 CS8409_I2C_DATA,
191 CS8409_I2C_CTRL,
192 CS8409_I2C_STS,
193 CS8409_I2C_QWRITE,
194 CS8409_I2C_QREAD,
195 CS8409_SPI_CTRL,
196 CS8409_SPI_TX_DATA,
197 CS8409_SPI_RX_DATA,
198 CS8409_SPI_STS,
199 CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/
200 CS8409_PFE_COEF_W2,
201 CS8409_PFE_CTRL1,
202 CS8409_PFE_CTRL2,
203 CS8409_PRE_SCALE_ATTN1,
204 CS8409_PRE_SCALE_ATTN2,
205 CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/
206 CS8409_PFE_COEF_MON2,
207 CS8409_ASP1_INTRN_STS,
208 CS8409_ASP2_INTRN_STS,
209 CS8409_ASP1_RX_SCLK_COUNT,
210 CS8409_ASP1_TX_SCLK_COUNT,
211 CS8409_ASP2_RX_SCLK_COUNT,
212 CS8409_ASP2_TX_SCLK_COUNT,
213 CS8409_ASP_UNS_RESP_MASK,
214 CS8409_LOOPBACK_CTRL = 0x80,
215 CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */
216 };
217
218 /* CS42L42 Specific Definitions */
219
220 #define CS8409_MAX_CODECS 8
221 #define CS42L42_VOLUMES (4U)
222 #define CS42L42_HP_VOL_REAL_MIN (-63)
223 #define CS42L42_HP_VOL_REAL_MAX (0)
224 #define CS42L42_AMIC_VOL_REAL_MIN (-97)
225 #define CS42L42_AMIC_VOL_REAL_MAX (12)
226 #define CS42L42_REG_AMIC_VOL_MASK (0x00FF)
227 #define CS42L42_HSTYPE_MASK (0x03)
228 #define CS42L42_I2C_TIMEOUT_US (20000)
229 #define CS42L42_I2C_SLEEP_US (2000)
230 #define CS42L42_PDN_TIMEOUT_US (250000)
231 #define CS42L42_PDN_SLEEP_US (2000)
232 #define CS42L42_INIT_TIMEOUT_MS (45)
233 #define CS42L42_FULL_SCALE_VOL_MASK (2)
234 #define CS42L42_FULL_SCALE_VOL_0DB (1)
235 #define CS42L42_FULL_SCALE_VOL_MINUS6DB (0)
236
237 /* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */
238
239 #define CS42L42_I2C_ADDR (0x48 << 1)
240 #define CS8409_CS42L42_RESET GENMASK(5, 5) /* CS8409_GPIO5 */
241 #define CS8409_CS42L42_INT GENMASK(4, 4) /* CS8409_GPIO4 */
242 #define CS8409_CYBORG_SPEAKER_PDN GENMASK(2, 2) /* CS8409_GPIO2 */
243 #define CS8409_WARLOCK_SPEAKER_PDN GENMASK(1, 1) /* CS8409_GPIO1 */
244 #define CS8409_CS42L42_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A
245 #define CS8409_CS42L42_SPK_PIN_NID CS8409_PIN_ASP2_TRANSMITTER_A
246 #define CS8409_CS42L42_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A
247 #define CS8409_CS42L42_DMIC_PIN_NID CS8409_PIN_DMIC1_IN
248 #define CS8409_CS42L42_DMIC_ADC_PIN_NID CS8409_PIN_DMIC1
249
250 /* Dolphin */
251
252 #define DOLPHIN_C0_I2C_ADDR (0x48 << 1)
253 #define DOLPHIN_C1_I2C_ADDR (0x49 << 1)
254 #define DOLPHIN_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A
255 #define DOLPHIN_LO_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_B
256 #define DOLPHIN_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A
257
258 #define DOLPHIN_C0_INT GENMASK(4, 4)
259 #define DOLPHIN_C1_INT GENMASK(0, 0)
260 #define DOLPHIN_C0_RESET GENMASK(5, 5)
261 #define DOLPHIN_C1_RESET GENMASK(1, 1)
262 #define DOLPHIN_WAKE (DOLPHIN_C0_INT | DOLPHIN_C1_INT)
263
264 enum {
265 CS8409_BULLSEYE,
266 CS8409_WARLOCK,
267 CS8409_WARLOCK_MLK,
268 CS8409_WARLOCK_MLK_DUAL_MIC,
269 CS8409_CYBORG,
270 CS8409_FIXUPS,
271 CS8409_DOLPHIN,
272 CS8409_DOLPHIN_FIXUPS,
273 CS8409_ODIN,
274 };
275
276 enum {
277 CS8409_CODEC0,
278 CS8409_CODEC1
279 };
280
281 enum {
282 CS42L42_VOL_ADC,
283 CS42L42_VOL_DAC,
284 };
285
286 #define CS42L42_ADC_VOL_OFFSET (CS42L42_VOL_ADC)
287 #define CS42L42_DAC_CH0_VOL_OFFSET (CS42L42_VOL_DAC)
288 #define CS42L42_DAC_CH1_VOL_OFFSET (CS42L42_VOL_DAC + 1)
289
290 struct cs8409_i2c_param {
291 unsigned int addr;
292 unsigned int value;
293 };
294
295 struct cs8409_cir_param {
296 unsigned int nid;
297 unsigned int cir;
298 unsigned int coeff;
299 };
300
301 struct sub_codec {
302 struct hda_codec *codec;
303 unsigned int addr;
304 unsigned int reset_gpio;
305 unsigned int irq_mask;
306 const struct cs8409_i2c_param *init_seq;
307 unsigned int init_seq_num;
308
309 unsigned int hp_jack_in:1;
310 unsigned int mic_jack_in:1;
311 unsigned int suspended:1;
312 unsigned int paged:1;
313 unsigned int last_page;
314 unsigned int hsbias_hiz;
315 unsigned int full_scale_vol:1;
316 unsigned int no_type_dect:1;
317
318 s8 vol[CS42L42_VOLUMES];
319 };
320
321 struct cs8409_spec {
322 struct hda_gen_spec gen;
323 struct hda_codec *codec;
324
325 struct sub_codec *scodecs[CS8409_MAX_CODECS];
326 unsigned int num_scodecs;
327
328 unsigned int gpio_mask;
329 unsigned int gpio_dir;
330 unsigned int gpio_data;
331
332 int speaker_pdn_gpio;
333
334 struct mutex i2c_mux;
335 unsigned int i2c_clck_enabled;
336 unsigned int dev_addr;
337 struct delayed_work i2c_clk_work;
338
339 unsigned int playback_started:1;
340 unsigned int capture_started:1;
341 unsigned int init_done:1;
342 unsigned int build_ctrl_done:1;
343
344 /* verb exec op override */
345 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
346 unsigned int *res);
347 };
348
349 extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer;
350 extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer;
351
352 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo);
353 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
354 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);
355
356 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback;
357 extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture;
358 extern const struct snd_pci_quirk cs8409_fixup_tbl[];
359 extern const struct hda_model_fixup cs8409_models[];
360 extern const struct hda_fixup cs8409_fixups[];
361 extern const struct hda_verb cs8409_cs42l42_init_verbs[];
362 extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[];
363 extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[];
364 extern struct sub_codec cs8409_cs42l42_codec;
365
366 extern const struct hda_verb dolphin_init_verbs[];
367 extern const struct cs8409_cir_param dolphin_hw_cfg[];
368 extern struct sub_codec dolphin_cs42l42_0;
369 extern struct sub_codec dolphin_cs42l42_1;
370
371 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
372 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);
373
374 #endif
375
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.