1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
34 #include "hda_jack.h"
35 #include "hda_controller.h"
36
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45 static bool enable_silent_stream =
46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47 module_param(enable_silent_stream, bool, 0644);
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50 static bool enable_all_pins;
51 module_param(enable_all_pins, bool, 0444);
52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
53
54 struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 bool assigned; /* the stream has been assigned */
57 bool silent_stream; /* silent stream activated */
58 unsigned int channels_min;
59 unsigned int channels_max;
60 u32 rates;
61 u64 formats;
62 unsigned int maxbps;
63 };
64
65 /* max. connections to a widget */
66 #define HDA_MAX_CONNECTIONS 32
67
68 struct hdmi_spec_per_pin {
69 hda_nid_t pin_nid;
70 int dev_id;
71 /* pin idx, different device entries on the same pin use the same idx */
72 int pin_nid_idx;
73 int num_mux_nids;
74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
75 int mux_idx;
76 hda_nid_t cvt_nid;
77
78 struct hda_codec *codec;
79 struct hdmi_eld sink_eld;
80 struct mutex lock;
81 struct delayed_work work;
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 int prev_pcm_idx; /* previously assigned pcm index */
85 int repoll_count;
86 bool setup; /* the stream has been set up by prepare callback */
87 bool silent_stream;
88 int channels; /* current number of channels */
89 bool non_pcm;
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
92 #ifdef CONFIG_SND_PROC_FS
93 struct snd_info_entry *proc_entry;
94 #endif
95 };
96
97 /* operations used by generic code that can be overridden by patches */
98 struct hdmi_ops {
99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int dev_id, unsigned char *buf, int *eld_size);
101
102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
103 int dev_id,
104 int ca, int active_channels, int conn_type);
105
106 /* enable/disable HBR (HD passthrough) */
107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
108 int dev_id, bool hbr);
109
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
112 int format);
113
114 void (*pin_cvt_fixup)(struct hda_codec *codec,
115 struct hdmi_spec_per_pin *per_pin,
116 hda_nid_t cvt_nid);
117 };
118
119 struct hdmi_pcm {
120 struct hda_pcm *pcm;
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
123 };
124
125 enum {
126 SILENT_STREAM_OFF = 0,
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
128 SILENT_STREAM_I915, /* Intel i915 extension */
129 };
130
131 struct hdmi_spec {
132 struct hda_codec *codec;
133 int num_cvts;
134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
135 hda_nid_t cvt_nids[4]; /* only for haswell fix */
136
137 /*
138 * num_pins is the number of virtual pins
139 * for example, there are 3 pins, and each pin
140 * has 4 device entries, then the num_pins is 12
141 */
142 int num_pins;
143 /*
144 * num_nids is the number of real pins
145 * In the above example, num_nids is 3
146 */
147 int num_nids;
148 /*
149 * dev_num is the number of device entries
150 * on each pin.
151 * In the above example, dev_num is 4
152 */
153 int dev_num;
154 struct snd_array pins; /* struct hdmi_spec_per_pin */
155 struct hdmi_pcm pcm_rec[8];
156 struct mutex pcm_lock;
157 struct mutex bind_lock; /* for audio component binding */
158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
160 int pcm_used; /* counter of pcm_rec[] */
161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
164 */
165 unsigned long pcm_in_use;
166
167 struct hdmi_eld temp_eld;
168 struct hdmi_ops ops;
169
170 bool dyn_pin_out;
171 bool static_pcm_mapping;
172 /* hdmi interrupt trigger control flag for Nvidia codec */
173 bool hdmi_intr_trig_ctrl;
174 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
175
176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
177 /*
178 * Non-generic VIA/NVIDIA specific
179 */
180 struct hda_multi_out multiout;
181 struct hda_pcm_stream pcm_playback;
182
183 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
184 bool acomp_registered; /* audio component registered in this driver */
185 bool force_connect; /* force connectivity */
186 struct drm_audio_component_audio_ops drm_audio_ops;
187 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
188
189 struct hdac_chmap chmap;
190 hda_nid_t vendor_nid;
191 const int *port_map;
192 int port_num;
193 int silent_stream_type;
194 };
195
196 #ifdef CONFIG_SND_HDA_COMPONENT
197 static inline bool codec_has_acomp(struct hda_codec *codec)
198 {
199 struct hdmi_spec *spec = codec->spec;
200 return spec->use_acomp_notifier;
201 }
202 #else
203 #define codec_has_acomp(codec) false
204 #endif
205
206 struct hdmi_audio_infoframe {
207 u8 type; /* 0x84 */
208 u8 ver; /* 0x01 */
209 u8 len; /* 0x0a */
210
211 u8 checksum;
212
213 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
214 u8 SS01_SF24;
215 u8 CXT04;
216 u8 CA;
217 u8 LFEPBL01_LSV36_DM_INH7;
218 };
219
220 struct dp_audio_infoframe {
221 u8 type; /* 0x84 */
222 u8 len; /* 0x1b */
223 u8 ver; /* 0x11 << 2 */
224
225 u8 CC02_CT47; /* match with HDMI infoframe from this on */
226 u8 SS01_SF24;
227 u8 CXT04;
228 u8 CA;
229 u8 LFEPBL01_LSV36_DM_INH7;
230 };
231
232 union audio_infoframe {
233 struct hdmi_audio_infoframe hdmi;
234 struct dp_audio_infoframe dp;
235 DECLARE_FLEX_ARRAY(u8, bytes);
236 };
237
238 /*
239 * HDMI routines
240 */
241
242 #define get_pin(spec, idx) \
243 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
244 #define get_cvt(spec, idx) \
245 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
246 /* obtain hdmi_pcm object assigned to idx */
247 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
248 /* obtain hda_pcm object assigned to idx */
249 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
250
251 static int pin_id_to_pin_index(struct hda_codec *codec,
252 hda_nid_t pin_nid, int dev_id)
253 {
254 struct hdmi_spec *spec = codec->spec;
255 int pin_idx;
256 struct hdmi_spec_per_pin *per_pin;
257
258 /*
259 * (dev_id == -1) means it is NON-MST pin
260 * return the first virtual pin on this port
261 */
262 if (dev_id == -1)
263 dev_id = 0;
264
265 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
266 per_pin = get_pin(spec, pin_idx);
267 if ((per_pin->pin_nid == pin_nid) &&
268 (per_pin->dev_id == dev_id))
269 return pin_idx;
270 }
271
272 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
273 return -EINVAL;
274 }
275
276 static int hinfo_to_pcm_index(struct hda_codec *codec,
277 struct hda_pcm_stream *hinfo)
278 {
279 struct hdmi_spec *spec = codec->spec;
280 int pcm_idx;
281
282 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
283 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
284 return pcm_idx;
285
286 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
287 return -EINVAL;
288 }
289
290 static int hinfo_to_pin_index(struct hda_codec *codec,
291 struct hda_pcm_stream *hinfo)
292 {
293 struct hdmi_spec *spec = codec->spec;
294 struct hdmi_spec_per_pin *per_pin;
295 int pin_idx;
296
297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
298 per_pin = get_pin(spec, pin_idx);
299 if (per_pin->pcm &&
300 per_pin->pcm->pcm->stream == hinfo)
301 return pin_idx;
302 }
303
304 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
305 hinfo_to_pcm_index(codec, hinfo));
306 return -EINVAL;
307 }
308
309 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
310 int pcm_idx)
311 {
312 int i;
313 struct hdmi_spec_per_pin *per_pin;
314
315 for (i = 0; i < spec->num_pins; i++) {
316 per_pin = get_pin(spec, i);
317 if (per_pin->pcm_idx == pcm_idx)
318 return per_pin;
319 }
320 return NULL;
321 }
322
323 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
324 {
325 struct hdmi_spec *spec = codec->spec;
326 int cvt_idx;
327
328 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
329 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
330 return cvt_idx;
331
332 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
333 return -EINVAL;
334 }
335
336 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
337 struct snd_ctl_elem_info *uinfo)
338 {
339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
340 struct hdmi_spec *spec = codec->spec;
341 struct hdmi_spec_per_pin *per_pin;
342 struct hdmi_eld *eld;
343 int pcm_idx;
344
345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
346
347 pcm_idx = kcontrol->private_value;
348 mutex_lock(&spec->pcm_lock);
349 per_pin = pcm_idx_to_pin(spec, pcm_idx);
350 if (!per_pin) {
351 /* no pin is bound to the pcm */
352 uinfo->count = 0;
353 goto unlock;
354 }
355 eld = &per_pin->sink_eld;
356 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
357
358 unlock:
359 mutex_unlock(&spec->pcm_lock);
360 return 0;
361 }
362
363 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365 {
366 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
367 struct hdmi_spec *spec = codec->spec;
368 struct hdmi_spec_per_pin *per_pin;
369 struct hdmi_eld *eld;
370 int pcm_idx;
371 int err = 0;
372
373 pcm_idx = kcontrol->private_value;
374 mutex_lock(&spec->pcm_lock);
375 per_pin = pcm_idx_to_pin(spec, pcm_idx);
376 if (!per_pin) {
377 /* no pin is bound to the pcm */
378 memset(ucontrol->value.bytes.data, 0,
379 ARRAY_SIZE(ucontrol->value.bytes.data));
380 goto unlock;
381 }
382
383 eld = &per_pin->sink_eld;
384 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
385 eld->eld_size > ELD_MAX_SIZE) {
386 snd_BUG();
387 err = -EINVAL;
388 goto unlock;
389 }
390
391 memset(ucontrol->value.bytes.data, 0,
392 ARRAY_SIZE(ucontrol->value.bytes.data));
393 if (eld->eld_valid)
394 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
395 eld->eld_size);
396
397 unlock:
398 mutex_unlock(&spec->pcm_lock);
399 return err;
400 }
401
402 static const struct snd_kcontrol_new eld_bytes_ctl = {
403 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
404 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
405 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
406 .name = "ELD",
407 .info = hdmi_eld_ctl_info,
408 .get = hdmi_eld_ctl_get,
409 };
410
411 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
412 int device)
413 {
414 struct snd_kcontrol *kctl;
415 struct hdmi_spec *spec = codec->spec;
416 int err;
417
418 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
419 if (!kctl)
420 return -ENOMEM;
421 kctl->private_value = pcm_idx;
422 kctl->id.device = device;
423
424 /* no pin nid is associated with the kctl now
425 * tbd: associate pin nid to eld ctl later
426 */
427 err = snd_hda_ctl_add(codec, 0, kctl);
428 if (err < 0)
429 return err;
430
431 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
432 return 0;
433 }
434
435 #ifdef BE_PARANOID
436 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
437 int *packet_index, int *byte_index)
438 {
439 int val;
440
441 val = snd_hda_codec_read(codec, pin_nid, 0,
442 AC_VERB_GET_HDMI_DIP_INDEX, 0);
443
444 *packet_index = val >> 5;
445 *byte_index = val & 0x1f;
446 }
447 #endif
448
449 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
450 int packet_index, int byte_index)
451 {
452 int val;
453
454 val = (packet_index << 5) | (byte_index & 0x1f);
455
456 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
457 }
458
459 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
460 unsigned char val)
461 {
462 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
463 }
464
465 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
466 {
467 struct hdmi_spec *spec = codec->spec;
468 int pin_out;
469
470 /* Unmute */
471 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
472 snd_hda_codec_write(codec, pin_nid, 0,
473 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
474
475 if (spec->dyn_pin_out)
476 /* Disable pin out until stream is active */
477 pin_out = 0;
478 else
479 /* Enable pin out: some machines with GM965 gets broken output
480 * when the pin is disabled or changed while using with HDMI
481 */
482 pin_out = PIN_OUT;
483
484 snd_hda_codec_write(codec, pin_nid, 0,
485 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
486 }
487
488 /*
489 * ELD proc files
490 */
491
492 #ifdef CONFIG_SND_PROC_FS
493 static void print_eld_info(struct snd_info_entry *entry,
494 struct snd_info_buffer *buffer)
495 {
496 struct hdmi_spec_per_pin *per_pin = entry->private_data;
497
498 mutex_lock(&per_pin->lock);
499 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid,
500 per_pin->dev_id, per_pin->cvt_nid);
501 mutex_unlock(&per_pin->lock);
502 }
503
504 static void write_eld_info(struct snd_info_entry *entry,
505 struct snd_info_buffer *buffer)
506 {
507 struct hdmi_spec_per_pin *per_pin = entry->private_data;
508
509 mutex_lock(&per_pin->lock);
510 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
511 mutex_unlock(&per_pin->lock);
512 }
513
514 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
515 {
516 char name[32];
517 struct hda_codec *codec = per_pin->codec;
518 struct snd_info_entry *entry;
519 int err;
520
521 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
522 err = snd_card_proc_new(codec->card, name, &entry);
523 if (err < 0)
524 return err;
525
526 snd_info_set_text_ops(entry, per_pin, print_eld_info);
527 entry->c.text.write = write_eld_info;
528 entry->mode |= 0200;
529 per_pin->proc_entry = entry;
530
531 return 0;
532 }
533
534 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
535 {
536 if (!per_pin->codec->bus->shutdown) {
537 snd_info_free_entry(per_pin->proc_entry);
538 per_pin->proc_entry = NULL;
539 }
540 }
541 #else
542 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
543 int index)
544 {
545 return 0;
546 }
547 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
548 {
549 }
550 #endif
551
552 /*
553 * Audio InfoFrame routines
554 */
555
556 /*
557 * Enable Audio InfoFrame Transmission
558 */
559 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
560 hda_nid_t pin_nid)
561 {
562 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
563 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
564 AC_DIPXMIT_BEST);
565 }
566
567 /*
568 * Disable Audio InfoFrame Transmission
569 */
570 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
571 hda_nid_t pin_nid)
572 {
573 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
574 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
575 AC_DIPXMIT_DISABLE);
576 }
577
578 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
579 {
580 #ifdef CONFIG_SND_DEBUG_VERBOSE
581 int i;
582 int size;
583
584 size = snd_hdmi_get_eld_size(codec, pin_nid);
585 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
586
587 for (i = 0; i < 8; i++) {
588 size = snd_hda_codec_read(codec, pin_nid, 0,
589 AC_VERB_GET_HDMI_DIP_SIZE, i);
590 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
591 }
592 #endif
593 }
594
595 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
596 {
597 #ifdef BE_PARANOID
598 int i, j;
599 int size;
600 int pi, bi;
601 for (i = 0; i < 8; i++) {
602 size = snd_hda_codec_read(codec, pin_nid, 0,
603 AC_VERB_GET_HDMI_DIP_SIZE, i);
604 if (size == 0)
605 continue;
606
607 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
608 for (j = 1; j < 1000; j++) {
609 hdmi_write_dip_byte(codec, pin_nid, 0x0);
610 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
611 if (pi != i)
612 codec_dbg(codec, "dip index %d: %d != %d\n",
613 bi, pi, i);
614 if (bi == 0) /* byte index wrapped around */
615 break;
616 }
617 codec_dbg(codec,
618 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
619 i, size, j);
620 }
621 #endif
622 }
623
624 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
625 {
626 u8 *bytes = (u8 *)hdmi_ai;
627 u8 sum = 0;
628 int i;
629
630 hdmi_ai->checksum = 0;
631
632 for (i = 0; i < sizeof(*hdmi_ai); i++)
633 sum += bytes[i];
634
635 hdmi_ai->checksum = -sum;
636 }
637
638 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
639 hda_nid_t pin_nid,
640 u8 *dip, int size)
641 {
642 int i;
643
644 hdmi_debug_dip_size(codec, pin_nid);
645 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
646
647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
648 for (i = 0; i < size; i++)
649 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
650 }
651
652 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
653 u8 *dip, int size)
654 {
655 u8 val;
656 int i;
657
658 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
659 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
660 != AC_DIPXMIT_BEST)
661 return false;
662
663 for (i = 0; i < size; i++) {
664 val = snd_hda_codec_read(codec, pin_nid, 0,
665 AC_VERB_GET_HDMI_DIP_DATA, 0);
666 if (val != dip[i])
667 return false;
668 }
669
670 return true;
671 }
672
673 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
674 int dev_id, unsigned char *buf, int *eld_size)
675 {
676 snd_hda_set_dev_select(codec, nid, dev_id);
677
678 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
679 }
680
681 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
682 hda_nid_t pin_nid, int dev_id,
683 int ca, int active_channels,
684 int conn_type)
685 {
686 struct hdmi_spec *spec = codec->spec;
687 union audio_infoframe ai;
688
689 memset(&ai, 0, sizeof(ai));
690 if ((conn_type == 0) || /* HDMI */
691 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
692 (conn_type == 1 && spec->nv_dp_workaround)) {
693 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
694
695 if (conn_type == 0) { /* HDMI */
696 hdmi_ai->type = 0x84;
697 hdmi_ai->ver = 0x01;
698 hdmi_ai->len = 0x0a;
699 } else {/* Nvidia DP */
700 hdmi_ai->type = 0x84;
701 hdmi_ai->ver = 0x1b;
702 hdmi_ai->len = 0x11 << 2;
703 }
704 hdmi_ai->CC02_CT47 = active_channels - 1;
705 hdmi_ai->CA = ca;
706 hdmi_checksum_audio_infoframe(hdmi_ai);
707 } else if (conn_type == 1) { /* DisplayPort */
708 struct dp_audio_infoframe *dp_ai = &ai.dp;
709
710 dp_ai->type = 0x84;
711 dp_ai->len = 0x1b;
712 dp_ai->ver = 0x11 << 2;
713 dp_ai->CC02_CT47 = active_channels - 1;
714 dp_ai->CA = ca;
715 } else {
716 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
717 return;
718 }
719
720 snd_hda_set_dev_select(codec, pin_nid, dev_id);
721
722 /*
723 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
724 * sizeof(*dp_ai) to avoid partial match/update problems when
725 * the user switches between HDMI/DP monitors.
726 */
727 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
728 sizeof(ai))) {
729 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
730 __func__, pin_nid, active_channels, ca);
731 hdmi_stop_infoframe_trans(codec, pin_nid);
732 hdmi_fill_audio_infoframe(codec, pin_nid,
733 ai.bytes, sizeof(ai));
734 hdmi_start_infoframe_trans(codec, pin_nid);
735 }
736 }
737
738 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
739 struct hdmi_spec_per_pin *per_pin,
740 bool non_pcm)
741 {
742 struct hdmi_spec *spec = codec->spec;
743 struct hdac_chmap *chmap = &spec->chmap;
744 hda_nid_t pin_nid = per_pin->pin_nid;
745 int dev_id = per_pin->dev_id;
746 int channels = per_pin->channels;
747 int active_channels;
748 struct hdmi_eld *eld;
749 int ca;
750
751 if (!channels)
752 return;
753
754 snd_hda_set_dev_select(codec, pin_nid, dev_id);
755
756 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
757 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
758 snd_hda_codec_write(codec, pin_nid, 0,
759 AC_VERB_SET_AMP_GAIN_MUTE,
760 AMP_OUT_UNMUTE);
761
762 eld = &per_pin->sink_eld;
763
764 ca = snd_hdac_channel_allocation(&codec->core,
765 eld->info.spk_alloc, channels,
766 per_pin->chmap_set, non_pcm, per_pin->chmap);
767
768 active_channels = snd_hdac_get_active_channels(ca);
769
770 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
771 active_channels);
772
773 /*
774 * always configure channel mapping, it may have been changed by the
775 * user in the meantime
776 */
777 snd_hdac_setup_channel_mapping(&spec->chmap,
778 pin_nid, non_pcm, ca, channels,
779 per_pin->chmap, per_pin->chmap_set);
780
781 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
782 ca, active_channels, eld->info.conn_type);
783
784 per_pin->non_pcm = non_pcm;
785 }
786
787 /*
788 * Unsolicited events
789 */
790
791 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
792
793 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
794 int dev_id)
795 {
796 struct hdmi_spec *spec = codec->spec;
797 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
798
799 if (pin_idx < 0)
800 return;
801 mutex_lock(&spec->pcm_lock);
802 hdmi_present_sense(get_pin(spec, pin_idx), 1);
803 mutex_unlock(&spec->pcm_lock);
804 }
805
806 static void jack_callback(struct hda_codec *codec,
807 struct hda_jack_callback *jack)
808 {
809 /* stop polling when notification is enabled */
810 if (codec_has_acomp(codec))
811 return;
812
813 check_presence_and_report(codec, jack->nid, jack->dev_id);
814 }
815
816 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
817 struct hda_jack_tbl *jack)
818 {
819 jack->jack_dirty = 1;
820
821 codec_dbg(codec,
822 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
823 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
824 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
825
826 check_presence_and_report(codec, jack->nid, jack->dev_id);
827 }
828
829 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
830 {
831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
833 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
834 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
835
836 codec_info(codec,
837 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
838 codec->addr,
839 tag,
840 subtag,
841 cp_state,
842 cp_ready);
843
844 /* TODO */
845 if (cp_state) {
846 ;
847 }
848 if (cp_ready) {
849 ;
850 }
851 }
852
853
854 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
855 {
856 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
857 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
858 struct hda_jack_tbl *jack;
859
860 if (codec_has_acomp(codec))
861 return;
862
863 if (codec->dp_mst) {
864 int dev_entry =
865 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
866
867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
868 } else {
869 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
870 }
871
872 if (!jack) {
873 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
874 return;
875 }
876
877 if (subtag == 0)
878 hdmi_intrinsic_event(codec, res, jack);
879 else
880 hdmi_non_intrinsic_event(codec, res);
881 }
882
883 static void haswell_verify_D0(struct hda_codec *codec,
884 hda_nid_t cvt_nid, hda_nid_t nid)
885 {
886 int pwr;
887
888 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
889 * thus pins could only choose converter 0 for use. Make sure the
890 * converters are in correct power state */
891 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
892 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
893
894 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
895 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
896 AC_PWRST_D0);
897 msleep(40);
898 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
899 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
900 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
901 }
902 }
903
904 /*
905 * Callbacks
906 */
907
908 /* HBR should be Non-PCM, 8 channels */
909 #define is_hbr_format(format) \
910 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
911
912 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
913 int dev_id, bool hbr)
914 {
915 int pinctl, new_pinctl;
916
917 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
918 snd_hda_set_dev_select(codec, pin_nid, dev_id);
919 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
920 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
921
922 if (pinctl < 0)
923 return hbr ? -EINVAL : 0;
924
925 new_pinctl = pinctl & ~AC_PINCTL_EPT;
926 if (hbr)
927 new_pinctl |= AC_PINCTL_EPT_HBR;
928 else
929 new_pinctl |= AC_PINCTL_EPT_NATIVE;
930
931 codec_dbg(codec,
932 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
933 pin_nid,
934 pinctl == new_pinctl ? "" : "new-",
935 new_pinctl);
936
937 if (pinctl != new_pinctl)
938 snd_hda_codec_write(codec, pin_nid, 0,
939 AC_VERB_SET_PIN_WIDGET_CONTROL,
940 new_pinctl);
941 } else if (hbr)
942 return -EINVAL;
943
944 return 0;
945 }
946
947 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
948 hda_nid_t pin_nid, int dev_id,
949 u32 stream_tag, int format)
950 {
951 struct hdmi_spec *spec = codec->spec;
952 unsigned int param;
953 int err;
954
955 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
956 is_hbr_format(format));
957
958 if (err) {
959 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
960 return err;
961 }
962
963 if (spec->intel_hsw_fixup) {
964
965 /*
966 * on recent platforms IEC Coding Type is required for HBR
967 * support, read current Digital Converter settings and set
968 * ICT bitfield if needed.
969 */
970 param = snd_hda_codec_read(codec, cvt_nid, 0,
971 AC_VERB_GET_DIGI_CONVERT_1, 0);
972
973 param = (param >> 16) & ~(AC_DIG3_ICT);
974
975 /* on recent platforms ICT mode is required for HBR support */
976 if (is_hbr_format(format))
977 param |= 0x1;
978
979 snd_hda_codec_write(codec, cvt_nid, 0,
980 AC_VERB_SET_DIGI_CONVERT_3, param);
981 }
982
983 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
984 return 0;
985 }
986
987 /* Try to find an available converter
988 * If pin_idx is less then zero, just try to find an available converter.
989 * Otherwise, try to find an available converter and get the cvt mux index
990 * of the pin.
991 */
992 static int hdmi_choose_cvt(struct hda_codec *codec,
993 int pin_idx, int *cvt_id,
994 bool silent)
995 {
996 struct hdmi_spec *spec = codec->spec;
997 struct hdmi_spec_per_pin *per_pin;
998 struct hdmi_spec_per_cvt *per_cvt = NULL;
999 int cvt_idx, mux_idx = 0;
1000
1001 /* pin_idx < 0 means no pin will be bound to the converter */
1002 if (pin_idx < 0)
1003 per_pin = NULL;
1004 else
1005 per_pin = get_pin(spec, pin_idx);
1006
1007 if (per_pin && per_pin->silent_stream) {
1008 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1009 per_cvt = get_cvt(spec, cvt_idx);
1010 if (per_cvt->assigned && !silent)
1011 return -EBUSY;
1012 if (cvt_id)
1013 *cvt_id = cvt_idx;
1014 return 0;
1015 }
1016
1017 /* Dynamically assign converter to stream */
1018 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1019 per_cvt = get_cvt(spec, cvt_idx);
1020
1021 /* Must not already be assigned */
1022 if (per_cvt->assigned || per_cvt->silent_stream)
1023 continue;
1024 if (per_pin == NULL)
1025 break;
1026 /* Must be in pin's mux's list of converters */
1027 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1028 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1029 break;
1030 /* Not in mux list */
1031 if (mux_idx == per_pin->num_mux_nids)
1032 continue;
1033 break;
1034 }
1035
1036 /* No free converters */
1037 if (cvt_idx == spec->num_cvts)
1038 return -EBUSY;
1039
1040 if (per_pin != NULL)
1041 per_pin->mux_idx = mux_idx;
1042
1043 if (cvt_id)
1044 *cvt_id = cvt_idx;
1045
1046 return 0;
1047 }
1048
1049 /* Assure the pin select the right convetor */
1050 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1051 struct hdmi_spec_per_pin *per_pin)
1052 {
1053 hda_nid_t pin_nid = per_pin->pin_nid;
1054 int mux_idx, curr;
1055
1056 mux_idx = per_pin->mux_idx;
1057 curr = snd_hda_codec_read(codec, pin_nid, 0,
1058 AC_VERB_GET_CONNECT_SEL, 0);
1059 if (curr != mux_idx)
1060 snd_hda_codec_write_cache(codec, pin_nid, 0,
1061 AC_VERB_SET_CONNECT_SEL,
1062 mux_idx);
1063 }
1064
1065 /* get the mux index for the converter of the pins
1066 * converter's mux index is the same for all pins on Intel platform
1067 */
1068 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1069 hda_nid_t cvt_nid)
1070 {
1071 int i;
1072
1073 for (i = 0; i < spec->num_cvts; i++)
1074 if (spec->cvt_nids[i] == cvt_nid)
1075 return i;
1076 return -EINVAL;
1077 }
1078
1079 /* Intel HDMI workaround to fix audio routing issue:
1080 * For some Intel display codecs, pins share the same connection list.
1081 * So a conveter can be selected by multiple pins and playback on any of these
1082 * pins will generate sound on the external display, because audio flows from
1083 * the same converter to the display pipeline. Also muting one pin may make
1084 * other pins have no sound output.
1085 * So this function assures that an assigned converter for a pin is not selected
1086 * by any other pins.
1087 */
1088 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1089 hda_nid_t pin_nid,
1090 int dev_id, int mux_idx)
1091 {
1092 struct hdmi_spec *spec = codec->spec;
1093 hda_nid_t nid;
1094 int cvt_idx, curr;
1095 struct hdmi_spec_per_cvt *per_cvt;
1096 struct hdmi_spec_per_pin *per_pin;
1097 int pin_idx;
1098
1099 /* configure the pins connections */
1100 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1101 int dev_id_saved;
1102 int dev_num;
1103
1104 per_pin = get_pin(spec, pin_idx);
1105 /*
1106 * pin not connected to monitor
1107 * no need to operate on it
1108 */
1109 if (!per_pin->pcm)
1110 continue;
1111
1112 if ((per_pin->pin_nid == pin_nid) &&
1113 (per_pin->dev_id == dev_id))
1114 continue;
1115
1116 /*
1117 * if per_pin->dev_id >= dev_num,
1118 * snd_hda_get_dev_select() will fail,
1119 * and the following operation is unpredictable.
1120 * So skip this situation.
1121 */
1122 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1123 if (per_pin->dev_id >= dev_num)
1124 continue;
1125
1126 nid = per_pin->pin_nid;
1127
1128 /*
1129 * Calling this function should not impact
1130 * on the device entry selection
1131 * So let's save the dev id for each pin,
1132 * and restore it when return
1133 */
1134 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1135 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1136 curr = snd_hda_codec_read(codec, nid, 0,
1137 AC_VERB_GET_CONNECT_SEL, 0);
1138 if (curr != mux_idx) {
1139 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1140 continue;
1141 }
1142
1143
1144 /* choose an unassigned converter. The conveters in the
1145 * connection list are in the same order as in the codec.
1146 */
1147 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1148 per_cvt = get_cvt(spec, cvt_idx);
1149 if (!per_cvt->assigned) {
1150 codec_dbg(codec,
1151 "choose cvt %d for pin NID 0x%x\n",
1152 cvt_idx, nid);
1153 snd_hda_codec_write_cache(codec, nid, 0,
1154 AC_VERB_SET_CONNECT_SEL,
1155 cvt_idx);
1156 break;
1157 }
1158 }
1159 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1160 }
1161 }
1162
1163 /* A wrapper of intel_not_share_asigned_cvt() */
1164 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1165 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1166 {
1167 int mux_idx;
1168 struct hdmi_spec *spec = codec->spec;
1169
1170 /* On Intel platform, the mapping of converter nid to
1171 * mux index of the pins are always the same.
1172 * The pin nid may be 0, this means all pins will not
1173 * share the converter.
1174 */
1175 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1176 if (mux_idx >= 0)
1177 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1178 }
1179
1180 /* skeleton caller of pin_cvt_fixup ops */
1181 static void pin_cvt_fixup(struct hda_codec *codec,
1182 struct hdmi_spec_per_pin *per_pin,
1183 hda_nid_t cvt_nid)
1184 {
1185 struct hdmi_spec *spec = codec->spec;
1186
1187 if (spec->ops.pin_cvt_fixup)
1188 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1189 }
1190
1191 /* called in hdmi_pcm_open when no pin is assigned to the PCM */
1192 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1193 struct hda_codec *codec,
1194 struct snd_pcm_substream *substream)
1195 {
1196 struct hdmi_spec *spec = codec->spec;
1197 struct snd_pcm_runtime *runtime = substream->runtime;
1198 int cvt_idx, pcm_idx;
1199 struct hdmi_spec_per_cvt *per_cvt = NULL;
1200 int err;
1201
1202 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1203 if (pcm_idx < 0)
1204 return -EINVAL;
1205
1206 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false);
1207 if (err)
1208 return err;
1209
1210 per_cvt = get_cvt(spec, cvt_idx);
1211 per_cvt->assigned = true;
1212 hinfo->nid = per_cvt->cvt_nid;
1213
1214 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1215
1216 set_bit(pcm_idx, &spec->pcm_in_use);
1217 /* todo: setup spdif ctls assign */
1218
1219 /* Initially set the converter's capabilities */
1220 hinfo->channels_min = per_cvt->channels_min;
1221 hinfo->channels_max = per_cvt->channels_max;
1222 hinfo->rates = per_cvt->rates;
1223 hinfo->formats = per_cvt->formats;
1224 hinfo->maxbps = per_cvt->maxbps;
1225
1226 /* Store the updated parameters */
1227 runtime->hw.channels_min = hinfo->channels_min;
1228 runtime->hw.channels_max = hinfo->channels_max;
1229 runtime->hw.formats = hinfo->formats;
1230 runtime->hw.rates = hinfo->rates;
1231
1232 snd_pcm_hw_constraint_step(substream->runtime, 0,
1233 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1234 return 0;
1235 }
1236
1237 /*
1238 * HDA PCM callbacks
1239 */
1240 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1241 struct hda_codec *codec,
1242 struct snd_pcm_substream *substream)
1243 {
1244 struct hdmi_spec *spec = codec->spec;
1245 struct snd_pcm_runtime *runtime = substream->runtime;
1246 int pin_idx, cvt_idx, pcm_idx;
1247 struct hdmi_spec_per_pin *per_pin;
1248 struct hdmi_eld *eld;
1249 struct hdmi_spec_per_cvt *per_cvt = NULL;
1250 int err;
1251
1252 /* Validate hinfo */
1253 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1254 if (pcm_idx < 0)
1255 return -EINVAL;
1256
1257 mutex_lock(&spec->pcm_lock);
1258 pin_idx = hinfo_to_pin_index(codec, hinfo);
1259 /* no pin is assigned to the PCM
1260 * PA need pcm open successfully when probe
1261 */
1262 if (pin_idx < 0) {
1263 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1264 goto unlock;
1265 }
1266
1267 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false);
1268 if (err < 0)
1269 goto unlock;
1270
1271 per_cvt = get_cvt(spec, cvt_idx);
1272 /* Claim converter */
1273 per_cvt->assigned = true;
1274
1275 set_bit(pcm_idx, &spec->pcm_in_use);
1276 per_pin = get_pin(spec, pin_idx);
1277 per_pin->cvt_nid = per_cvt->cvt_nid;
1278 hinfo->nid = per_cvt->cvt_nid;
1279
1280 /* flip stripe flag for the assigned stream if supported */
1281 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1282 azx_stream(get_azx_dev(substream))->stripe = 1;
1283
1284 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1285 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1286 AC_VERB_SET_CONNECT_SEL,
1287 per_pin->mux_idx);
1288
1289 /* configure unused pins to choose other converters */
1290 pin_cvt_fixup(codec, per_pin, 0);
1291
1292 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1293
1294 /* Initially set the converter's capabilities */
1295 hinfo->channels_min = per_cvt->channels_min;
1296 hinfo->channels_max = per_cvt->channels_max;
1297 hinfo->rates = per_cvt->rates;
1298 hinfo->formats = per_cvt->formats;
1299 hinfo->maxbps = per_cvt->maxbps;
1300
1301 eld = &per_pin->sink_eld;
1302 /* Restrict capabilities by ELD if this isn't disabled */
1303 if (!static_hdmi_pcm && eld->eld_valid) {
1304 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1305 if (hinfo->channels_min > hinfo->channels_max ||
1306 !hinfo->rates || !hinfo->formats) {
1307 per_cvt->assigned = false;
1308 hinfo->nid = 0;
1309 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1310 err = -ENODEV;
1311 goto unlock;
1312 }
1313 }
1314
1315 /* Store the updated parameters */
1316 runtime->hw.channels_min = hinfo->channels_min;
1317 runtime->hw.channels_max = hinfo->channels_max;
1318 runtime->hw.formats = hinfo->formats;
1319 runtime->hw.rates = hinfo->rates;
1320
1321 snd_pcm_hw_constraint_step(substream->runtime, 0,
1322 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1323 unlock:
1324 mutex_unlock(&spec->pcm_lock);
1325 return err;
1326 }
1327
1328 /*
1329 * HDA/HDMI auto parsing
1330 */
1331 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1332 {
1333 struct hdmi_spec *spec = codec->spec;
1334 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1335 hda_nid_t pin_nid = per_pin->pin_nid;
1336 int dev_id = per_pin->dev_id;
1337 int conns;
1338
1339 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1340 codec_warn(codec,
1341 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1342 pin_nid, get_wcaps(codec, pin_nid));
1343 return -EINVAL;
1344 }
1345
1346 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1347
1348 if (spec->intel_hsw_fixup) {
1349 conns = spec->num_cvts;
1350 memcpy(per_pin->mux_nids, spec->cvt_nids,
1351 sizeof(hda_nid_t) * conns);
1352 } else {
1353 conns = snd_hda_get_raw_connections(codec, pin_nid,
1354 per_pin->mux_nids,
1355 HDA_MAX_CONNECTIONS);
1356 }
1357
1358 /* all the device entries on the same pin have the same conn list */
1359 per_pin->num_mux_nids = conns;
1360
1361 return 0;
1362 }
1363
1364 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1365 struct hdmi_spec_per_pin *per_pin)
1366 {
1367 int i;
1368
1369 for (i = 0; i < spec->pcm_used; i++) {
1370 if (!test_bit(i, &spec->pcm_bitmap))
1371 return i;
1372 }
1373 return -EBUSY;
1374 }
1375
1376 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1377 struct hdmi_spec_per_pin *per_pin)
1378 {
1379 int idx;
1380
1381 /* pcm already be attached to the pin */
1382 if (per_pin->pcm)
1383 return;
1384 /* try the previously used slot at first */
1385 idx = per_pin->prev_pcm_idx;
1386 if (idx >= 0) {
1387 if (!test_bit(idx, &spec->pcm_bitmap))
1388 goto found;
1389 per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */
1390 }
1391 idx = hdmi_find_pcm_slot(spec, per_pin);
1392 if (idx == -EBUSY)
1393 return;
1394 found:
1395 per_pin->pcm_idx = idx;
1396 per_pin->pcm = get_hdmi_pcm(spec, idx);
1397 set_bit(idx, &spec->pcm_bitmap);
1398 }
1399
1400 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1401 struct hdmi_spec_per_pin *per_pin)
1402 {
1403 int idx;
1404
1405 /* pcm already be detached from the pin */
1406 if (!per_pin->pcm)
1407 return;
1408 idx = per_pin->pcm_idx;
1409 per_pin->pcm_idx = -1;
1410 per_pin->prev_pcm_idx = idx; /* remember the previous index */
1411 per_pin->pcm = NULL;
1412 if (idx >= 0 && idx < spec->pcm_used)
1413 clear_bit(idx, &spec->pcm_bitmap);
1414 }
1415
1416 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1417 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1418 {
1419 int mux_idx;
1420
1421 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1422 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1423 break;
1424 return mux_idx;
1425 }
1426
1427 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1428
1429 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1430 struct hdmi_spec_per_pin *per_pin)
1431 {
1432 struct hda_codec *codec = per_pin->codec;
1433 struct hda_pcm *pcm;
1434 struct hda_pcm_stream *hinfo;
1435 struct snd_pcm_substream *substream;
1436 int mux_idx;
1437 bool non_pcm;
1438
1439 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used)
1440 return;
1441 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1442 if (!pcm->pcm)
1443 return;
1444 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1445 return;
1446
1447 /* hdmi audio only uses playback and one substream */
1448 hinfo = pcm->stream;
1449 substream = pcm->pcm->streams[0].substream;
1450
1451 per_pin->cvt_nid = hinfo->nid;
1452
1453 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1454 if (mux_idx < per_pin->num_mux_nids) {
1455 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1456 per_pin->dev_id);
1457 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1458 AC_VERB_SET_CONNECT_SEL,
1459 mux_idx);
1460 }
1461 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1462
1463 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1464 if (substream->runtime)
1465 per_pin->channels = substream->runtime->channels;
1466 per_pin->setup = true;
1467 per_pin->mux_idx = mux_idx;
1468
1469 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1470 }
1471
1472 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1473 struct hdmi_spec_per_pin *per_pin)
1474 {
1475 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1476 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1477
1478 per_pin->chmap_set = false;
1479 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1480
1481 per_pin->setup = false;
1482 per_pin->channels = 0;
1483 }
1484
1485 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1486 struct hdmi_spec_per_pin *per_pin)
1487 {
1488 struct hdmi_spec *spec = codec->spec;
1489
1490 if (per_pin->pcm_idx >= 0)
1491 return spec->pcm_rec[per_pin->pcm_idx].jack;
1492 else
1493 return NULL;
1494 }
1495
1496 /* update per_pin ELD from the given new ELD;
1497 * setup info frame and notification accordingly
1498 * also notify ELD kctl and report jack status changes
1499 */
1500 static void update_eld(struct hda_codec *codec,
1501 struct hdmi_spec_per_pin *per_pin,
1502 struct hdmi_eld *eld,
1503 int repoll)
1504 {
1505 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1506 struct hdmi_spec *spec = codec->spec;
1507 struct snd_jack *pcm_jack;
1508 bool old_eld_valid = pin_eld->eld_valid;
1509 bool eld_changed;
1510 int pcm_idx;
1511
1512 if (eld->eld_valid) {
1513 if (eld->eld_size <= 0 ||
1514 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1515 eld->eld_size) < 0) {
1516 eld->eld_valid = false;
1517 if (repoll) {
1518 schedule_delayed_work(&per_pin->work,
1519 msecs_to_jiffies(300));
1520 return;
1521 }
1522 }
1523 }
1524
1525 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1526 eld->eld_valid = false;
1527 eld->eld_size = 0;
1528 }
1529
1530 /* for monitor disconnection, save pcm_idx firstly */
1531 pcm_idx = per_pin->pcm_idx;
1532
1533 /*
1534 * pcm_idx >=0 before update_eld() means it is in monitor
1535 * disconnected event. Jack must be fetched before update_eld().
1536 */
1537 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1538
1539 if (!spec->static_pcm_mapping) {
1540 if (eld->eld_valid) {
1541 hdmi_attach_hda_pcm(spec, per_pin);
1542 hdmi_pcm_setup_pin(spec, per_pin);
1543 } else {
1544 hdmi_pcm_reset_pin(spec, per_pin);
1545 hdmi_detach_hda_pcm(spec, per_pin);
1546 }
1547 }
1548
1549 /* if pcm_idx == -1, it means this is in monitor connection event
1550 * we can get the correct pcm_idx now.
1551 */
1552 if (pcm_idx == -1)
1553 pcm_idx = per_pin->pcm_idx;
1554 if (!pcm_jack)
1555 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1556
1557 if (eld->eld_valid)
1558 snd_hdmi_show_eld(codec, &eld->info);
1559
1560 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1561 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1562 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1563 if (pin_eld->eld_size != eld->eld_size ||
1564 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1565 eld->eld_size) != 0)
1566 eld_changed = true;
1567
1568 if (eld_changed) {
1569 pin_eld->monitor_present = eld->monitor_present;
1570 pin_eld->eld_valid = eld->eld_valid;
1571 pin_eld->eld_size = eld->eld_size;
1572 if (eld->eld_valid)
1573 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1574 eld->eld_size);
1575 pin_eld->info = eld->info;
1576 }
1577
1578 /*
1579 * Re-setup pin and infoframe. This is needed e.g. when
1580 * - sink is first plugged-in
1581 * - transcoder can change during stream playback on Haswell
1582 * and this can make HW reset converter selection on a pin.
1583 */
1584 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1585 pin_cvt_fixup(codec, per_pin, 0);
1586 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1587 }
1588
1589 if (eld_changed && pcm_idx >= 0)
1590 snd_ctl_notify(codec->card,
1591 SNDRV_CTL_EVENT_MASK_VALUE |
1592 SNDRV_CTL_EVENT_MASK_INFO,
1593 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1594
1595 if (eld_changed && pcm_jack)
1596 snd_jack_report(pcm_jack,
1597 (eld->monitor_present && eld->eld_valid) ?
1598 SND_JACK_AVOUT : 0);
1599 }
1600
1601 /* update ELD and jack state via HD-audio verbs */
1602 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1603 int repoll)
1604 {
1605 struct hda_codec *codec = per_pin->codec;
1606 struct hdmi_spec *spec = codec->spec;
1607 struct hdmi_eld *eld = &spec->temp_eld;
1608 struct device *dev = hda_codec_dev(codec);
1609 hda_nid_t pin_nid = per_pin->pin_nid;
1610 int dev_id = per_pin->dev_id;
1611 /*
1612 * Always execute a GetPinSense verb here, even when called from
1613 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1614 * response's PD bit is not the real PD value, but indicates that
1615 * the real PD value changed. An older version of the HD-audio
1616 * specification worked this way. Hence, we just ignore the data in
1617 * the unsolicited response to avoid custom WARs.
1618 */
1619 int present;
1620 int ret;
1621
1622 #ifdef CONFIG_PM
1623 if (dev->power.runtime_status == RPM_SUSPENDING)
1624 return;
1625 #endif
1626
1627 ret = snd_hda_power_up_pm(codec);
1628 if (ret < 0 && pm_runtime_suspended(dev))
1629 goto out;
1630
1631 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1632
1633 mutex_lock(&per_pin->lock);
1634 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1635 if (eld->monitor_present)
1636 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1637 else
1638 eld->eld_valid = false;
1639
1640 codec_dbg(codec,
1641 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1642 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1643
1644 if (eld->eld_valid) {
1645 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1646 eld->eld_buffer, &eld->eld_size) < 0)
1647 eld->eld_valid = false;
1648 }
1649
1650 update_eld(codec, per_pin, eld, repoll);
1651 mutex_unlock(&per_pin->lock);
1652 out:
1653 snd_hda_power_down_pm(codec);
1654 }
1655
1656 #define I915_SILENT_RATE 48000
1657 #define I915_SILENT_CHANNELS 2
1658 #define I915_SILENT_FORMAT_BITS 16
1659 #define I915_SILENT_FMT_MASK 0xf
1660
1661 static void silent_stream_enable_i915(struct hda_codec *codec,
1662 struct hdmi_spec_per_pin *per_pin)
1663 {
1664 unsigned int format;
1665
1666 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1667 per_pin->dev_id, I915_SILENT_RATE);
1668
1669 /* trigger silent stream generation in hw */
1670 format = snd_hdac_stream_format(I915_SILENT_CHANNELS, I915_SILENT_FORMAT_BITS,
1671 I915_SILENT_RATE);
1672 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1673 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1674 usleep_range(100, 200);
1675 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1676
1677 per_pin->channels = I915_SILENT_CHANNELS;
1678 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1679 }
1680
1681 static void silent_stream_set_kae(struct hda_codec *codec,
1682 struct hdmi_spec_per_pin *per_pin,
1683 bool enable)
1684 {
1685 unsigned int param;
1686
1687 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
1688
1689 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
1690 param = (param >> 16) & 0xff;
1691
1692 if (enable)
1693 param |= AC_DIG3_KAE;
1694 else
1695 param &= ~AC_DIG3_KAE;
1696
1697 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
1698 }
1699
1700 static void silent_stream_enable(struct hda_codec *codec,
1701 struct hdmi_spec_per_pin *per_pin)
1702 {
1703 struct hdmi_spec *spec = codec->spec;
1704 struct hdmi_spec_per_cvt *per_cvt;
1705 int cvt_idx, pin_idx, err;
1706 int keep_power = 0;
1707
1708 /*
1709 * Power-up will call hdmi_present_sense, so the PM calls
1710 * have to be done without mutex held.
1711 */
1712
1713 err = snd_hda_power_up_pm(codec);
1714 if (err < 0 && err != -EACCES) {
1715 codec_err(codec,
1716 "Failed to power up codec for silent stream enable ret=[%d]\n", err);
1717 snd_hda_power_down_pm(codec);
1718 return;
1719 }
1720
1721 mutex_lock(&per_pin->lock);
1722
1723 if (per_pin->setup) {
1724 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1725 err = -EBUSY;
1726 goto unlock_out;
1727 }
1728
1729 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1730 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true);
1731 if (err) {
1732 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1733 goto unlock_out;
1734 }
1735
1736 per_cvt = get_cvt(spec, cvt_idx);
1737 per_cvt->silent_stream = true;
1738 per_pin->cvt_nid = per_cvt->cvt_nid;
1739 per_pin->silent_stream = true;
1740
1741 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1742 per_pin->pin_nid, per_cvt->cvt_nid);
1743
1744 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1745 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1746 AC_VERB_SET_CONNECT_SEL,
1747 per_pin->mux_idx);
1748
1749 /* configure unused pins to choose other converters */
1750 pin_cvt_fixup(codec, per_pin, 0);
1751
1752 switch (spec->silent_stream_type) {
1753 case SILENT_STREAM_KAE:
1754 silent_stream_enable_i915(codec, per_pin);
1755 silent_stream_set_kae(codec, per_pin, true);
1756 break;
1757 case SILENT_STREAM_I915:
1758 silent_stream_enable_i915(codec, per_pin);
1759 keep_power = 1;
1760 break;
1761 default:
1762 break;
1763 }
1764
1765 unlock_out:
1766 mutex_unlock(&per_pin->lock);
1767
1768 if (err || !keep_power)
1769 snd_hda_power_down_pm(codec);
1770 }
1771
1772 static void silent_stream_disable(struct hda_codec *codec,
1773 struct hdmi_spec_per_pin *per_pin)
1774 {
1775 struct hdmi_spec *spec = codec->spec;
1776 struct hdmi_spec_per_cvt *per_cvt;
1777 int cvt_idx, err;
1778
1779 err = snd_hda_power_up_pm(codec);
1780 if (err < 0 && err != -EACCES) {
1781 codec_err(codec,
1782 "Failed to power up codec for silent stream disable ret=[%d]\n",
1783 err);
1784 snd_hda_power_down_pm(codec);
1785 return;
1786 }
1787
1788 mutex_lock(&per_pin->lock);
1789 if (!per_pin->silent_stream)
1790 goto unlock_out;
1791
1792 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1793 per_pin->pin_nid, per_pin->cvt_nid);
1794
1795 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1796 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1797 per_cvt = get_cvt(spec, cvt_idx);
1798 per_cvt->silent_stream = false;
1799 }
1800
1801 if (spec->silent_stream_type == SILENT_STREAM_I915) {
1802 /* release ref taken in silent_stream_enable() */
1803 snd_hda_power_down_pm(codec);
1804 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
1805 silent_stream_set_kae(codec, per_pin, false);
1806 }
1807
1808 per_pin->cvt_nid = 0;
1809 per_pin->silent_stream = false;
1810
1811 unlock_out:
1812 mutex_unlock(&per_pin->lock);
1813
1814 snd_hda_power_down_pm(codec);
1815 }
1816
1817 /* update ELD and jack state via audio component */
1818 static void sync_eld_via_acomp(struct hda_codec *codec,
1819 struct hdmi_spec_per_pin *per_pin)
1820 {
1821 struct hdmi_spec *spec = codec->spec;
1822 struct hdmi_eld *eld = &spec->temp_eld;
1823 bool monitor_prev, monitor_next;
1824
1825 mutex_lock(&per_pin->lock);
1826 eld->monitor_present = false;
1827 monitor_prev = per_pin->sink_eld.monitor_present;
1828 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1829 per_pin->dev_id, &eld->monitor_present,
1830 eld->eld_buffer, ELD_MAX_SIZE);
1831 eld->eld_valid = (eld->eld_size > 0);
1832 update_eld(codec, per_pin, eld, 0);
1833 monitor_next = per_pin->sink_eld.monitor_present;
1834 mutex_unlock(&per_pin->lock);
1835
1836 if (spec->silent_stream_type) {
1837 if (!monitor_prev && monitor_next)
1838 silent_stream_enable(codec, per_pin);
1839 else if (monitor_prev && !monitor_next)
1840 silent_stream_disable(codec, per_pin);
1841 }
1842 }
1843
1844 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1845 {
1846 struct hda_codec *codec = per_pin->codec;
1847
1848 if (!codec_has_acomp(codec))
1849 hdmi_present_sense_via_verbs(per_pin, repoll);
1850 else
1851 sync_eld_via_acomp(codec, per_pin);
1852 }
1853
1854 static void hdmi_repoll_eld(struct work_struct *work)
1855 {
1856 struct hdmi_spec_per_pin *per_pin =
1857 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1858 struct hda_codec *codec = per_pin->codec;
1859 struct hdmi_spec *spec = codec->spec;
1860 struct hda_jack_tbl *jack;
1861
1862 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1863 per_pin->dev_id);
1864 if (jack)
1865 jack->jack_dirty = 1;
1866
1867 if (per_pin->repoll_count++ > 6)
1868 per_pin->repoll_count = 0;
1869
1870 mutex_lock(&spec->pcm_lock);
1871 hdmi_present_sense(per_pin, per_pin->repoll_count);
1872 mutex_unlock(&spec->pcm_lock);
1873 }
1874
1875 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1876 {
1877 struct hdmi_spec *spec = codec->spec;
1878 unsigned int caps, config;
1879 int pin_idx;
1880 struct hdmi_spec_per_pin *per_pin;
1881 int err;
1882 int dev_num, i;
1883
1884 caps = snd_hda_query_pin_caps(codec, pin_nid);
1885 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1886 return 0;
1887
1888 /*
1889 * For DP MST audio, Configuration Default is the same for
1890 * all device entries on the same pin
1891 */
1892 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1893 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1894 !spec->force_connect)
1895 return 0;
1896
1897 /*
1898 * To simplify the implementation, malloc all
1899 * the virtual pins in the initialization statically
1900 */
1901 if (spec->intel_hsw_fixup) {
1902 /*
1903 * On Intel platforms, device entries count returned
1904 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1905 * the type of receiver that is connected. Allocate pin
1906 * structures based on worst case.
1907 */
1908 dev_num = spec->dev_num;
1909 } else if (codec->dp_mst) {
1910 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1911 /*
1912 * spec->dev_num is the maxinum number of device entries
1913 * among all the pins
1914 */
1915 spec->dev_num = (spec->dev_num > dev_num) ?
1916 spec->dev_num : dev_num;
1917 } else {
1918 /*
1919 * If the platform doesn't support DP MST,
1920 * manually set dev_num to 1. This means
1921 * the pin has only one device entry.
1922 */
1923 dev_num = 1;
1924 spec->dev_num = 1;
1925 }
1926
1927 for (i = 0; i < dev_num; i++) {
1928 pin_idx = spec->num_pins;
1929 per_pin = snd_array_new(&spec->pins);
1930
1931 if (!per_pin)
1932 return -ENOMEM;
1933
1934 per_pin->pcm = NULL;
1935 per_pin->pcm_idx = -1;
1936 per_pin->prev_pcm_idx = -1;
1937 per_pin->pin_nid = pin_nid;
1938 per_pin->pin_nid_idx = spec->num_nids;
1939 per_pin->dev_id = i;
1940 per_pin->non_pcm = false;
1941 snd_hda_set_dev_select(codec, pin_nid, i);
1942 err = hdmi_read_pin_conn(codec, pin_idx);
1943 if (err < 0)
1944 return err;
1945 if (!is_jack_detectable(codec, pin_nid))
1946 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid);
1947 spec->num_pins++;
1948 }
1949 spec->num_nids++;
1950
1951 return 0;
1952 }
1953
1954 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1955 {
1956 struct hdmi_spec *spec = codec->spec;
1957 struct hdmi_spec_per_cvt *per_cvt;
1958 unsigned int chans;
1959 int err;
1960
1961 chans = get_wcaps(codec, cvt_nid);
1962 chans = get_wcaps_channels(chans);
1963
1964 per_cvt = snd_array_new(&spec->cvts);
1965 if (!per_cvt)
1966 return -ENOMEM;
1967
1968 per_cvt->cvt_nid = cvt_nid;
1969 per_cvt->channels_min = 2;
1970 if (chans <= 16) {
1971 per_cvt->channels_max = chans;
1972 if (chans > spec->chmap.channels_max)
1973 spec->chmap.channels_max = chans;
1974 }
1975
1976 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1977 &per_cvt->rates,
1978 &per_cvt->formats,
1979 NULL,
1980 &per_cvt->maxbps);
1981 if (err < 0)
1982 return err;
1983
1984 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1985 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1986 spec->num_cvts++;
1987
1988 return 0;
1989 }
1990
1991 static const struct snd_pci_quirk force_connect_list[] = {
1992 SND_PCI_QUIRK(0x103c, 0x83e2, "HP EliteDesk 800 G4", 1),
1993 SND_PCI_QUIRK(0x103c, 0x83ef, "HP MP9 G4 Retail System AMS", 1),
1994 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1995 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1996 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1997 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
1998 SND_PCI_QUIRK(0x1043, 0x86ae, "ASUS", 1), /* Z170 PRO */
1999 SND_PCI_QUIRK(0x1043, 0x86c7, "ASUS", 1), /* Z170M PLUS */
2000 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
2001 SND_PCI_QUIRK(0x8086, 0x2060, "Intel NUC5CPYB", 1),
2002 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
2003 {}
2004 };
2005
2006 static int hdmi_parse_codec(struct hda_codec *codec)
2007 {
2008 struct hdmi_spec *spec = codec->spec;
2009 hda_nid_t start_nid;
2010 unsigned int caps;
2011 int i, nodes;
2012 const struct snd_pci_quirk *q;
2013
2014 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
2015 if (!start_nid || nodes < 0) {
2016 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2017 return -EINVAL;
2018 }
2019
2020 if (enable_all_pins)
2021 spec->force_connect = true;
2022
2023 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
2024
2025 if (q && q->value)
2026 spec->force_connect = true;
2027
2028 /*
2029 * hdmi_add_pin() assumes total amount of converters to
2030 * be known, so first discover all converters
2031 */
2032 for (i = 0; i < nodes; i++) {
2033 hda_nid_t nid = start_nid + i;
2034
2035 caps = get_wcaps(codec, nid);
2036
2037 if (!(caps & AC_WCAP_DIGITAL))
2038 continue;
2039
2040 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2041 hdmi_add_cvt(codec, nid);
2042 }
2043
2044 /* discover audio pins */
2045 for (i = 0; i < nodes; i++) {
2046 hda_nid_t nid = start_nid + i;
2047
2048 caps = get_wcaps(codec, nid);
2049
2050 if (!(caps & AC_WCAP_DIGITAL))
2051 continue;
2052
2053 if (get_wcaps_type(caps) == AC_WID_PIN)
2054 hdmi_add_pin(codec, nid);
2055 }
2056
2057 return 0;
2058 }
2059
2060 /*
2061 */
2062 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2063 {
2064 struct hda_spdif_out *spdif;
2065 bool non_pcm;
2066
2067 mutex_lock(&codec->spdif_mutex);
2068 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2069 /* Add sanity check to pass klockwork check.
2070 * This should never happen.
2071 */
2072 if (WARN_ON(spdif == NULL)) {
2073 mutex_unlock(&codec->spdif_mutex);
2074 return true;
2075 }
2076 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2077 mutex_unlock(&codec->spdif_mutex);
2078 return non_pcm;
2079 }
2080
2081 /*
2082 * HDMI callbacks
2083 */
2084
2085 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2086 struct hda_codec *codec,
2087 unsigned int stream_tag,
2088 unsigned int format,
2089 struct snd_pcm_substream *substream)
2090 {
2091 hda_nid_t cvt_nid = hinfo->nid;
2092 struct hdmi_spec *spec = codec->spec;
2093 int pin_idx;
2094 struct hdmi_spec_per_pin *per_pin;
2095 struct snd_pcm_runtime *runtime = substream->runtime;
2096 bool non_pcm;
2097 int pinctl, stripe;
2098 int err = 0;
2099
2100 mutex_lock(&spec->pcm_lock);
2101 pin_idx = hinfo_to_pin_index(codec, hinfo);
2102 if (pin_idx < 0) {
2103 /* when pcm is not bound to a pin skip pin setup and return 0
2104 * to make audio playback be ongoing
2105 */
2106 pin_cvt_fixup(codec, NULL, cvt_nid);
2107 snd_hda_codec_setup_stream(codec, cvt_nid,
2108 stream_tag, 0, format);
2109 goto unlock;
2110 }
2111
2112 per_pin = get_pin(spec, pin_idx);
2113
2114 /* Verify pin:cvt selections to avoid silent audio after S3.
2115 * After S3, the audio driver restores pin:cvt selections
2116 * but this can happen before gfx is ready and such selection
2117 * is overlooked by HW. Thus multiple pins can share a same
2118 * default convertor and mute control will affect each other,
2119 * which can cause a resumed audio playback become silent
2120 * after S3.
2121 */
2122 pin_cvt_fixup(codec, per_pin, 0);
2123
2124 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2125 /* Todo: add DP1.2 MST audio support later */
2126 if (codec_has_acomp(codec))
2127 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2128 per_pin->dev_id, runtime->rate);
2129
2130 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2131 mutex_lock(&per_pin->lock);
2132 per_pin->channels = substream->runtime->channels;
2133 per_pin->setup = true;
2134
2135 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2136 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2137 substream);
2138 snd_hda_codec_write(codec, cvt_nid, 0,
2139 AC_VERB_SET_STRIPE_CONTROL,
2140 stripe);
2141 }
2142
2143 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2144 mutex_unlock(&per_pin->lock);
2145 if (spec->dyn_pin_out) {
2146 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2147 per_pin->dev_id);
2148 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2149 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2150 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2151 AC_VERB_SET_PIN_WIDGET_CONTROL,
2152 pinctl | PIN_OUT);
2153 }
2154
2155 /* snd_hda_set_dev_select() has been called before */
2156 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2157 per_pin->dev_id, stream_tag, format);
2158 unlock:
2159 mutex_unlock(&spec->pcm_lock);
2160 return err;
2161 }
2162
2163 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2164 struct hda_codec *codec,
2165 struct snd_pcm_substream *substream)
2166 {
2167 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2168 return 0;
2169 }
2170
2171 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2172 struct hda_codec *codec,
2173 struct snd_pcm_substream *substream)
2174 {
2175 struct hdmi_spec *spec = codec->spec;
2176 int cvt_idx, pin_idx, pcm_idx;
2177 struct hdmi_spec_per_cvt *per_cvt;
2178 struct hdmi_spec_per_pin *per_pin;
2179 int pinctl;
2180 int err = 0;
2181
2182 mutex_lock(&spec->pcm_lock);
2183 if (hinfo->nid) {
2184 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2185 if (snd_BUG_ON(pcm_idx < 0)) {
2186 err = -EINVAL;
2187 goto unlock;
2188 }
2189 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2190 if (snd_BUG_ON(cvt_idx < 0)) {
2191 err = -EINVAL;
2192 goto unlock;
2193 }
2194 per_cvt = get_cvt(spec, cvt_idx);
2195 per_cvt->assigned = false;
2196 hinfo->nid = 0;
2197
2198 azx_stream(get_azx_dev(substream))->stripe = 0;
2199
2200 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2201 clear_bit(pcm_idx, &spec->pcm_in_use);
2202 pin_idx = hinfo_to_pin_index(codec, hinfo);
2203 /*
2204 * In such a case, return 0 to match the behavior in
2205 * hdmi_pcm_open()
2206 */
2207 if (pin_idx < 0)
2208 goto unlock;
2209
2210 per_pin = get_pin(spec, pin_idx);
2211
2212 if (spec->dyn_pin_out) {
2213 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2214 per_pin->dev_id);
2215 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2216 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2217 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2218 AC_VERB_SET_PIN_WIDGET_CONTROL,
2219 pinctl & ~PIN_OUT);
2220 }
2221
2222 mutex_lock(&per_pin->lock);
2223 per_pin->chmap_set = false;
2224 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2225
2226 per_pin->setup = false;
2227 per_pin->channels = 0;
2228 mutex_unlock(&per_pin->lock);
2229 }
2230
2231 unlock:
2232 mutex_unlock(&spec->pcm_lock);
2233
2234 return err;
2235 }
2236
2237 static const struct hda_pcm_ops generic_ops = {
2238 .open = hdmi_pcm_open,
2239 .close = hdmi_pcm_close,
2240 .prepare = generic_hdmi_playback_pcm_prepare,
2241 .cleanup = generic_hdmi_playback_pcm_cleanup,
2242 };
2243
2244 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2245 {
2246 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2247 struct hdmi_spec *spec = codec->spec;
2248 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2249
2250 if (!per_pin)
2251 return 0;
2252
2253 return per_pin->sink_eld.info.spk_alloc;
2254 }
2255
2256 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2257 unsigned char *chmap)
2258 {
2259 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2260 struct hdmi_spec *spec = codec->spec;
2261 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2262
2263 /* chmap is already set to 0 in caller */
2264 if (!per_pin)
2265 return;
2266
2267 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2268 }
2269
2270 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2271 unsigned char *chmap, int prepared)
2272 {
2273 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2274 struct hdmi_spec *spec = codec->spec;
2275 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2276
2277 if (!per_pin)
2278 return;
2279 mutex_lock(&per_pin->lock);
2280 per_pin->chmap_set = true;
2281 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2282 if (prepared)
2283 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2284 mutex_unlock(&per_pin->lock);
2285 }
2286
2287 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2288 {
2289 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2290 struct hdmi_spec *spec = codec->spec;
2291 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2292
2293 return per_pin ? true:false;
2294 }
2295
2296 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2297 {
2298 struct hdmi_spec *spec = codec->spec;
2299 int idx, pcm_num;
2300
2301 /* limit the PCM devices to the codec converters or available PINs */
2302 pcm_num = min(spec->num_cvts, spec->num_pins);
2303 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2304
2305 for (idx = 0; idx < pcm_num; idx++) {
2306 struct hdmi_spec_per_cvt *per_cvt;
2307 struct hda_pcm *info;
2308 struct hda_pcm_stream *pstr;
2309
2310 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2311 if (!info)
2312 return -ENOMEM;
2313
2314 spec->pcm_rec[idx].pcm = info;
2315 spec->pcm_used++;
2316 info->pcm_type = HDA_PCM_TYPE_HDMI;
2317 info->own_chmap = true;
2318
2319 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2320 pstr->substreams = 1;
2321 pstr->ops = generic_ops;
2322
2323 per_cvt = get_cvt(spec, 0);
2324 pstr->channels_min = per_cvt->channels_min;
2325 pstr->channels_max = per_cvt->channels_max;
2326
2327 /* pcm number is less than pcm_rec array size */
2328 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec))
2329 break;
2330 /* other pstr fields are set in open */
2331 }
2332
2333 return 0;
2334 }
2335
2336 static void free_hdmi_jack_priv(struct snd_jack *jack)
2337 {
2338 struct hdmi_pcm *pcm = jack->private_data;
2339
2340 pcm->jack = NULL;
2341 }
2342
2343 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2344 {
2345 char hdmi_str[32] = "HDMI/DP";
2346 struct hdmi_spec *spec = codec->spec;
2347 struct snd_jack *jack;
2348 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2349 int err;
2350
2351 if (pcmdev > 0)
2352 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2353
2354 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2355 true, false);
2356 if (err < 0)
2357 return err;
2358
2359 spec->pcm_rec[pcm_idx].jack = jack;
2360 jack->private_data = &spec->pcm_rec[pcm_idx];
2361 jack->private_free = free_hdmi_jack_priv;
2362 return 0;
2363 }
2364
2365 static int generic_hdmi_build_controls(struct hda_codec *codec)
2366 {
2367 struct hdmi_spec *spec = codec->spec;
2368 int dev, err;
2369 int pin_idx, pcm_idx;
2370
2371 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2372 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2373 /* no PCM: mark this for skipping permanently */
2374 set_bit(pcm_idx, &spec->pcm_bitmap);
2375 continue;
2376 }
2377
2378 err = generic_hdmi_build_jack(codec, pcm_idx);
2379 if (err < 0)
2380 return err;
2381
2382 /* create the spdif for each pcm
2383 * pin will be bound when monitor is connected
2384 */
2385 err = snd_hda_create_dig_out_ctls(codec,
2386 0, spec->cvt_nids[0],
2387 HDA_PCM_TYPE_HDMI);
2388 if (err < 0)
2389 return err;
2390 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2391
2392 dev = get_pcm_rec(spec, pcm_idx)->device;
2393 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2394 /* add control for ELD Bytes */
2395 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2396 if (err < 0)
2397 return err;
2398 }
2399 }
2400
2401 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2402 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2403 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2404
2405 if (spec->static_pcm_mapping) {
2406 hdmi_attach_hda_pcm(spec, per_pin);
2407 hdmi_pcm_setup_pin(spec, per_pin);
2408 }
2409
2410 pin_eld->eld_valid = false;
2411 hdmi_present_sense(per_pin, 0);
2412 }
2413
2414 /* add channel maps */
2415 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2416 struct hda_pcm *pcm;
2417
2418 pcm = get_pcm_rec(spec, pcm_idx);
2419 if (!pcm || !pcm->pcm)
2420 break;
2421 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2422 if (err < 0)
2423 return err;
2424 }
2425
2426 return 0;
2427 }
2428
2429 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2430 {
2431 struct hdmi_spec *spec = codec->spec;
2432 int pin_idx;
2433
2434 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2435 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2436
2437 per_pin->codec = codec;
2438 mutex_init(&per_pin->lock);
2439 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2440 eld_proc_new(per_pin, pin_idx);
2441 }
2442 return 0;
2443 }
2444
2445 static int generic_hdmi_init(struct hda_codec *codec)
2446 {
2447 struct hdmi_spec *spec = codec->spec;
2448 int pin_idx;
2449
2450 mutex_lock(&spec->bind_lock);
2451 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2452 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2453 hda_nid_t pin_nid = per_pin->pin_nid;
2454 int dev_id = per_pin->dev_id;
2455
2456 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2457 hdmi_init_pin(codec, pin_nid);
2458 if (codec_has_acomp(codec))
2459 continue;
2460 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2461 jack_callback);
2462 }
2463 mutex_unlock(&spec->bind_lock);
2464 return 0;
2465 }
2466
2467 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2468 {
2469 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2470 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2471 }
2472
2473 static void hdmi_array_free(struct hdmi_spec *spec)
2474 {
2475 snd_array_free(&spec->pins);
2476 snd_array_free(&spec->cvts);
2477 }
2478
2479 static void generic_spec_free(struct hda_codec *codec)
2480 {
2481 struct hdmi_spec *spec = codec->spec;
2482
2483 if (spec) {
2484 hdmi_array_free(spec);
2485 kfree(spec);
2486 codec->spec = NULL;
2487 }
2488 codec->dp_mst = false;
2489 }
2490
2491 static void generic_hdmi_free(struct hda_codec *codec)
2492 {
2493 struct hdmi_spec *spec = codec->spec;
2494 int pin_idx, pcm_idx;
2495
2496 if (spec->acomp_registered) {
2497 snd_hdac_acomp_exit(&codec->bus->core);
2498 } else if (codec_has_acomp(codec)) {
2499 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2500 }
2501 codec->relaxed_resume = 0;
2502
2503 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2504 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2505 cancel_delayed_work_sync(&per_pin->work);
2506 eld_proc_free(per_pin);
2507 }
2508
2509 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2510 if (spec->pcm_rec[pcm_idx].jack == NULL)
2511 continue;
2512 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack);
2513 }
2514
2515 generic_spec_free(codec);
2516 }
2517
2518 static int generic_hdmi_suspend(struct hda_codec *codec)
2519 {
2520 struct hdmi_spec *spec = codec->spec;
2521 int pin_idx;
2522
2523 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2524 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2525 cancel_delayed_work_sync(&per_pin->work);
2526 }
2527 return 0;
2528 }
2529
2530 static int generic_hdmi_resume(struct hda_codec *codec)
2531 {
2532 struct hdmi_spec *spec = codec->spec;
2533 int pin_idx;
2534
2535 codec->patch_ops.init(codec);
2536 snd_hda_regmap_sync(codec);
2537
2538 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2539 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2540 hdmi_present_sense(per_pin, 1);
2541 }
2542 return 0;
2543 }
2544
2545 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2546 .init = generic_hdmi_init,
2547 .free = generic_hdmi_free,
2548 .build_pcms = generic_hdmi_build_pcms,
2549 .build_controls = generic_hdmi_build_controls,
2550 .unsol_event = hdmi_unsol_event,
2551 .suspend = generic_hdmi_suspend,
2552 .resume = generic_hdmi_resume,
2553 };
2554
2555 static const struct hdmi_ops generic_standard_hdmi_ops = {
2556 .pin_get_eld = hdmi_pin_get_eld,
2557 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2558 .pin_hbr_setup = hdmi_pin_hbr_setup,
2559 .setup_stream = hdmi_setup_stream,
2560 };
2561
2562 /* allocate codec->spec and assign/initialize generic parser ops */
2563 static int alloc_generic_hdmi(struct hda_codec *codec)
2564 {
2565 struct hdmi_spec *spec;
2566
2567 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2568 if (!spec)
2569 return -ENOMEM;
2570
2571 spec->codec = codec;
2572 spec->ops = generic_standard_hdmi_ops;
2573 spec->dev_num = 1; /* initialize to 1 */
2574 mutex_init(&spec->pcm_lock);
2575 mutex_init(&spec->bind_lock);
2576 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2577
2578 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2579 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2580 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2581 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2582
2583 codec->spec = spec;
2584 hdmi_array_init(spec, 4);
2585
2586 codec->patch_ops = generic_hdmi_patch_ops;
2587
2588 return 0;
2589 }
2590
2591 /* generic HDMI parser */
2592 static int patch_generic_hdmi(struct hda_codec *codec)
2593 {
2594 int err;
2595
2596 err = alloc_generic_hdmi(codec);
2597 if (err < 0)
2598 return err;
2599
2600 err = hdmi_parse_codec(codec);
2601 if (err < 0) {
2602 generic_spec_free(codec);
2603 return err;
2604 }
2605
2606 generic_hdmi_init_per_pins(codec);
2607 return 0;
2608 }
2609
2610 /*
2611 * generic audio component binding
2612 */
2613
2614 /* turn on / off the unsol event jack detection dynamically */
2615 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2616 int dev_id, bool use_acomp)
2617 {
2618 struct hda_jack_tbl *tbl;
2619
2620 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2621 if (tbl) {
2622 /* clear unsol even if component notifier is used, or re-enable
2623 * if notifier is cleared
2624 */
2625 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2626 snd_hda_codec_write_cache(codec, nid, 0,
2627 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2628 }
2629 }
2630
2631 /* set up / clear component notifier dynamically */
2632 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2633 bool use_acomp)
2634 {
2635 struct hdmi_spec *spec;
2636 int i;
2637
2638 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2639 mutex_lock(&spec->bind_lock);
2640 spec->use_acomp_notifier = use_acomp;
2641 spec->codec->relaxed_resume = use_acomp;
2642 spec->codec->bus->keep_power = 0;
2643 /* reprogram each jack detection logic depending on the notifier */
2644 for (i = 0; i < spec->num_pins; i++)
2645 reprogram_jack_detect(spec->codec,
2646 get_pin(spec, i)->pin_nid,
2647 get_pin(spec, i)->dev_id,
2648 use_acomp);
2649 mutex_unlock(&spec->bind_lock);
2650 }
2651
2652 /* enable / disable the notifier via master bind / unbind */
2653 static int generic_acomp_master_bind(struct device *dev,
2654 struct drm_audio_component *acomp)
2655 {
2656 generic_acomp_notifier_set(acomp, true);
2657 return 0;
2658 }
2659
2660 static void generic_acomp_master_unbind(struct device *dev,
2661 struct drm_audio_component *acomp)
2662 {
2663 generic_acomp_notifier_set(acomp, false);
2664 }
2665
2666 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2667 static int match_bound_vga(struct device *dev, int subtype, void *data)
2668 {
2669 struct hdac_bus *bus = data;
2670 struct pci_dev *pci, *master;
2671
2672 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2673 return 0;
2674 master = to_pci_dev(bus->dev);
2675 pci = to_pci_dev(dev);
2676 return master->bus == pci->bus;
2677 }
2678
2679 /* audio component notifier for AMD/Nvidia HDMI codecs */
2680 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2681 {
2682 struct hda_codec *codec = audio_ptr;
2683 struct hdmi_spec *spec = codec->spec;
2684 hda_nid_t pin_nid = spec->port2pin(codec, port);
2685
2686 if (!pin_nid)
2687 return;
2688 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2689 return;
2690 /* skip notification during system suspend (but not in runtime PM);
2691 * the state will be updated at resume
2692 */
2693 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2694 return;
2695
2696 check_presence_and_report(codec, pin_nid, dev_id);
2697 }
2698
2699 /* set up the private drm_audio_ops from the template */
2700 static void setup_drm_audio_ops(struct hda_codec *codec,
2701 const struct drm_audio_component_audio_ops *ops)
2702 {
2703 struct hdmi_spec *spec = codec->spec;
2704
2705 spec->drm_audio_ops.audio_ptr = codec;
2706 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2707 * will call pin_eld_notify with using audio_ptr pointer
2708 * We need make sure audio_ptr is really setup
2709 */
2710 wmb();
2711 spec->drm_audio_ops.pin2port = ops->pin2port;
2712 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2713 spec->drm_audio_ops.master_bind = ops->master_bind;
2714 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2715 }
2716
2717 /* initialize the generic HDMI audio component */
2718 static void generic_acomp_init(struct hda_codec *codec,
2719 const struct drm_audio_component_audio_ops *ops,
2720 int (*port2pin)(struct hda_codec *, int))
2721 {
2722 struct hdmi_spec *spec = codec->spec;
2723
2724 if (!enable_acomp) {
2725 codec_info(codec, "audio component disabled by module option\n");
2726 return;
2727 }
2728
2729 spec->port2pin = port2pin;
2730 setup_drm_audio_ops(codec, ops);
2731 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2732 match_bound_vga, 0)) {
2733 spec->acomp_registered = true;
2734 }
2735 }
2736
2737 /*
2738 * Intel codec parsers and helpers
2739 */
2740
2741 #define INTEL_GET_VENDOR_VERB 0xf81
2742 #define INTEL_SET_VENDOR_VERB 0x781
2743 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2744 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2745
2746 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2747 bool update_tree)
2748 {
2749 unsigned int vendor_param;
2750 struct hdmi_spec *spec = codec->spec;
2751
2752 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2753 INTEL_GET_VENDOR_VERB, 0);
2754 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2755 return;
2756
2757 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2758 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2759 INTEL_SET_VENDOR_VERB, vendor_param);
2760 if (vendor_param == -1)
2761 return;
2762
2763 if (update_tree)
2764 snd_hda_codec_update_widgets(codec);
2765 }
2766
2767 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2768 {
2769 unsigned int vendor_param;
2770 struct hdmi_spec *spec = codec->spec;
2771
2772 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2773 INTEL_GET_VENDOR_VERB, 0);
2774 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2775 return;
2776
2777 /* enable DP1.2 mode */
2778 vendor_param |= INTEL_EN_DP12;
2779 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2780 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2781 INTEL_SET_VENDOR_VERB, vendor_param);
2782 }
2783
2784 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2785 * Otherwise you may get severe h/w communication errors.
2786 */
2787 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2788 unsigned int power_state)
2789 {
2790 if (power_state == AC_PWRST_D0) {
2791 intel_haswell_enable_all_pins(codec, false);
2792 intel_haswell_fixup_enable_dp12(codec);
2793 }
2794
2795 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2796 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2797 }
2798
2799 /* There is a fixed mapping between audio pin node and display port.
2800 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2801 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2802 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2803 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2804 *
2805 * on VLV, ILK:
2806 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2807 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2808 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2809 */
2810 static int intel_base_nid(struct hda_codec *codec)
2811 {
2812 switch (codec->core.vendor_id) {
2813 case 0x80860054: /* ILK */
2814 case 0x80862804: /* ILK */
2815 case 0x80862882: /* VLV */
2816 return 4;
2817 default:
2818 return 5;
2819 }
2820 }
2821
2822 static int intel_pin2port(void *audio_ptr, int pin_nid)
2823 {
2824 struct hda_codec *codec = audio_ptr;
2825 struct hdmi_spec *spec = codec->spec;
2826 int base_nid, i;
2827
2828 if (!spec->port_num) {
2829 base_nid = intel_base_nid(codec);
2830 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2831 return -1;
2832 return pin_nid - base_nid + 1;
2833 }
2834
2835 /*
2836 * looking for the pin number in the mapping table and return
2837 * the index which indicate the port number
2838 */
2839 for (i = 0; i < spec->port_num; i++) {
2840 if (pin_nid == spec->port_map[i])
2841 return i;
2842 }
2843
2844 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2845 return -1;
2846 }
2847
2848 static int intel_port2pin(struct hda_codec *codec, int port)
2849 {
2850 struct hdmi_spec *spec = codec->spec;
2851
2852 if (!spec->port_num) {
2853 /* we assume only from port-B to port-D */
2854 if (port < 1 || port > 3)
2855 return 0;
2856 return port + intel_base_nid(codec) - 1;
2857 }
2858
2859 if (port < 0 || port >= spec->port_num)
2860 return 0;
2861 return spec->port_map[port];
2862 }
2863
2864 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2865 {
2866 struct hda_codec *codec = audio_ptr;
2867 int pin_nid;
2868 int dev_id = pipe;
2869
2870 pin_nid = intel_port2pin(codec, port);
2871 if (!pin_nid)
2872 return;
2873 /* skip notification during system suspend (but not in runtime PM);
2874 * the state will be updated at resume
2875 */
2876 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2877 return;
2878
2879 snd_hdac_i915_set_bclk(&codec->bus->core);
2880 check_presence_and_report(codec, pin_nid, dev_id);
2881 }
2882
2883 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2884 .pin2port = intel_pin2port,
2885 .pin_eld_notify = intel_pin_eld_notify,
2886 };
2887
2888 /* register i915 component pin_eld_notify callback */
2889 static void register_i915_notifier(struct hda_codec *codec)
2890 {
2891 struct hdmi_spec *spec = codec->spec;
2892
2893 spec->use_acomp_notifier = true;
2894 spec->port2pin = intel_port2pin;
2895 setup_drm_audio_ops(codec, &intel_audio_ops);
2896 snd_hdac_acomp_register_notifier(&codec->bus->core,
2897 &spec->drm_audio_ops);
2898 /* no need for forcible resume for jack check thanks to notifier */
2899 codec->relaxed_resume = 1;
2900 }
2901
2902 /* setup_stream ops override for HSW+ */
2903 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2904 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2905 int format)
2906 {
2907 struct hdmi_spec *spec = codec->spec;
2908 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
2909 struct hdmi_spec_per_pin *per_pin;
2910 int res;
2911
2912 if (pin_idx < 0)
2913 per_pin = NULL;
2914 else
2915 per_pin = get_pin(spec, pin_idx);
2916
2917 haswell_verify_D0(codec, cvt_nid, pin_nid);
2918
2919 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2920 silent_stream_set_kae(codec, per_pin, false);
2921 /* wait for pending transfers in codec to clear */
2922 usleep_range(100, 200);
2923 }
2924
2925 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2926 stream_tag, format);
2927
2928 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2929 usleep_range(100, 200);
2930 silent_stream_set_kae(codec, per_pin, true);
2931 }
2932
2933 return res;
2934 }
2935
2936 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2937 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2938 struct hdmi_spec_per_pin *per_pin,
2939 hda_nid_t cvt_nid)
2940 {
2941 if (per_pin) {
2942 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2943 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2944 per_pin->dev_id);
2945 intel_verify_pin_cvt_connect(codec, per_pin);
2946 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2947 per_pin->dev_id, per_pin->mux_idx);
2948 } else {
2949 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2950 }
2951 }
2952
2953 static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
2954 {
2955 struct hdmi_spec *spec = codec->spec;
2956 bool silent_streams = false;
2957 int pin_idx, res;
2958
2959 res = generic_hdmi_suspend(codec);
2960
2961 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2962 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2963
2964 if (per_pin->silent_stream) {
2965 silent_streams = true;
2966 break;
2967 }
2968 }
2969
2970 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
2971 /*
2972 * stream-id should remain programmed when codec goes
2973 * to runtime suspend
2974 */
2975 codec->no_stream_clean_at_suspend = 1;
2976
2977 /*
2978 * the system might go to S3, in which case keep-alive
2979 * must be reprogrammed upon resume
2980 */
2981 codec->forced_resume = 1;
2982
2983 codec_dbg(codec, "HDMI: KAE active at suspend\n");
2984 } else {
2985 codec->no_stream_clean_at_suspend = 0;
2986 codec->forced_resume = 0;
2987 }
2988
2989 return res;
2990 }
2991
2992 static int i915_adlp_hdmi_resume(struct hda_codec *codec)
2993 {
2994 struct hdmi_spec *spec = codec->spec;
2995 int pin_idx, res;
2996
2997 res = generic_hdmi_resume(codec);
2998
2999 /* KAE not programmed at suspend, nothing to do here */
3000 if (!codec->no_stream_clean_at_suspend)
3001 return res;
3002
3003 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3004 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3005
3006 /*
3007 * If system was in suspend with monitor connected,
3008 * the codec setting may have been lost. Re-enable
3009 * keep-alive.
3010 */
3011 if (per_pin->silent_stream) {
3012 unsigned int param;
3013
3014 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3015 AC_VERB_GET_CONV, 0);
3016 if (!param) {
3017 codec_dbg(codec, "HDMI: KAE: restore stream id\n");
3018 silent_stream_enable_i915(codec, per_pin);
3019 }
3020
3021 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3022 AC_VERB_GET_DIGI_CONVERT_1, 0);
3023 if (!(param & (AC_DIG3_KAE << 16))) {
3024 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
3025 silent_stream_set_kae(codec, per_pin, true);
3026 }
3027 }
3028 }
3029
3030 return res;
3031 }
3032
3033 /* precondition and allocation for Intel codecs */
3034 static int alloc_intel_hdmi(struct hda_codec *codec)
3035 {
3036 int err;
3037
3038 /* requires i915 binding */
3039 if (!codec->bus->core.audio_component) {
3040 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
3041 /* set probe_id here to prevent generic fallback binding */
3042 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
3043 return -ENODEV;
3044 }
3045
3046 err = alloc_generic_hdmi(codec);
3047 if (err < 0)
3048 return err;
3049 /* no need to handle unsol events */
3050 codec->patch_ops.unsol_event = NULL;
3051 return 0;
3052 }
3053
3054 /* parse and post-process for Intel codecs */
3055 static int parse_intel_hdmi(struct hda_codec *codec)
3056 {
3057 int err, retries = 3;
3058
3059 do {
3060 err = hdmi_parse_codec(codec);
3061 } while (err < 0 && retries--);
3062
3063 if (err < 0) {
3064 generic_spec_free(codec);
3065 return err;
3066 }
3067
3068 generic_hdmi_init_per_pins(codec);
3069 register_i915_notifier(codec);
3070 return 0;
3071 }
3072
3073 /* Intel Haswell and onwards; audio component with eld notifier */
3074 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3075 const int *port_map, int port_num, int dev_num,
3076 bool send_silent_stream)
3077 {
3078 struct hdmi_spec *spec;
3079 int err;
3080
3081 err = alloc_intel_hdmi(codec);
3082 if (err < 0)
3083 return err;
3084 spec = codec->spec;
3085 codec->dp_mst = true;
3086 spec->vendor_nid = vendor_nid;
3087 spec->port_map = port_map;
3088 spec->port_num = port_num;
3089 spec->intel_hsw_fixup = true;
3090 spec->dev_num = dev_num;
3091
3092 intel_haswell_enable_all_pins(codec, true);
3093 intel_haswell_fixup_enable_dp12(codec);
3094
3095 codec->display_power_control = 1;
3096
3097 codec->patch_ops.set_power_state = haswell_set_power_state;
3098 codec->depop_delay = 0;
3099 codec->auto_runtime_pm = 1;
3100
3101 spec->ops.setup_stream = i915_hsw_setup_stream;
3102 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3103
3104 /*
3105 * Enable silent stream feature, if it is enabled via
3106 * module param or Kconfig option
3107 */
3108 if (send_silent_stream)
3109 spec->silent_stream_type = SILENT_STREAM_I915;
3110
3111 return parse_intel_hdmi(codec);
3112 }
3113
3114 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3115 {
3116 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3117 enable_silent_stream);
3118 }
3119
3120 static int patch_i915_glk_hdmi(struct hda_codec *codec)
3121 {
3122 /*
3123 * Silent stream calls audio component .get_power() from
3124 * .pin_eld_notify(). On GLK this will deadlock in i915 due
3125 * to the audio vs. CDCLK workaround.
3126 */
3127 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3128 }
3129
3130 static int patch_i915_icl_hdmi(struct hda_codec *codec)
3131 {
3132 /*
3133 * pin to port mapping table where the value indicate the pin number and
3134 * the index indicate the port number.
3135 */
3136 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3137
3138 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3139 enable_silent_stream);
3140 }
3141
3142 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3143 {
3144 /*
3145 * pin to port mapping table where the value indicate the pin number and
3146 * the index indicate the port number.
3147 */
3148 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3149
3150 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3151 enable_silent_stream);
3152 }
3153
3154 static int patch_i915_adlp_hdmi(struct hda_codec *codec)
3155 {
3156 struct hdmi_spec *spec;
3157 int res;
3158
3159 res = patch_i915_tgl_hdmi(codec);
3160 if (!res) {
3161 spec = codec->spec;
3162
3163 if (spec->silent_stream_type) {
3164 spec->silent_stream_type = SILENT_STREAM_KAE;
3165
3166 codec->patch_ops.resume = i915_adlp_hdmi_resume;
3167 codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
3168 }
3169 }
3170
3171 return res;
3172 }
3173
3174 /* Intel Baytrail and Braswell; with eld notifier */
3175 static int patch_i915_byt_hdmi(struct hda_codec *codec)
3176 {
3177 struct hdmi_spec *spec;
3178 int err;
3179
3180 err = alloc_intel_hdmi(codec);
3181 if (err < 0)
3182 return err;
3183 spec = codec->spec;
3184
3185 /* For Valleyview/Cherryview, only the display codec is in the display
3186 * power well and can use link_power ops to request/release the power.
3187 */
3188 codec->display_power_control = 1;
3189
3190 codec->depop_delay = 0;
3191 codec->auto_runtime_pm = 1;
3192
3193 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3194
3195 return parse_intel_hdmi(codec);
3196 }
3197
3198 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3199 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3200 {
3201 int err;
3202
3203 err = alloc_intel_hdmi(codec);
3204 if (err < 0)
3205 return err;
3206 return parse_intel_hdmi(codec);
3207 }
3208
3209 /*
3210 * Shared non-generic implementations
3211 */
3212
3213 static int simple_playback_build_pcms(struct hda_codec *codec)
3214 {
3215 struct hdmi_spec *spec = codec->spec;
3216 struct hda_pcm *info;
3217 unsigned int chans;
3218 struct hda_pcm_stream *pstr;
3219 struct hdmi_spec_per_cvt *per_cvt;
3220
3221 per_cvt = get_cvt(spec, 0);
3222 chans = get_wcaps(codec, per_cvt->cvt_nid);
3223 chans = get_wcaps_channels(chans);
3224
3225 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3226 if (!info)
3227 return -ENOMEM;
3228 spec->pcm_rec[0].pcm = info;
3229 info->pcm_type = HDA_PCM_TYPE_HDMI;
3230 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3231 *pstr = spec->pcm_playback;
3232 pstr->nid = per_cvt->cvt_nid;
3233 if (pstr->channels_max <= 2 && chans && chans <= 16)
3234 pstr->channels_max = chans;
3235
3236 return 0;
3237 }
3238
3239 /* unsolicited event for jack sensing */
3240 static void simple_hdmi_unsol_event(struct hda_codec *codec,
3241 unsigned int res)
3242 {
3243 snd_hda_jack_set_dirty_all(codec);
3244 snd_hda_jack_report_sync(codec);
3245 }
3246
3247 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
3248 * as long as spec->pins[] is set correctly
3249 */
3250 #define simple_hdmi_build_jack generic_hdmi_build_jack
3251
3252 static int simple_playback_build_controls(struct hda_codec *codec)
3253 {
3254 struct hdmi_spec *spec = codec->spec;
3255 struct hdmi_spec_per_cvt *per_cvt;
3256 int err;
3257
3258 per_cvt = get_cvt(spec, 0);
3259 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3260 per_cvt->cvt_nid,
3261 HDA_PCM_TYPE_HDMI);
3262 if (err < 0)
3263 return err;
3264 return simple_hdmi_build_jack(codec, 0);
3265 }
3266
3267 static int simple_playback_init(struct hda_codec *codec)
3268 {
3269 struct hdmi_spec *spec = codec->spec;
3270 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3271 hda_nid_t pin = per_pin->pin_nid;
3272
3273 snd_hda_codec_write(codec, pin, 0,
3274 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3275 /* some codecs require to unmute the pin */
3276 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3277 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3278 AMP_OUT_UNMUTE);
3279 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3280 return 0;
3281 }
3282
3283 static void simple_playback_free(struct hda_codec *codec)
3284 {
3285 struct hdmi_spec *spec = codec->spec;
3286
3287 hdmi_array_free(spec);
3288 kfree(spec);
3289 }
3290
3291 /*
3292 * Nvidia specific implementations
3293 */
3294
3295 #define Nv_VERB_SET_Channel_Allocation 0xF79
3296 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3297 #define Nv_VERB_SET_Audio_Protection_On 0xF98
3298 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
3299
3300 #define nvhdmi_master_con_nid_7x 0x04
3301 #define nvhdmi_master_pin_nid_7x 0x05
3302
3303 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3304 /*front, rear, clfe, rear_surr */
3305 0x6, 0x8, 0xa, 0xc,
3306 };
3307
3308 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3309 /* set audio protect on */
3310 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3311 /* enable digital output on pin widget */
3312 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3313 {} /* terminator */
3314 };
3315
3316 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3317 /* set audio protect on */
3318 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3319 /* enable digital output on pin widget */
3320 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3321 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3322 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3323 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3324 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3325 {} /* terminator */
3326 };
3327
3328 #ifdef LIMITED_RATE_FMT_SUPPORT
3329 /* support only the safe format and rate */
3330 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3331 #define SUPPORTED_MAXBPS 16
3332 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3333 #else
3334 /* support all rates and formats */
3335 #define SUPPORTED_RATES \
3336 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3337 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3338 SNDRV_PCM_RATE_192000)
3339 #define SUPPORTED_MAXBPS 24
3340 #define SUPPORTED_FORMATS \
3341 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3342 #endif
3343
3344 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3345 {
3346 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3347 return 0;
3348 }
3349
3350 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3351 {
3352 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3353 return 0;
3354 }
3355
3356 static const unsigned int channels_2_6_8[] = {
3357 2, 6, 8
3358 };
3359
3360 static const unsigned int channels_2_8[] = {
3361 2, 8
3362 };
3363
3364 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3365 .count = ARRAY_SIZE(channels_2_6_8),
3366 .list = channels_2_6_8,
3367 .mask = 0,
3368 };
3369
3370 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3371 .count = ARRAY_SIZE(channels_2_8),
3372 .list = channels_2_8,
3373 .mask = 0,
3374 };
3375
3376 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3377 struct hda_codec *codec,
3378 struct snd_pcm_substream *substream)
3379 {
3380 struct hdmi_spec *spec = codec->spec;
3381 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3382
3383 switch (codec->preset->vendor_id) {
3384 case 0x10de0002:
3385 case 0x10de0003:
3386 case 0x10de0005:
3387 case 0x10de0006:
3388 hw_constraints_channels = &hw_constraints_2_8_channels;
3389 break;
3390 case 0x10de0007:
3391 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3392 break;
3393 default:
3394 break;
3395 }
3396
3397 if (hw_constraints_channels != NULL) {
3398 snd_pcm_hw_constraint_list(substream->runtime, 0,
3399 SNDRV_PCM_HW_PARAM_CHANNELS,
3400 hw_constraints_channels);
3401 } else {
3402 snd_pcm_hw_constraint_step(substream->runtime, 0,
3403 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3404 }
3405
3406 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3407 }
3408
3409 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3410 struct hda_codec *codec,
3411 struct snd_pcm_substream *substream)
3412 {
3413 struct hdmi_spec *spec = codec->spec;
3414 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3415 }
3416
3417 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3418 struct hda_codec *codec,
3419 unsigned int stream_tag,
3420 unsigned int format,
3421 struct snd_pcm_substream *substream)
3422 {
3423 struct hdmi_spec *spec = codec->spec;
3424 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3425 stream_tag, format, substream);
3426 }
3427
3428 static const struct hda_pcm_stream simple_pcm_playback = {
3429 .substreams = 1,
3430 .channels_min = 2,
3431 .channels_max = 2,
3432 .ops = {
3433 .open = simple_playback_pcm_open,
3434 .close = simple_playback_pcm_close,
3435 .prepare = simple_playback_pcm_prepare
3436 },
3437 };
3438
3439 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3440 .build_controls = simple_playback_build_controls,
3441 .build_pcms = simple_playback_build_pcms,
3442 .init = simple_playback_init,
3443 .free = simple_playback_free,
3444 .unsol_event = simple_hdmi_unsol_event,
3445 };
3446
3447 static int patch_simple_hdmi(struct hda_codec *codec,
3448 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3449 {
3450 struct hdmi_spec *spec;
3451 struct hdmi_spec_per_cvt *per_cvt;
3452 struct hdmi_spec_per_pin *per_pin;
3453
3454 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3455 if (!spec)
3456 return -ENOMEM;
3457
3458 spec->codec = codec;
3459 codec->spec = spec;
3460 hdmi_array_init(spec, 1);
3461
3462 spec->multiout.num_dacs = 0; /* no analog */
3463 spec->multiout.max_channels = 2;
3464 spec->multiout.dig_out_nid = cvt_nid;
3465 spec->num_cvts = 1;
3466 spec->num_pins = 1;
3467 per_pin = snd_array_new(&spec->pins);
3468 per_cvt = snd_array_new(&spec->cvts);
3469 if (!per_pin || !per_cvt) {
3470 simple_playback_free(codec);
3471 return -ENOMEM;
3472 }
3473 per_cvt->cvt_nid = cvt_nid;
3474 per_pin->pin_nid = pin_nid;
3475 spec->pcm_playback = simple_pcm_playback;
3476
3477 codec->patch_ops = simple_hdmi_patch_ops;
3478
3479 return 0;
3480 }
3481
3482 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3483 int channels)
3484 {
3485 unsigned int chanmask;
3486 int chan = channels ? (channels - 1) : 1;
3487
3488 switch (channels) {
3489 default:
3490 case 0:
3491 case 2:
3492 chanmask = 0x00;
3493 break;
3494 case 4:
3495 chanmask = 0x08;
3496 break;
3497 case 6:
3498 chanmask = 0x0b;
3499 break;
3500 case 8:
3501 chanmask = 0x13;
3502 break;
3503 }
3504
3505 /* Set the audio infoframe channel allocation and checksum fields. The
3506 * channel count is computed implicitly by the hardware. */
3507 snd_hda_codec_write(codec, 0x1, 0,
3508 Nv_VERB_SET_Channel_Allocation, chanmask);
3509
3510 snd_hda_codec_write(codec, 0x1, 0,
3511 Nv_VERB_SET_Info_Frame_Checksum,
3512 (0x71 - chan - chanmask));
3513 }
3514
3515 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3516 struct hda_codec *codec,
3517 struct snd_pcm_substream *substream)
3518 {
3519 struct hdmi_spec *spec = codec->spec;
3520 int i;
3521
3522 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3523 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3524 for (i = 0; i < 4; i++) {
3525 /* set the stream id */
3526 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3527 AC_VERB_SET_CHANNEL_STREAMID, 0);
3528 /* set the stream format */
3529 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3530 AC_VERB_SET_STREAM_FORMAT, 0);
3531 }
3532
3533 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3534 * streams are disabled. */
3535 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3536
3537 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3538 }
3539
3540 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3541 struct hda_codec *codec,
3542 unsigned int stream_tag,
3543 unsigned int format,
3544 struct snd_pcm_substream *substream)
3545 {
3546 int chs;
3547 unsigned int dataDCC2, channel_id;
3548 int i;
3549 struct hdmi_spec *spec = codec->spec;
3550 struct hda_spdif_out *spdif;
3551 struct hdmi_spec_per_cvt *per_cvt;
3552
3553 mutex_lock(&codec->spdif_mutex);
3554 per_cvt = get_cvt(spec, 0);
3555 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3556
3557 chs = substream->runtime->channels;
3558
3559 dataDCC2 = 0x2;
3560
3561 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3562 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3563 snd_hda_codec_write(codec,
3564 nvhdmi_master_con_nid_7x,
3565 0,
3566 AC_VERB_SET_DIGI_CONVERT_1,
3567 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3568
3569 /* set the stream id */
3570 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3571 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3572
3573 /* set the stream format */
3574 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3575 AC_VERB_SET_STREAM_FORMAT, format);
3576
3577 /* turn on again (if needed) */
3578 /* enable and set the channel status audio/data flag */
3579 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3580 snd_hda_codec_write(codec,
3581 nvhdmi_master_con_nid_7x,
3582 0,
3583 AC_VERB_SET_DIGI_CONVERT_1,
3584 spdif->ctls & 0xff);
3585 snd_hda_codec_write(codec,
3586 nvhdmi_master_con_nid_7x,
3587 0,
3588 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3589 }
3590
3591 for (i = 0; i < 4; i++) {
3592 if (chs == 2)
3593 channel_id = 0;
3594 else
3595 channel_id = i * 2;
3596
3597 /* turn off SPDIF once;
3598 *otherwise the IEC958 bits won't be updated
3599 */
3600 if (codec->spdif_status_reset &&
3601 (spdif->ctls & AC_DIG1_ENABLE))
3602 snd_hda_codec_write(codec,
3603 nvhdmi_con_nids_7x[i],
3604 0,
3605 AC_VERB_SET_DIGI_CONVERT_1,
3606 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3607 /* set the stream id */
3608 snd_hda_codec_write(codec,
3609 nvhdmi_con_nids_7x[i],
3610 0,
3611 AC_VERB_SET_CHANNEL_STREAMID,
3612 (stream_tag << 4) | channel_id);
3613 /* set the stream format */
3614 snd_hda_codec_write(codec,
3615 nvhdmi_con_nids_7x[i],
3616 0,
3617 AC_VERB_SET_STREAM_FORMAT,
3618 format);
3619 /* turn on again (if needed) */
3620 /* enable and set the channel status audio/data flag */
3621 if (codec->spdif_status_reset &&
3622 (spdif->ctls & AC_DIG1_ENABLE)) {
3623 snd_hda_codec_write(codec,
3624 nvhdmi_con_nids_7x[i],
3625 0,
3626 AC_VERB_SET_DIGI_CONVERT_1,
3627 spdif->ctls & 0xff);
3628 snd_hda_codec_write(codec,
3629 nvhdmi_con_nids_7x[i],
3630 0,
3631 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3632 }
3633 }
3634
3635 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3636
3637 mutex_unlock(&codec->spdif_mutex);
3638 return 0;
3639 }
3640
3641 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3642 .substreams = 1,
3643 .channels_min = 2,
3644 .channels_max = 8,
3645 .nid = nvhdmi_master_con_nid_7x,
3646 .rates = SUPPORTED_RATES,
3647 .maxbps = SUPPORTED_MAXBPS,
3648 .formats = SUPPORTED_FORMATS,
3649 .ops = {
3650 .open = simple_playback_pcm_open,
3651 .close = nvhdmi_8ch_7x_pcm_close,
3652 .prepare = nvhdmi_8ch_7x_pcm_prepare
3653 },
3654 };
3655
3656 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3657 {
3658 struct hdmi_spec *spec;
3659 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3660 nvhdmi_master_pin_nid_7x);
3661 if (err < 0)
3662 return err;
3663
3664 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3665 /* override the PCM rates, etc, as the codec doesn't give full list */
3666 spec = codec->spec;
3667 spec->pcm_playback.rates = SUPPORTED_RATES;
3668 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3669 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3670 spec->nv_dp_workaround = true;
3671 return 0;
3672 }
3673
3674 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3675 {
3676 struct hdmi_spec *spec = codec->spec;
3677 int err = simple_playback_build_pcms(codec);
3678 if (!err) {
3679 struct hda_pcm *info = get_pcm_rec(spec, 0);
3680 info->own_chmap = true;
3681 }
3682 return err;
3683 }
3684
3685 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3686 {
3687 struct hdmi_spec *spec = codec->spec;
3688 struct hda_pcm *info;
3689 struct snd_pcm_chmap *chmap;
3690 int err;
3691
3692 err = simple_playback_build_controls(codec);
3693 if (err < 0)
3694 return err;
3695
3696 /* add channel maps */
3697 info = get_pcm_rec(spec, 0);
3698 err = snd_pcm_add_chmap_ctls(info->pcm,
3699 SNDRV_PCM_STREAM_PLAYBACK,
3700 snd_pcm_alt_chmaps, 8, 0, &chmap);
3701 if (err < 0)
3702 return err;
3703 switch (codec->preset->vendor_id) {
3704 case 0x10de0002:
3705 case 0x10de0003:
3706 case 0x10de0005:
3707 case 0x10de0006:
3708 chmap->channel_mask = (1U << 2) | (1U << 8);
3709 break;
3710 case 0x10de0007:
3711 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3712 }
3713 return 0;
3714 }
3715
3716 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3717 {
3718 struct hdmi_spec *spec;
3719 int err = patch_nvhdmi_2ch(codec);
3720 if (err < 0)
3721 return err;
3722 spec = codec->spec;
3723 spec->multiout.max_channels = 8;
3724 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3725 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3726 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3727 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3728
3729 /* Initialize the audio infoframe channel mask and checksum to something
3730 * valid */
3731 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3732
3733 return 0;
3734 }
3735
3736 /*
3737 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3738 * - 0x10de0015
3739 * - 0x10de0040
3740 */
3741 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3742 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3743 {
3744 if (cap->ca_index == 0x00 && channels == 2)
3745 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3746
3747 /* If the speaker allocation matches the channel count, it is OK. */
3748 if (cap->channels != channels)
3749 return -1;
3750
3751 /* all channels are remappable freely */
3752 return SNDRV_CTL_TLVT_CHMAP_VAR;
3753 }
3754
3755 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3756 int ca, int chs, unsigned char *map)
3757 {
3758 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3759 return -EINVAL;
3760
3761 return 0;
3762 }
3763
3764 /* map from pin NID to port; port is 0-based */
3765 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3766 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3767 {
3768 return pin_nid - 4;
3769 }
3770
3771 /* reverse-map from port to pin NID: see above */
3772 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3773 {
3774 return port + 4;
3775 }
3776
3777 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3778 .pin2port = nvhdmi_pin2port,
3779 .pin_eld_notify = generic_acomp_pin_eld_notify,
3780 .master_bind = generic_acomp_master_bind,
3781 .master_unbind = generic_acomp_master_unbind,
3782 };
3783
3784 static int patch_nvhdmi(struct hda_codec *codec)
3785 {
3786 struct hdmi_spec *spec;
3787 int err;
3788
3789 err = alloc_generic_hdmi(codec);
3790 if (err < 0)
3791 return err;
3792 codec->dp_mst = true;
3793
3794 spec = codec->spec;
3795
3796 err = hdmi_parse_codec(codec);
3797 if (err < 0) {
3798 generic_spec_free(codec);
3799 return err;
3800 }
3801
3802 generic_hdmi_init_per_pins(codec);
3803
3804 spec->dyn_pin_out = true;
3805
3806 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3807 nvhdmi_chmap_cea_alloc_validate_get_type;
3808 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3809 spec->nv_dp_workaround = true;
3810
3811 codec->link_down_at_suspend = 1;
3812
3813 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3814
3815 return 0;
3816 }
3817
3818 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3819 {
3820 struct hdmi_spec *spec;
3821 int err;
3822
3823 err = patch_generic_hdmi(codec);
3824 if (err)
3825 return err;
3826
3827 spec = codec->spec;
3828 spec->dyn_pin_out = true;
3829
3830 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3831 nvhdmi_chmap_cea_alloc_validate_get_type;
3832 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3833 spec->nv_dp_workaround = true;
3834
3835 codec->link_down_at_suspend = 1;
3836
3837 return 0;
3838 }
3839
3840 /*
3841 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3842 * accessed using vendor-defined verbs. These registers can be used for
3843 * interoperability between the HDA and HDMI drivers.
3844 */
3845
3846 /* Audio Function Group node */
3847 #define NVIDIA_AFG_NID 0x01
3848
3849 /*
3850 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3851 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3852 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3853 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3854 * additional bit (at position 30) to signal the validity of the format.
3855 *
3856 * | 31 | 30 | 29 16 | 15 0 |
3857 * +---------+-------+--------+--------+
3858 * | TRIGGER | VALID | UNUSED | FORMAT |
3859 * +-----------------------------------|
3860 *
3861 * Note that for the trigger bit to take effect it needs to change value
3862 * (i.e. it needs to be toggled). The trigger bit is not applicable from
3863 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
3864 * trigger to hdmi.
3865 */
3866 #define NVIDIA_SET_HOST_INTR 0xf80
3867 #define NVIDIA_GET_SCRATCH0 0xfa6
3868 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3869 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3870 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3871 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3872 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3873 #define NVIDIA_SCRATCH_VALID (1 << 6)
3874
3875 #define NVIDIA_GET_SCRATCH1 0xfab
3876 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3877 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3878 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3879 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3880
3881 /*
3882 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3883 * the format is invalidated so that the HDMI codec can be disabled.
3884 */
3885 static void tegra_hdmi_set_format(struct hda_codec *codec,
3886 hda_nid_t cvt_nid,
3887 unsigned int format)
3888 {
3889 unsigned int value;
3890 unsigned int nid = NVIDIA_AFG_NID;
3891 struct hdmi_spec *spec = codec->spec;
3892
3893 /*
3894 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
3895 * This resulted in moving scratch registers from audio function
3896 * group to converter widget context. So CVT NID should be used for
3897 * scratch register read/write for DP MST supported Tegra HDA codec.
3898 */
3899 if (codec->dp_mst)
3900 nid = cvt_nid;
3901
3902 /* bits [31:30] contain the trigger and valid bits */
3903 value = snd_hda_codec_read(codec, nid, 0,
3904 NVIDIA_GET_SCRATCH0, 0);
3905 value = (value >> 24) & 0xff;
3906
3907 /* bits [15:0] are used to store the HDA format */
3908 snd_hda_codec_write(codec, nid, 0,
3909 NVIDIA_SET_SCRATCH0_BYTE0,
3910 (format >> 0) & 0xff);
3911 snd_hda_codec_write(codec, nid, 0,
3912 NVIDIA_SET_SCRATCH0_BYTE1,
3913 (format >> 8) & 0xff);
3914
3915 /* bits [16:24] are unused */
3916 snd_hda_codec_write(codec, nid, 0,
3917 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3918
3919 /*
3920 * Bit 30 signals that the data is valid and hence that HDMI audio can
3921 * be enabled.
3922 */
3923 if (format == 0)
3924 value &= ~NVIDIA_SCRATCH_VALID;
3925 else
3926 value |= NVIDIA_SCRATCH_VALID;
3927
3928 if (spec->hdmi_intr_trig_ctrl) {
3929 /*
3930 * For Tegra HDA Codec design from TEGRA234 onwards, the
3931 * Interrupt to hdmi driver is triggered by writing
3932 * non-zero values to verb 0xF80 instead of 31st bit of
3933 * scratch register.
3934 */
3935 snd_hda_codec_write(codec, nid, 0,
3936 NVIDIA_SET_SCRATCH0_BYTE3, value);
3937 snd_hda_codec_write(codec, nid, 0,
3938 NVIDIA_SET_HOST_INTR, 0x1);
3939 } else {
3940 /*
3941 * Whenever the 31st trigger bit is toggled, an interrupt is raised
3942 * in the HDMI codec. The HDMI driver will use that as trigger
3943 * to update its configuration.
3944 */
3945 value ^= NVIDIA_SCRATCH_TRIGGER;
3946
3947 snd_hda_codec_write(codec, nid, 0,
3948 NVIDIA_SET_SCRATCH0_BYTE3, value);
3949 }
3950 }
3951
3952 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3953 struct hda_codec *codec,
3954 unsigned int stream_tag,
3955 unsigned int format,
3956 struct snd_pcm_substream *substream)
3957 {
3958 int err;
3959
3960 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3961 format, substream);
3962 if (err < 0)
3963 return err;
3964
3965 /* notify the HDMI codec of the format change */
3966 tegra_hdmi_set_format(codec, hinfo->nid, format);
3967
3968 return 0;
3969 }
3970
3971 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3972 struct hda_codec *codec,
3973 struct snd_pcm_substream *substream)
3974 {
3975 /* invalidate the format in the HDMI codec */
3976 tegra_hdmi_set_format(codec, hinfo->nid, 0);
3977
3978 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3979 }
3980
3981 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3982 {
3983 struct hdmi_spec *spec = codec->spec;
3984 unsigned int i;
3985
3986 for (i = 0; i < spec->num_pins; i++) {
3987 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3988
3989 if (pcm->pcm_type == type)
3990 return pcm;
3991 }
3992
3993 return NULL;
3994 }
3995
3996 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3997 {
3998 struct hda_pcm_stream *stream;
3999 struct hda_pcm *pcm;
4000 int err;
4001
4002 err = generic_hdmi_build_pcms(codec);
4003 if (err < 0)
4004 return err;
4005
4006 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
4007 if (!pcm)
4008 return -ENODEV;
4009
4010 /*
4011 * Override ->prepare() and ->cleanup() operations to notify the HDMI
4012 * codec about format changes.
4013 */
4014 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
4015 stream->ops.prepare = tegra_hdmi_pcm_prepare;
4016 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
4017
4018 return 0;
4019 }
4020
4021 static int tegra_hdmi_init(struct hda_codec *codec)
4022 {
4023 struct hdmi_spec *spec = codec->spec;
4024 int i, err;
4025
4026 err = hdmi_parse_codec(codec);
4027 if (err < 0) {
4028 generic_spec_free(codec);
4029 return err;
4030 }
4031
4032 for (i = 0; i < spec->num_cvts; i++)
4033 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
4034 AC_VERB_SET_DIGI_CONVERT_1,
4035 AC_DIG1_ENABLE);
4036
4037 generic_hdmi_init_per_pins(codec);
4038
4039 codec->depop_delay = 10;
4040 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
4041 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4042 nvhdmi_chmap_cea_alloc_validate_get_type;
4043 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4044
4045 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4046 nvhdmi_chmap_cea_alloc_validate_get_type;
4047 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4048 spec->nv_dp_workaround = true;
4049
4050 return 0;
4051 }
4052
4053 static int patch_tegra_hdmi(struct hda_codec *codec)
4054 {
4055 int err;
4056
4057 err = alloc_generic_hdmi(codec);
4058 if (err < 0)
4059 return err;
4060
4061 return tegra_hdmi_init(codec);
4062 }
4063
4064 static int patch_tegra234_hdmi(struct hda_codec *codec)
4065 {
4066 struct hdmi_spec *spec;
4067 int err;
4068
4069 err = alloc_generic_hdmi(codec);
4070 if (err < 0)
4071 return err;
4072
4073 codec->dp_mst = true;
4074 spec = codec->spec;
4075 spec->dyn_pin_out = true;
4076 spec->hdmi_intr_trig_ctrl = true;
4077
4078 return tegra_hdmi_init(codec);
4079 }
4080
4081 /*
4082 * ATI/AMD-specific implementations
4083 */
4084
4085 #define is_amdhdmi_rev3_or_later(codec) \
4086 ((codec)->core.vendor_id == 0x1002aa01 && \
4087 ((codec)->core.revision_id & 0xff00) >= 0x0300)
4088 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
4089
4090 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
4091 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
4092 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
4093 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
4094 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
4095 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
4096 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
4097 #define ATI_VERB_SET_HBR_CONTROL 0x77c
4098 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
4099 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
4100 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
4101 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
4102 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
4103 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
4104 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
4105 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
4106 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
4107 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
4108 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
4109 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
4110 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
4111 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
4112 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
4113 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
4114 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
4115
4116 /* AMD specific HDA cvt verbs */
4117 #define ATI_VERB_SET_RAMP_RATE 0x770
4118 #define ATI_VERB_GET_RAMP_RATE 0xf70
4119
4120 #define ATI_OUT_ENABLE 0x1
4121
4122 #define ATI_MULTICHANNEL_MODE_PAIRED 0
4123 #define ATI_MULTICHANNEL_MODE_SINGLE 1
4124
4125 #define ATI_HBR_CAPABLE 0x01
4126 #define ATI_HBR_ENABLE 0x10
4127
4128 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4129 int dev_id, unsigned char *buf, int *eld_size)
4130 {
4131 WARN_ON(dev_id != 0);
4132 /* call hda_eld.c ATI/AMD-specific function */
4133 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
4134 is_amdhdmi_rev3_or_later(codec));
4135 }
4136
4137 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
4138 hda_nid_t pin_nid, int dev_id, int ca,
4139 int active_channels, int conn_type)
4140 {
4141 WARN_ON(dev_id != 0);
4142 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
4143 }
4144
4145 static int atihdmi_paired_swap_fc_lfe(int pos)
4146 {
4147 /*
4148 * ATI/AMD have automatic FC/LFE swap built-in
4149 * when in pairwise mapping mode.
4150 */
4151
4152 switch (pos) {
4153 /* see channel_allocations[].speakers[] */
4154 case 2: return 3;
4155 case 3: return 2;
4156 default: break;
4157 }
4158
4159 return pos;
4160 }
4161
4162 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
4163 int ca, int chs, unsigned char *map)
4164 {
4165 struct hdac_cea_channel_speaker_allocation *cap;
4166 int i, j;
4167
4168 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
4169
4170 cap = snd_hdac_get_ch_alloc_from_ca(ca);
4171 for (i = 0; i < chs; ++i) {
4172 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4173 bool ok = false;
4174 bool companion_ok = false;
4175
4176 if (!mask)
4177 continue;
4178
4179 for (j = 0 + i % 2; j < 8; j += 2) {
4180 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
4181 if (cap->speakers[chan_idx] == mask) {
4182 /* channel is in a supported position */
4183 ok = true;
4184
4185 if (i % 2 == 0 && i + 1 < chs) {
4186 /* even channel, check the odd companion */
4187 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4188 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4189 int comp_mask_act = cap->speakers[comp_chan_idx];
4190
4191 if (comp_mask_req == comp_mask_act)
4192 companion_ok = true;
4193 else
4194 return -EINVAL;
4195 }
4196 break;
4197 }
4198 }
4199
4200 if (!ok)
4201 return -EINVAL;
4202
4203 if (companion_ok)
4204 i++; /* companion channel already checked */
4205 }
4206
4207 return 0;
4208 }
4209
4210 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4211 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4212 {
4213 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4214 int verb;
4215 int ati_channel_setup = 0;
4216
4217 if (hdmi_slot > 7)
4218 return -EINVAL;
4219
4220 if (!has_amd_full_remap_support(codec)) {
4221 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4222
4223 /* In case this is an odd slot but without stream channel, do not
4224 * disable the slot since the corresponding even slot could have a
4225 * channel. In case neither have a channel, the slot pair will be
4226 * disabled when this function is called for the even slot. */
4227 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4228 return 0;
4229
4230 hdmi_slot -= hdmi_slot % 2;
4231
4232 if (stream_channel != 0xf)
4233 stream_channel -= stream_channel % 2;
4234 }
4235
4236 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4237
4238 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4239
4240 if (stream_channel != 0xf)
4241 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4242
4243 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4244 }
4245
4246 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4247 hda_nid_t pin_nid, int asp_slot)
4248 {
4249 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4250 bool was_odd = false;
4251 int ati_asp_slot = asp_slot;
4252 int verb;
4253 int ati_channel_setup;
4254
4255 if (asp_slot > 7)
4256 return -EINVAL;
4257
4258 if (!has_amd_full_remap_support(codec)) {
4259 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4260 if (ati_asp_slot % 2 != 0) {
4261 ati_asp_slot -= 1;
4262 was_odd = true;
4263 }
4264 }
4265
4266 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4267
4268 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4269
4270 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4271 return 0xf;
4272
4273 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4274 }
4275
4276 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4277 struct hdac_chmap *chmap,
4278 struct hdac_cea_channel_speaker_allocation *cap,
4279 int channels)
4280 {
4281 int c;
4282
4283 /*
4284 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4285 * we need to take that into account (a single channel may take 2
4286 * channel slots if we need to carry a silent channel next to it).
4287 * On Rev3+ AMD codecs this function is not used.
4288 */
4289 int chanpairs = 0;
4290
4291 /* We only produce even-numbered channel count TLVs */
4292 if ((channels % 2) != 0)
4293 return -1;
4294
4295 for (c = 0; c < 7; c += 2) {
4296 if (cap->speakers[c] || cap->speakers[c+1])
4297 chanpairs++;
4298 }
4299
4300 if (chanpairs * 2 != channels)
4301 return -1;
4302
4303 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4304 }
4305
4306 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4307 struct hdac_cea_channel_speaker_allocation *cap,
4308 unsigned int *chmap, int channels)
4309 {
4310 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4311 int count = 0;
4312 int c;
4313
4314 for (c = 7; c >= 0; c--) {
4315 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4316 int spk = cap->speakers[chan];
4317 if (!spk) {
4318 /* add N/A channel if the companion channel is occupied */
4319 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4320 chmap[count++] = SNDRV_CHMAP_NA;
4321
4322 continue;
4323 }
4324
4325 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4326 }
4327
4328 WARN_ON(count != channels);
4329 }
4330
4331 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4332 int dev_id, bool hbr)
4333 {
4334 int hbr_ctl, hbr_ctl_new;
4335
4336 WARN_ON(dev_id != 0);
4337
4338 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4339 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4340 if (hbr)
4341 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4342 else
4343 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4344
4345 codec_dbg(codec,
4346 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4347 pin_nid,
4348 hbr_ctl == hbr_ctl_new ? "" : "new-",
4349 hbr_ctl_new);
4350
4351 if (hbr_ctl != hbr_ctl_new)
4352 snd_hda_codec_write(codec, pin_nid, 0,
4353 ATI_VERB_SET_HBR_CONTROL,
4354 hbr_ctl_new);
4355
4356 } else if (hbr)
4357 return -EINVAL;
4358
4359 return 0;
4360 }
4361
4362 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4363 hda_nid_t pin_nid, int dev_id,
4364 u32 stream_tag, int format)
4365 {
4366 if (is_amdhdmi_rev3_or_later(codec)) {
4367 int ramp_rate = 180; /* default as per AMD spec */
4368 /* disable ramp-up/down for non-pcm as per AMD spec */
4369 if (format & AC_FMT_TYPE_NON_PCM)
4370 ramp_rate = 0;
4371
4372 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4373 }
4374
4375 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4376 stream_tag, format);
4377 }
4378
4379
4380 static int atihdmi_init(struct hda_codec *codec)
4381 {
4382 struct hdmi_spec *spec = codec->spec;
4383 int pin_idx, err;
4384
4385 err = generic_hdmi_init(codec);
4386
4387 if (err)
4388 return err;
4389
4390 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4391 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4392
4393 /* make sure downmix information in infoframe is zero */
4394 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4395
4396 /* enable channel-wise remap mode if supported */
4397 if (has_amd_full_remap_support(codec))
4398 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4399 ATI_VERB_SET_MULTICHANNEL_MODE,
4400 ATI_MULTICHANNEL_MODE_SINGLE);
4401 }
4402 codec->auto_runtime_pm = 1;
4403
4404 return 0;
4405 }
4406
4407 /* map from pin NID to port; port is 0-based */
4408 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4409 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4410 {
4411 return pin_nid / 2 - 1;
4412 }
4413
4414 /* reverse-map from port to pin NID: see above */
4415 static int atihdmi_port2pin(struct hda_codec *codec, int port)
4416 {
4417 return port * 2 + 3;
4418 }
4419
4420 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4421 .pin2port = atihdmi_pin2port,
4422 .pin_eld_notify = generic_acomp_pin_eld_notify,
4423 .master_bind = generic_acomp_master_bind,
4424 .master_unbind = generic_acomp_master_unbind,
4425 };
4426
4427 static int patch_atihdmi(struct hda_codec *codec)
4428 {
4429 struct hdmi_spec *spec;
4430 struct hdmi_spec_per_cvt *per_cvt;
4431 int err, cvt_idx;
4432
4433 err = patch_generic_hdmi(codec);
4434
4435 if (err)
4436 return err;
4437
4438 codec->patch_ops.init = atihdmi_init;
4439
4440 spec = codec->spec;
4441
4442 spec->static_pcm_mapping = true;
4443
4444 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4445 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4446 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4447 spec->ops.setup_stream = atihdmi_setup_stream;
4448
4449 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4450 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4451
4452 if (!has_amd_full_remap_support(codec)) {
4453 /* override to ATI/AMD-specific versions with pairwise mapping */
4454 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4455 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4456 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4457 atihdmi_paired_cea_alloc_to_tlv_chmap;
4458 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4459 }
4460
4461 /* ATI/AMD converters do not advertise all of their capabilities */
4462 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4463 per_cvt = get_cvt(spec, cvt_idx);
4464 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4465 per_cvt->rates |= SUPPORTED_RATES;
4466 per_cvt->formats |= SUPPORTED_FORMATS;
4467 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4468 }
4469
4470 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4471
4472 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4473 * the link-down as is. Tell the core to allow it.
4474 */
4475 codec->link_down_at_suspend = 1;
4476
4477 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4478
4479 return 0;
4480 }
4481
4482 /* VIA HDMI Implementation */
4483 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4484 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4485
4486 static int patch_via_hdmi(struct hda_codec *codec)
4487 {
4488 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4489 }
4490
4491 static int patch_gf_hdmi(struct hda_codec *codec)
4492 {
4493 int err;
4494
4495 err = patch_generic_hdmi(codec);
4496 if (err)
4497 return err;
4498
4499 /*
4500 * Glenfly GPUs have two codecs, stream switches from one codec to
4501 * another, need to do actual clean-ups in codec_cleanup_stream
4502 */
4503 codec->no_sticky_stream = 1;
4504 return 0;
4505 }
4506
4507 /*
4508 * patch entries
4509 */
4510 static const struct hda_device_id snd_hda_id_hdmi[] = {
4511 HDA_CODEC_ENTRY(0x00147a47, "Loongson HDMI", patch_generic_hdmi),
4512 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4513 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4514 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4515 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4516 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4517 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4518 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4519 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4520 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4521 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4522 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4523 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4524 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4525 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4526 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4527 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4528 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4529 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4530 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4531 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4532 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4533 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4534 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4535 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4536 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4537 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4538 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4539 /* 17 is known to be absent */
4540 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4541 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4542 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4543 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4544 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4545 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4546 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4547 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4548 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4549 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4550 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4551 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4552 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4553 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4554 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4555 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4556 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4557 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4558 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4559 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4560 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4561 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4562 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4563 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4564 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4565 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4566 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4567 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4568 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4569 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4570 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4571 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4572 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4573 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4574 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4575 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4576 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4577 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4578 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4579 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4580 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4581 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4582 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4583 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4584 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4585 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4586 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4587 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4588 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4589 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4590 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4591 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4592 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4593 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4594 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4595 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4596 HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi),
4597 HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi),
4598 HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi),
4599 HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi),
4600 HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi),
4601 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4602 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4603 HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
4604 HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi),
4605 HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi),
4606 HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi),
4607 HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi),
4608 HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi),
4609 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4610 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4611 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4612 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4613 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4614 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4615 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4616 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4617 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4618 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4619 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4620 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4621 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4622 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4623 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4624 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4625 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4626 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4627 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4628 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4629 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4630 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4631 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4632 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4633 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
4634 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
4635 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4636 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4637 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4638 HDA_CODEC_ENTRY(0x8086281d, "Meteor Lake HDMI", patch_i915_adlp_hdmi),
4639 HDA_CODEC_ENTRY(0x8086281e, "Battlemage HDMI", patch_i915_adlp_hdmi),
4640 HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI", patch_i915_adlp_hdmi),
4641 HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI", patch_i915_adlp_hdmi),
4642 HDA_CODEC_ENTRY(0x80862822, "Panther Lake HDMI", patch_i915_adlp_hdmi),
4643 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4644 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4645 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4646 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4647 /* special ID for generic HDMI */
4648 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4649 {} /* terminator */
4650 };
4651 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4652
4653 MODULE_LICENSE("GPL");
4654 MODULE_DESCRIPTION("HDMI HD-audio codec");
4655 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4656 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4657 MODULE_ALIAS("snd-hda-codec-atihdmi");
4658
4659 static struct hda_codec_driver hdmi_driver = {
4660 .id = snd_hda_id_hdmi,
4661 };
4662
4663 module_hda_codec_driver(hdmi_driver);
4664
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