1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef __SOUND_VT1724_H
3 #define __SOUND_VT1724_H
4
5 /*
6 * ALSA driver for ICEnsemble VT1724 (Envy24)
7 *
8 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
9 */
10
11 #include <sound/control.h>
12 #include <sound/ac97_codec.h>
13 #include <sound/rawmidi.h>
14 #include <sound/i2c.h>
15 #include <sound/pcm.h>
16
17 #include "ice1712.h"
18
19 enum {
20 ICE_EEP2_SYSCONF = 0, /* 06 */
21 ICE_EEP2_ACLINK, /* 07 */
22 ICE_EEP2_I2S, /* 08 */
23 ICE_EEP2_SPDIF, /* 09 */
24 ICE_EEP2_GPIO_DIR, /* 0a */
25 ICE_EEP2_GPIO_DIR1, /* 0b */
26 ICE_EEP2_GPIO_DIR2, /* 0c */
27 ICE_EEP2_GPIO_MASK, /* 0d */
28 ICE_EEP2_GPIO_MASK1, /* 0e */
29 ICE_EEP2_GPIO_MASK2, /* 0f */
30 ICE_EEP2_GPIO_STATE, /* 10 */
31 ICE_EEP2_GPIO_STATE1, /* 11 */
32 ICE_EEP2_GPIO_STATE2 /* 12 */
33 };
34
35 /*
36 * Direct registers
37 */
38
39 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
40
41 #define VT1724_REG_CONTROL 0x00 /* byte */
42 #define VT1724_RESET 0x80 /* reset whole chip */
43 #define VT1724_REG_IRQMASK 0x01 /* byte */
44 #define VT1724_IRQ_MPU_RX 0x80
45 #define VT1724_IRQ_MPU_TX 0x20
46 #define VT1724_IRQ_MTPCM 0x10
47 #define VT1724_REG_IRQSTAT 0x02 /* byte */
48 /* look to VT1724_IRQ_* */
49 #define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
50 #define VT1724_CFG_CLOCK 0xc0
51 #define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
52 #define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
53 #define VT1724_CFG_MPU401 0x20 /* MPU401 UARTs */
54 #define VT1724_CFG_ADC_MASK 0x0c /* one, two or one and S/PDIF, stereo ADCs */
55 #define VT1724_CFG_ADC_NONE 0x0c /* no ADCs */
56 #define VT1724_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
57
58 #define VT1724_REG_AC97_CFG 0x05 /* byte */
59 #define VT1724_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
60 #define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
61
62 #define VT1724_REG_I2S_FEATURES 0x06 /* byte */
63 #define VT1724_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
64 #define VT1724_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
65 #define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
66 #define VT1724_CFG_I2S_192KHZ 0x08 /* supports 192kHz sampling */
67 #define VT1724_CFG_I2S_OTHER 0x07 /* other I2S IDs */
68
69 #define VT1724_REG_SPDIF_CFG 0x07 /* byte */
70 #define VT1724_CFG_SPDIF_OUT_EN 0x80 /*Internal S/PDIF output is enabled*/
71 #define VT1724_CFG_SPDIF_OUT_INT 0x40 /*Internal S/PDIF output is implemented*/
72 #define VT1724_CFG_I2S_CHIPID 0x3c /* I2S chip ID */
73 #define VT1724_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
74 #define VT1724_CFG_SPDIF_OUT 0x01 /* External S/PDIF output is present */
75
76 /*there is no consumer AC97 codec with the VT1724*/
77 //#define VT1724_REG_AC97_INDEX 0x08 /* byte */
78 //#define VT1724_REG_AC97_CMD 0x09 /* byte */
79
80 #define VT1724_REG_MPU_TXFIFO 0x0a /*byte ro. number of bytes in TX fifo*/
81 #define VT1724_REG_MPU_RXFIFO 0x0b /*byte ro. number of bytes in RX fifo*/
82
83 #define VT1724_REG_MPU_DATA 0x0c /* byte */
84 #define VT1724_REG_MPU_CTRL 0x0d /* byte */
85 #define VT1724_MPU_UART 0x01
86 #define VT1724_MPU_TX_EMPTY 0x02
87 #define VT1724_MPU_TX_FULL 0x04
88 #define VT1724_MPU_RX_EMPTY 0x08
89 #define VT1724_MPU_RX_FULL 0x10
90
91 #define VT1724_REG_MPU_FIFO_WM 0x0e /*byte set the high/low watermarks for RX/TX fifos*/
92 #define VT1724_MPU_RX_FIFO 0x20 //1=rx fifo watermark 0=tx fifo watermark
93 #define VT1724_MPU_FIFO_MASK 0x1f
94
95 #define VT1724_REG_I2C_DEV_ADDR 0x10 /* byte */
96 #define VT1724_I2C_WRITE 0x01 /* write direction */
97 #define VT1724_REG_I2C_BYTE_ADDR 0x11 /* byte */
98 #define VT1724_REG_I2C_DATA 0x12 /* byte */
99 #define VT1724_REG_I2C_CTRL 0x13 /* byte */
100 #define VT1724_I2C_EEPROM 0x80 /* 1 = EEPROM exists */
101 #define VT1724_I2C_BUSY 0x01 /* busy bit */
102
103 #define VT1724_REG_GPIO_DATA 0x14 /* word */
104 #define VT1724_REG_GPIO_WRITE_MASK 0x16 /* word */
105 #define VT1724_REG_GPIO_DIRECTION 0x18 /* dword? (3 bytes) 0=input 1=output.
106 bit3 - during reset used for Eeprom power-on strapping
107 if TESTEN# pin active, bit 2 always input*/
108 #define VT1724_REG_POWERDOWN 0x1c
109 #define VT1724_REG_GPIO_DATA_22 0x1e /* byte direction for GPIO 16:22 */
110 #define VT1724_REG_GPIO_WRITE_MASK_22 0x1f /* byte write mask for GPIO 16:22 */
111
112
113 /*
114 * Professional multi-track direct control registers
115 */
116
117 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
118
119 #define VT1724_MT_IRQ 0x00 /* byte - interrupt mask */
120 #define VT1724_MULTI_PDMA4 0x80 /* SPDIF Out / PDMA4 */
121 #define VT1724_MULTI_PDMA3 0x40 /* PDMA3 */
122 #define VT1724_MULTI_PDMA2 0x20 /* PDMA2 */
123 #define VT1724_MULTI_PDMA1 0x10 /* PDMA1 */
124 #define VT1724_MULTI_FIFO_ERR 0x08 /* DMA FIFO underrun/overrun. */
125 #define VT1724_MULTI_RDMA1 0x04 /* RDMA1 (S/PDIF input) */
126 #define VT1724_MULTI_RDMA0 0x02 /* RMDA0 */
127 #define VT1724_MULTI_PDMA0 0x01 /* MC Interleave/PDMA0 */
128
129 #define VT1724_MT_RATE 0x01 /* byte - sampling rate select */
130 #define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
131 #define VT1724_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
132 #define VT1724_MT_I2S_MCLK_128X 0x08
133 #define VT1724_MT_I2S_FORMAT_MASK 0x03
134 #define VT1724_MT_I2S_FORMAT_I2S 0x00
135 #define VT1724_MT_DMA_INT_MASK 0x03 /* byte -DMA Interrupt Mask */
136 /* lool to VT1724_MULTI_* */
137 #define VT1724_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
138 #define VT1724_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
139 #define VT1724_AC97_COLD 0x80 /* cold reset */
140 #define VT1724_AC97_WARM 0x40 /* warm reset */
141 #define VT1724_AC97_WRITE 0x20 /* W: write, R: write in progress */
142 #define VT1724_AC97_READ 0x10 /* W: read, R: read in progress */
143 #define VT1724_AC97_READY 0x08 /* codec ready status bit */
144 #define VT1724_AC97_ID_MASK 0x03 /* codec id mask */
145 #define VT1724_MT_AC97_DATA 0x06 /* word - AC'97 data */
146 #define VT1724_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
147 #define VT1724_MT_PLAYBACK_SIZE 0x14 /* dword - playback size */
148 #define VT1724_MT_DMA_CONTROL 0x18 /* byte - control */
149 #define VT1724_PDMA4_START 0x80 /* SPDIF out / PDMA4 start */
150 #define VT1724_PDMA3_START 0x40 /* PDMA3 start */
151 #define VT1724_PDMA2_START 0x20 /* PDMA2 start */
152 #define VT1724_PDMA1_START 0x10 /* PDMA1 start */
153 #define VT1724_RDMA1_START 0x04 /* RDMA1 start */
154 #define VT1724_RDMA0_START 0x02 /* RMDA0 start */
155 #define VT1724_PDMA0_START 0x01 /* MC Interleave / PDMA0 start */
156 #define VT1724_MT_BURST 0x19 /* Interleaved playback DMA Active streams / PCI burst size */
157 #define VT1724_MT_DMA_FIFO_ERR 0x1a /*Global playback and record DMA FIFO Underrun/Overrun */
158 #define VT1724_PDMA4_UNDERRUN 0x80
159 #define VT1724_PDMA2_UNDERRUN 0x40
160 #define VT1724_PDMA3_UNDERRUN 0x20
161 #define VT1724_PDMA1_UNDERRUN 0x10
162 #define VT1724_RDMA1_UNDERRUN 0x04
163 #define VT1724_RDMA0_UNDERRUN 0x02
164 #define VT1724_PDMA0_UNDERRUN 0x01
165 #define VT1724_MT_DMA_PAUSE 0x1b /*Global playback and record DMA FIFO pause/resume */
166 #define VT1724_PDMA4_PAUSE 0x80
167 #define VT1724_PDMA3_PAUSE 0x40
168 #define VT1724_PDMA2_PAUSE 0x20
169 #define VT1724_PDMA1_PAUSE 0x10
170 #define VT1724_RDMA1_PAUSE 0x04
171 #define VT1724_RDMA0_PAUSE 0x02
172 #define VT1724_PDMA0_PAUSE 0x01
173 #define VT1724_MT_PLAYBACK_COUNT 0x1c /* word - playback count */
174 #define VT1724_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
175 #define VT1724_MT_CAPTURE_SIZE 0x24 /* word - capture size */
176 #define VT1724_MT_CAPTURE_COUNT 0x26 /* word - capture count */
177
178 #define VT1724_MT_ROUTE_PLAYBACK 0x2c /* word */
179
180 #define VT1724_MT_RDMA1_ADDR 0x30 /* dword - RDMA1 capture address */
181 #define VT1724_MT_RDMA1_SIZE 0x34 /* word - RDMA1 capture size */
182 #define VT1724_MT_RDMA1_COUNT 0x36 /* word - RDMA1 capture count */
183
184 #define VT1724_MT_SPDIF_CTRL 0x3c /* word */
185 #define VT1724_MT_MONITOR_PEAKINDEX 0x3e /* byte */
186 #define VT1724_MT_MONITOR_PEAKDATA 0x3f /* byte */
187
188 /* concurrent stereo channels */
189 #define VT1724_MT_PDMA4_ADDR 0x40 /* dword */
190 #define VT1724_MT_PDMA4_SIZE 0x44 /* word */
191 #define VT1724_MT_PDMA4_COUNT 0x46 /* word */
192 #define VT1724_MT_PDMA3_ADDR 0x50 /* dword */
193 #define VT1724_MT_PDMA3_SIZE 0x54 /* word */
194 #define VT1724_MT_PDMA3_COUNT 0x56 /* word */
195 #define VT1724_MT_PDMA2_ADDR 0x60 /* dword */
196 #define VT1724_MT_PDMA2_SIZE 0x64 /* word */
197 #define VT1724_MT_PDMA2_COUNT 0x66 /* word */
198 #define VT1724_MT_PDMA1_ADDR 0x70 /* dword */
199 #define VT1724_MT_PDMA1_SIZE 0x74 /* word */
200 #define VT1724_MT_PDMA1_COUNT 0x76 /* word */
201
202
203 unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr);
204 void snd_vt1724_write_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr, unsigned char data);
205
206 #endif /* __SOUND_VT1724_H */
207
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