1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA modem driver for Intel ICH (i8x0) chipsets
4 *
5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
6 *
7 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
8 * of ALSA ICH sound driver intel8x0.c .
9 */
10
11 #include <linux/io.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/slab.h>
17 #include <linux/module.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/ac97_codec.h>
21 #include <sound/info.h>
22 #include <sound/initval.h>
23
24 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
25 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
26 "SiS 7013; NVidia MCP/2/2S/3 modems");
27 MODULE_LICENSE("GPL");
28
29 static int index = -2; /* Exclude the first card */
30 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
31 static int ac97_clock;
32
33 module_param(index, int, 0444);
34 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
35 module_param(id, charp, 0444);
36 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
37 module_param(ac97_clock, int, 0444);
38 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
39
40 /* just for backward compatibility */
41 static bool enable;
42 module_param(enable, bool, 0444);
43
44 /*
45 * Direct registers
46 */
47 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
48
49 #define ICHREG(x) ICH_REG_##x
50
51 #define DEFINE_REGSET(name,base) \
52 enum { \
53 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
54 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
55 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
56 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
57 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
58 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
59 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
60 }
61
62 /* busmaster blocks */
63 DEFINE_REGSET(OFF, 0); /* offset */
64
65 /* values for each busmaster block */
66
67 /* LVI */
68 #define ICH_REG_LVI_MASK 0x1f
69
70 /* SR */
71 #define ICH_FIFOE 0x10 /* FIFO error */
72 #define ICH_BCIS 0x08 /* buffer completion interrupt status */
73 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
74 #define ICH_CELV 0x02 /* current equals last valid */
75 #define ICH_DCH 0x01 /* DMA controller halted */
76
77 /* PIV */
78 #define ICH_REG_PIV_MASK 0x1f /* mask */
79
80 /* CR */
81 #define ICH_IOCE 0x10 /* interrupt on completion enable */
82 #define ICH_FEIE 0x08 /* fifo error interrupt enable */
83 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
84 #define ICH_RESETREGS 0x02 /* reset busmaster registers */
85 #define ICH_STARTBM 0x01 /* start busmaster operation */
86
87
88 /* global block */
89 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */
90 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
91 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
92 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
93 #define ICH_ACLINK 0x00000008 /* AClink shut off */
94 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
95 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
96 #define ICH_GIE 0x00000001 /* GPI interrupt enable */
97 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */
98 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
99 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
100 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
101 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
102 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
103 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
104 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
105 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
106 #define ICH_MD3 0x00020000 /* modem power down semaphore */
107 #define ICH_AD3 0x00010000 /* audio power down semaphore */
108 #define ICH_RCS 0x00008000 /* read completion status */
109 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
110 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
111 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
112 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
113 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
114 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
115 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
116 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
117 #define ICH_POINT 0x00000040 /* playback interrupt */
118 #define ICH_PIINT 0x00000020 /* capture interrupt */
119 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
120 #define ICH_MOINT 0x00000004 /* modem playback interrupt */
121 #define ICH_MIINT 0x00000002 /* modem capture interrupt */
122 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
123 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */
124 #define ICH_CAS 0x01 /* codec access semaphore */
125
126 #define ICH_MAX_FRAGS 32 /* max hw frags */
127
128
129 /*
130 *
131 */
132
133 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
134 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
135
136 #define get_ichdev(substream) (substream->runtime->private_data)
137
138 struct ichdev {
139 unsigned int ichd; /* ich device number */
140 unsigned long reg_offset; /* offset to bmaddr */
141 __le32 *bdbar; /* CPU address (32bit) */
142 unsigned int bdbar_addr; /* PCI bus address (32bit) */
143 struct snd_pcm_substream *substream;
144 unsigned int physbuf; /* physical address (32bit) */
145 unsigned int size;
146 unsigned int fragsize;
147 unsigned int fragsize1;
148 unsigned int position;
149 int frags;
150 int lvi;
151 int lvi_frag;
152 int civ;
153 int ack;
154 int ack_reload;
155 unsigned int ack_bit;
156 unsigned int roff_sr;
157 unsigned int roff_picb;
158 unsigned int int_sta_mask; /* interrupt status mask */
159 unsigned int ali_slot; /* ALI DMA slot */
160 struct snd_ac97 *ac97;
161 };
162
163 struct intel8x0m {
164 unsigned int device_type;
165
166 int irq;
167
168 void __iomem *addr;
169 void __iomem *bmaddr;
170
171 struct pci_dev *pci;
172 struct snd_card *card;
173
174 int pcm_devs;
175 struct snd_pcm *pcm[2];
176 struct ichdev ichd[2];
177
178 unsigned int in_ac97_init: 1;
179
180 struct snd_ac97_bus *ac97_bus;
181 struct snd_ac97 *ac97;
182
183 spinlock_t reg_lock;
184
185 struct snd_dma_buffer *bdbars;
186 u32 bdbars_count;
187 u32 int_sta_reg; /* interrupt status register */
188 u32 int_sta_mask; /* interrupt status mask */
189 unsigned int pcm_pos_shift;
190 };
191
192 static const struct pci_device_id snd_intel8x0m_ids[] = {
193 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */
194 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */
195 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */
196 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */
197 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */
198 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */
199 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */
200 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */
201 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */
202 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */
203 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */
204 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */
205 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */
206 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */
207 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */
208 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */
209 #if 0
210 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
211 #endif
212 { 0, }
213 };
214
215 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
216
217 /*
218 * Lowlevel I/O - busmaster
219 */
220
221 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
222 {
223 return ioread8(chip->bmaddr + offset);
224 }
225
226 static inline u16 igetword(struct intel8x0m *chip, u32 offset)
227 {
228 return ioread16(chip->bmaddr + offset);
229 }
230
231 static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
232 {
233 return ioread32(chip->bmaddr + offset);
234 }
235
236 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
237 {
238 iowrite8(val, chip->bmaddr + offset);
239 }
240
241 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
242 {
243 iowrite16(val, chip->bmaddr + offset);
244 }
245
246 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
247 {
248 iowrite32(val, chip->bmaddr + offset);
249 }
250
251 /*
252 * Lowlevel I/O - AC'97 registers
253 */
254
255 static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
256 {
257 return ioread16(chip->addr + offset);
258 }
259
260 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
261 {
262 iowrite16(val, chip->addr + offset);
263 }
264
265 /*
266 * Basic I/O
267 */
268
269 /*
270 * access to AC97 codec via normal i/o (for ICH and SIS7013)
271 */
272
273 /* return the GLOB_STA bit for the corresponding codec */
274 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
275 {
276 static const unsigned int codec_bit[3] = {
277 ICH_PCR, ICH_SCR, ICH_TCR
278 };
279 if (snd_BUG_ON(codec >= 3))
280 return ICH_PCR;
281 return codec_bit[codec];
282 }
283
284 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
285 {
286 int time;
287
288 if (codec > 1)
289 return -EIO;
290 codec = get_ich_codec_bit(chip, codec);
291
292 /* codec ready ? */
293 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
294 return -EIO;
295
296 /* Anyone holding a semaphore for 1 msec should be shot... */
297 time = 100;
298 do {
299 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
300 return 0;
301 udelay(10);
302 } while (time--);
303
304 /* access to some forbidden (non existent) ac97 registers will not
305 * reset the semaphore. So even if you don't get the semaphore, still
306 * continue the access. We don't need the semaphore anyway. */
307 dev_err(chip->card->dev,
308 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
309 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
310 iagetword(chip, 0); /* clear semaphore flag */
311 /* I don't care about the semaphore */
312 return -EBUSY;
313 }
314
315 static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97,
316 unsigned short reg,
317 unsigned short val)
318 {
319 struct intel8x0m *chip = ac97->private_data;
320
321 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
322 if (! chip->in_ac97_init)
323 dev_err(chip->card->dev,
324 "codec_write %d: semaphore is not ready for register 0x%x\n",
325 ac97->num, reg);
326 }
327 iaputword(chip, reg + ac97->num * 0x80, val);
328 }
329
330 static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97,
331 unsigned short reg)
332 {
333 struct intel8x0m *chip = ac97->private_data;
334 unsigned short res;
335 unsigned int tmp;
336
337 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
338 if (! chip->in_ac97_init)
339 dev_err(chip->card->dev,
340 "codec_read %d: semaphore is not ready for register 0x%x\n",
341 ac97->num, reg);
342 res = 0xffff;
343 } else {
344 res = iagetword(chip, reg + ac97->num * 0x80);
345 tmp = igetdword(chip, ICHREG(GLOB_STA));
346 if (tmp & ICH_RCS) {
347 /* reset RCS and preserve other R/WC bits */
348 iputdword(chip, ICHREG(GLOB_STA),
349 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
350 if (! chip->in_ac97_init)
351 dev_err(chip->card->dev,
352 "codec_read %d: read timeout for register 0x%x\n",
353 ac97->num, reg);
354 res = 0xffff;
355 }
356 }
357 if (reg == AC97_GPIO_STATUS)
358 iagetword(chip, 0); /* clear semaphore */
359 return res;
360 }
361
362
363 /*
364 * DMA I/O
365 */
366 static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
367 {
368 int idx;
369 __le32 *bdbar = ichdev->bdbar;
370 unsigned long port = ichdev->reg_offset;
371
372 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
373 if (ichdev->size == ichdev->fragsize) {
374 ichdev->ack_reload = ichdev->ack = 2;
375 ichdev->fragsize1 = ichdev->fragsize >> 1;
376 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
377 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
378 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
379 ichdev->fragsize1 >> chip->pcm_pos_shift);
380 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
381 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
382 ichdev->fragsize1 >> chip->pcm_pos_shift);
383 }
384 ichdev->frags = 2;
385 } else {
386 ichdev->ack_reload = ichdev->ack = 1;
387 ichdev->fragsize1 = ichdev->fragsize;
388 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
389 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
390 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
391 ichdev->fragsize >> chip->pcm_pos_shift);
392 /*
393 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
394 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
395 */
396 }
397 ichdev->frags = ichdev->size / ichdev->fragsize;
398 }
399 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
400 ichdev->civ = 0;
401 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
402 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
403 ichdev->position = 0;
404 #if 0
405 dev_dbg(chip->card->dev,
406 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
407 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
408 ichdev->fragsize1);
409 #endif
410 /* clear interrupts */
411 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
412 }
413
414 /*
415 * Interrupt handler
416 */
417
418 static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev)
419 {
420 unsigned long port = ichdev->reg_offset;
421 int civ, i, step;
422 int ack = 0;
423
424 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
425 if (civ == ichdev->civ) {
426 // snd_printd("civ same %d\n", civ);
427 step = 1;
428 ichdev->civ++;
429 ichdev->civ &= ICH_REG_LVI_MASK;
430 } else {
431 step = civ - ichdev->civ;
432 if (step < 0)
433 step += ICH_REG_LVI_MASK + 1;
434 // if (step != 1)
435 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
436 ichdev->civ = civ;
437 }
438
439 ichdev->position += step * ichdev->fragsize1;
440 ichdev->position %= ichdev->size;
441 ichdev->lvi += step;
442 ichdev->lvi &= ICH_REG_LVI_MASK;
443 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
444 for (i = 0; i < step; i++) {
445 ichdev->lvi_frag++;
446 ichdev->lvi_frag %= ichdev->frags;
447 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
448 ichdev->lvi_frag *
449 ichdev->fragsize1);
450 #if 0
451 dev_dbg(chip->card->dev,
452 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
453 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
454 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
455 inl(port + 4), inb(port + ICH_REG_OFF_CR));
456 #endif
457 if (--ichdev->ack == 0) {
458 ichdev->ack = ichdev->ack_reload;
459 ack = 1;
460 }
461 }
462 if (ack && ichdev->substream) {
463 spin_unlock(&chip->reg_lock);
464 snd_pcm_period_elapsed(ichdev->substream);
465 spin_lock(&chip->reg_lock);
466 }
467 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
468 }
469
470 static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id)
471 {
472 struct intel8x0m *chip = dev_id;
473 struct ichdev *ichdev;
474 unsigned int status;
475 unsigned int i;
476
477 spin_lock(&chip->reg_lock);
478 status = igetdword(chip, chip->int_sta_reg);
479 if (status == 0xffffffff) { /* we are not yet resumed */
480 spin_unlock(&chip->reg_lock);
481 return IRQ_NONE;
482 }
483 if ((status & chip->int_sta_mask) == 0) {
484 if (status)
485 iputdword(chip, chip->int_sta_reg, status);
486 spin_unlock(&chip->reg_lock);
487 return IRQ_NONE;
488 }
489
490 for (i = 0; i < chip->bdbars_count; i++) {
491 ichdev = &chip->ichd[i];
492 if (status & ichdev->int_sta_mask)
493 snd_intel8x0m_update(chip, ichdev);
494 }
495
496 /* ack them */
497 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
498 spin_unlock(&chip->reg_lock);
499
500 return IRQ_HANDLED;
501 }
502
503 /*
504 * PCM part
505 */
506
507 static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
508 {
509 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
510 struct ichdev *ichdev = get_ichdev(substream);
511 unsigned char val = 0;
512 unsigned long port = ichdev->reg_offset;
513
514 switch (cmd) {
515 case SNDRV_PCM_TRIGGER_START:
516 case SNDRV_PCM_TRIGGER_RESUME:
517 val = ICH_IOCE | ICH_STARTBM;
518 break;
519 case SNDRV_PCM_TRIGGER_STOP:
520 case SNDRV_PCM_TRIGGER_SUSPEND:
521 val = 0;
522 break;
523 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
524 val = ICH_IOCE;
525 break;
526 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
527 val = ICH_IOCE | ICH_STARTBM;
528 break;
529 default:
530 return -EINVAL;
531 }
532 iputbyte(chip, port + ICH_REG_OFF_CR, val);
533 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
534 /* wait until DMA stopped */
535 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
536 /* reset whole DMA things */
537 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
538 }
539 return 0;
540 }
541
542 static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream)
543 {
544 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
545 struct ichdev *ichdev = get_ichdev(substream);
546 size_t ptr1, ptr;
547
548 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
549 if (ptr1 != 0)
550 ptr = ichdev->fragsize1 - ptr1;
551 else
552 ptr = 0;
553 ptr += ichdev->position;
554 if (ptr >= ichdev->size)
555 return 0;
556 return bytes_to_frames(substream->runtime, ptr);
557 }
558
559 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
560 {
561 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
562 struct snd_pcm_runtime *runtime = substream->runtime;
563 struct ichdev *ichdev = get_ichdev(substream);
564
565 ichdev->physbuf = runtime->dma_addr;
566 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
567 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
568 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
569 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
570 snd_intel8x0m_setup_periods(chip, ichdev);
571 return 0;
572 }
573
574 static const struct snd_pcm_hardware snd_intel8x0m_stream =
575 {
576 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
577 SNDRV_PCM_INFO_BLOCK_TRANSFER |
578 SNDRV_PCM_INFO_MMAP_VALID |
579 SNDRV_PCM_INFO_PAUSE |
580 SNDRV_PCM_INFO_RESUME),
581 .formats = SNDRV_PCM_FMTBIT_S16_LE,
582 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
583 .rate_min = 8000,
584 .rate_max = 16000,
585 .channels_min = 1,
586 .channels_max = 1,
587 .buffer_bytes_max = 64 * 1024,
588 .period_bytes_min = 32,
589 .period_bytes_max = 64 * 1024,
590 .periods_min = 1,
591 .periods_max = 1024,
592 .fifo_size = 0,
593 };
594
595
596 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
597 {
598 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 };
599 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
600 .count = ARRAY_SIZE(rates),
601 .list = rates,
602 .mask = 0,
603 };
604 struct snd_pcm_runtime *runtime = substream->runtime;
605 int err;
606
607 ichdev->substream = substream;
608 runtime->hw = snd_intel8x0m_stream;
609 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
610 &hw_constraints_rates);
611 if ( err < 0 )
612 return err;
613 runtime->private_data = ichdev;
614 return 0;
615 }
616
617 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
618 {
619 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
620
621 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
622 }
623
624 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
625 {
626 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
627
628 chip->ichd[ICHD_MDMOUT].substream = NULL;
629 return 0;
630 }
631
632 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
633 {
634 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
635
636 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
637 }
638
639 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
640 {
641 struct intel8x0m *chip = snd_pcm_substream_chip(substream);
642
643 chip->ichd[ICHD_MDMIN].substream = NULL;
644 return 0;
645 }
646
647
648 static const struct snd_pcm_ops snd_intel8x0m_playback_ops = {
649 .open = snd_intel8x0m_playback_open,
650 .close = snd_intel8x0m_playback_close,
651 .prepare = snd_intel8x0m_pcm_prepare,
652 .trigger = snd_intel8x0m_pcm_trigger,
653 .pointer = snd_intel8x0m_pcm_pointer,
654 };
655
656 static const struct snd_pcm_ops snd_intel8x0m_capture_ops = {
657 .open = snd_intel8x0m_capture_open,
658 .close = snd_intel8x0m_capture_close,
659 .prepare = snd_intel8x0m_pcm_prepare,
660 .trigger = snd_intel8x0m_pcm_trigger,
661 .pointer = snd_intel8x0m_pcm_pointer,
662 };
663
664
665 struct ich_pcm_table {
666 char *suffix;
667 const struct snd_pcm_ops *playback_ops;
668 const struct snd_pcm_ops *capture_ops;
669 size_t prealloc_size;
670 size_t prealloc_max_size;
671 int ac97_idx;
672 };
673
674 static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device,
675 const struct ich_pcm_table *rec)
676 {
677 struct snd_pcm *pcm;
678 int err;
679 char name[32];
680
681 if (rec->suffix)
682 sprintf(name, "Intel ICH - %s", rec->suffix);
683 else
684 strcpy(name, "Intel ICH");
685 err = snd_pcm_new(chip->card, name, device,
686 rec->playback_ops ? 1 : 0,
687 rec->capture_ops ? 1 : 0, &pcm);
688 if (err < 0)
689 return err;
690
691 if (rec->playback_ops)
692 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
693 if (rec->capture_ops)
694 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
695
696 pcm->private_data = chip;
697 pcm->info_flags = 0;
698 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
699 if (rec->suffix)
700 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
701 else
702 strcpy(pcm->name, chip->card->shortname);
703 chip->pcm[device] = pcm;
704
705 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
706 &chip->pci->dev,
707 rec->prealloc_size,
708 rec->prealloc_max_size);
709
710 return 0;
711 }
712
713 static const struct ich_pcm_table intel_pcms[] = {
714 {
715 .suffix = "Modem",
716 .playback_ops = &snd_intel8x0m_playback_ops,
717 .capture_ops = &snd_intel8x0m_capture_ops,
718 .prealloc_size = 32 * 1024,
719 .prealloc_max_size = 64 * 1024,
720 },
721 };
722
723 static int snd_intel8x0m_pcm(struct intel8x0m *chip)
724 {
725 int i, tblsize, device, err;
726 const struct ich_pcm_table *tbl, *rec;
727
728 #if 1
729 tbl = intel_pcms;
730 tblsize = 1;
731 #else
732 switch (chip->device_type) {
733 case DEVICE_NFORCE:
734 tbl = nforce_pcms;
735 tblsize = ARRAY_SIZE(nforce_pcms);
736 break;
737 case DEVICE_ALI:
738 tbl = ali_pcms;
739 tblsize = ARRAY_SIZE(ali_pcms);
740 break;
741 default:
742 tbl = intel_pcms;
743 tblsize = 2;
744 break;
745 }
746 #endif
747 device = 0;
748 for (i = 0; i < tblsize; i++) {
749 rec = tbl + i;
750 if (i > 0 && rec->ac97_idx) {
751 /* activate PCM only when associated AC'97 codec */
752 if (! chip->ichd[rec->ac97_idx].ac97)
753 continue;
754 }
755 err = snd_intel8x0m_pcm1(chip, device, rec);
756 if (err < 0)
757 return err;
758 device++;
759 }
760
761 chip->pcm_devs = device;
762 return 0;
763 }
764
765
766 /*
767 * Mixer part
768 */
769
770 static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
771 {
772 struct intel8x0m *chip = bus->private_data;
773 chip->ac97_bus = NULL;
774 }
775
776 static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97)
777 {
778 struct intel8x0m *chip = ac97->private_data;
779 chip->ac97 = NULL;
780 }
781
782
783 static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock)
784 {
785 struct snd_ac97_bus *pbus;
786 struct snd_ac97_template ac97;
787 struct snd_ac97 *x97;
788 int err;
789 unsigned int glob_sta = 0;
790 static const struct snd_ac97_bus_ops ops = {
791 .write = snd_intel8x0m_codec_write,
792 .read = snd_intel8x0m_codec_read,
793 };
794
795 chip->in_ac97_init = 1;
796
797 memset(&ac97, 0, sizeof(ac97));
798 ac97.private_data = chip;
799 ac97.private_free = snd_intel8x0m_mixer_free_ac97;
800 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
801
802 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
803
804 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus);
805 if (err < 0)
806 goto __err;
807 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus;
808 if (ac97_clock >= 8000 && ac97_clock <= 48000)
809 pbus->clock = ac97_clock;
810 chip->ac97_bus = pbus;
811
812 ac97.pci = chip->pci;
813 ac97.num = glob_sta & ICH_SCR ? 1 : 0;
814 err = snd_ac97_mixer(pbus, &ac97, &x97);
815 if (err < 0) {
816 dev_err(chip->card->dev,
817 "Unable to initialize codec #%d\n", ac97.num);
818 if (ac97.num == 0)
819 goto __err;
820 return err;
821 }
822 chip->ac97 = x97;
823 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
824 chip->ichd[ICHD_MDMIN].ac97 = x97;
825 chip->ichd[ICHD_MDMOUT].ac97 = x97;
826 }
827
828 chip->in_ac97_init = 0;
829 return 0;
830
831 __err:
832 /* clear the cold-reset bit for the next chance */
833 if (chip->device_type != DEVICE_ALI)
834 iputdword(chip, ICHREG(GLOB_CNT),
835 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
836 return err;
837 }
838
839
840 /*
841 *
842 */
843
844 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
845 {
846 unsigned long end_time;
847 unsigned int cnt, status, nstatus;
848
849 /* put logic to right state */
850 /* first clear status bits */
851 status = ICH_RCS | ICH_MIINT | ICH_MOINT;
852 cnt = igetdword(chip, ICHREG(GLOB_STA));
853 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
854
855 /* ACLink on, 2 channels */
856 cnt = igetdword(chip, ICHREG(GLOB_CNT));
857 cnt &= ~(ICH_ACLINK);
858 /* finish cold or do warm reset */
859 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
860 iputdword(chip, ICHREG(GLOB_CNT), cnt);
861 usleep_range(500, 1000); /* give warm reset some time */
862 end_time = jiffies + HZ / 4;
863 do {
864 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
865 goto __ok;
866 schedule_timeout_uninterruptible(1);
867 } while (time_after_eq(end_time, jiffies));
868 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
869 igetdword(chip, ICHREG(GLOB_CNT)));
870 return -EIO;
871
872 __ok:
873 if (probing) {
874 /* wait for any codec ready status.
875 * Once it becomes ready it should remain ready
876 * as long as we do not disable the ac97 link.
877 */
878 end_time = jiffies + HZ;
879 do {
880 status = igetdword(chip, ICHREG(GLOB_STA)) &
881 (ICH_PCR | ICH_SCR | ICH_TCR);
882 if (status)
883 break;
884 schedule_timeout_uninterruptible(1);
885 } while (time_after_eq(end_time, jiffies));
886 if (! status) {
887 /* no codec is found */
888 dev_err(chip->card->dev,
889 "codec_ready: codec is not ready [0x%x]\n",
890 igetdword(chip, ICHREG(GLOB_STA)));
891 return -EIO;
892 }
893
894 /* up to two codecs (modem cannot be tertiary with ICH4) */
895 nstatus = ICH_PCR | ICH_SCR;
896
897 /* wait for other codecs ready status. */
898 end_time = jiffies + HZ / 4;
899 while (status != nstatus && time_after_eq(end_time, jiffies)) {
900 schedule_timeout_uninterruptible(1);
901 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
902 }
903
904 } else {
905 /* resume phase */
906 status = 0;
907 if (chip->ac97)
908 status |= get_ich_codec_bit(chip, chip->ac97->num);
909 /* wait until all the probed codecs are ready */
910 end_time = jiffies + HZ;
911 do {
912 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
913 (ICH_PCR | ICH_SCR | ICH_TCR);
914 if (status == nstatus)
915 break;
916 schedule_timeout_uninterruptible(1);
917 } while (time_after_eq(end_time, jiffies));
918 }
919
920 if (chip->device_type == DEVICE_SIS) {
921 /* unmute the output on SIS7013 */
922 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
923 }
924
925 return 0;
926 }
927
928 static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing)
929 {
930 unsigned int i;
931 int err;
932
933 err = snd_intel8x0m_ich_chip_init(chip, probing);
934 if (err < 0)
935 return err;
936 iagetword(chip, 0); /* clear semaphore flag */
937
938 /* disable interrupts */
939 for (i = 0; i < chip->bdbars_count; i++)
940 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
941 /* reset channels */
942 for (i = 0; i < chip->bdbars_count; i++)
943 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
944 /* initialize Buffer Descriptor Lists */
945 for (i = 0; i < chip->bdbars_count; i++)
946 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
947 return 0;
948 }
949
950 static void snd_intel8x0m_free(struct snd_card *card)
951 {
952 struct intel8x0m *chip = card->private_data;
953 unsigned int i;
954
955 if (chip->irq < 0)
956 goto __hw_end;
957 /* disable interrupts */
958 for (i = 0; i < chip->bdbars_count; i++)
959 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
960 /* reset channels */
961 for (i = 0; i < chip->bdbars_count; i++)
962 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
963 __hw_end:
964 if (chip->irq >= 0)
965 free_irq(chip->irq, chip);
966 }
967
968 /*
969 * power management
970 */
971 static int intel8x0m_suspend(struct device *dev)
972 {
973 struct snd_card *card = dev_get_drvdata(dev);
974 struct intel8x0m *chip = card->private_data;
975
976 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
977 snd_ac97_suspend(chip->ac97);
978 if (chip->irq >= 0) {
979 free_irq(chip->irq, chip);
980 chip->irq = -1;
981 card->sync_irq = -1;
982 }
983 return 0;
984 }
985
986 static int intel8x0m_resume(struct device *dev)
987 {
988 struct pci_dev *pci = to_pci_dev(dev);
989 struct snd_card *card = dev_get_drvdata(dev);
990 struct intel8x0m *chip = card->private_data;
991
992 if (request_irq(pci->irq, snd_intel8x0m_interrupt,
993 IRQF_SHARED, KBUILD_MODNAME, chip)) {
994 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
995 pci->irq);
996 snd_card_disconnect(card);
997 return -EIO;
998 }
999 chip->irq = pci->irq;
1000 card->sync_irq = chip->irq;
1001 snd_intel8x0m_chip_init(chip, 0);
1002 snd_ac97_resume(chip->ac97);
1003
1004 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1005 return 0;
1006 }
1007
1008 static DEFINE_SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume);
1009
1010 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1011 struct snd_info_buffer *buffer)
1012 {
1013 struct intel8x0m *chip = entry->private_data;
1014 unsigned int tmp;
1015
1016 snd_iprintf(buffer, "Intel8x0m\n\n");
1017 if (chip->device_type == DEVICE_ALI)
1018 return;
1019 tmp = igetdword(chip, ICHREG(GLOB_STA));
1020 snd_iprintf(buffer, "Global control : 0x%08x\n",
1021 igetdword(chip, ICHREG(GLOB_CNT)));
1022 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
1023 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
1024 tmp & ICH_PCR ? " primary" : "",
1025 tmp & ICH_SCR ? " secondary" : "",
1026 tmp & ICH_TCR ? " tertiary" : "",
1027 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1028 }
1029
1030 static void snd_intel8x0m_proc_init(struct intel8x0m *chip)
1031 {
1032 snd_card_ro_proc_new(chip->card, "intel8x0m", chip,
1033 snd_intel8x0m_proc_read);
1034 }
1035
1036 struct ich_reg_info {
1037 unsigned int int_sta_mask;
1038 unsigned int offset;
1039 };
1040
1041 static int snd_intel8x0m_init(struct snd_card *card,
1042 struct pci_dev *pci,
1043 unsigned long device_type)
1044 {
1045 struct intel8x0m *chip = card->private_data;
1046 int err;
1047 unsigned int i;
1048 unsigned int int_sta_masks;
1049 struct ichdev *ichdev;
1050 static const struct ich_reg_info intel_regs[2] = {
1051 { ICH_MIINT, 0 },
1052 { ICH_MOINT, 0x10 },
1053 };
1054 const struct ich_reg_info *tbl;
1055
1056 err = pcim_enable_device(pci);
1057 if (err < 0)
1058 return err;
1059
1060 spin_lock_init(&chip->reg_lock);
1061 chip->device_type = device_type;
1062 chip->card = card;
1063 chip->pci = pci;
1064 chip->irq = -1;
1065
1066 err = pci_request_regions(pci, card->shortname);
1067 if (err < 0)
1068 return err;
1069
1070 if (device_type == DEVICE_ALI) {
1071 /* ALI5455 has no ac97 region */
1072 chip->bmaddr = pcim_iomap(pci, 0, 0);
1073 } else {
1074 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1075 chip->addr = pcim_iomap(pci, 2, 0);
1076 else
1077 chip->addr = pcim_iomap(pci, 0, 0);
1078 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1079 chip->bmaddr = pcim_iomap(pci, 3, 0);
1080 else
1081 chip->bmaddr = pcim_iomap(pci, 1, 0);
1082 }
1083
1084 /* initialize offsets */
1085 chip->bdbars_count = 2;
1086 tbl = intel_regs;
1087
1088 for (i = 0; i < chip->bdbars_count; i++) {
1089 ichdev = &chip->ichd[i];
1090 ichdev->ichd = i;
1091 ichdev->reg_offset = tbl[i].offset;
1092 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1093 if (device_type == DEVICE_SIS) {
1094 /* SiS 7013 swaps the registers */
1095 ichdev->roff_sr = ICH_REG_OFF_PICB;
1096 ichdev->roff_picb = ICH_REG_OFF_SR;
1097 } else {
1098 ichdev->roff_sr = ICH_REG_OFF_SR;
1099 ichdev->roff_picb = ICH_REG_OFF_PICB;
1100 }
1101 if (device_type == DEVICE_ALI)
1102 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1103 }
1104 /* SIS7013 handles the pcm data in bytes, others are in words */
1105 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1106
1107 /* allocate buffer descriptor lists */
1108 /* the start of each lists must be aligned to 8 bytes */
1109 chip->bdbars = snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV,
1110 chip->bdbars_count * sizeof(u32) *
1111 ICH_MAX_FRAGS * 2);
1112 if (!chip->bdbars)
1113 return -ENOMEM;
1114
1115 /* tables must be aligned to 8 bytes here, but the kernel pages
1116 are much bigger, so we don't care (on i386) */
1117 int_sta_masks = 0;
1118 for (i = 0; i < chip->bdbars_count; i++) {
1119 ichdev = &chip->ichd[i];
1120 ichdev->bdbar = ((__le32 *)chip->bdbars->area) + (i * ICH_MAX_FRAGS * 2);
1121 ichdev->bdbar_addr = chip->bdbars->addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1122 int_sta_masks |= ichdev->int_sta_mask;
1123 }
1124 chip->int_sta_reg = ICH_REG_GLOB_STA;
1125 chip->int_sta_mask = int_sta_masks;
1126
1127 pci_set_master(pci);
1128
1129 err = snd_intel8x0m_chip_init(chip, 1);
1130 if (err < 0)
1131 return err;
1132
1133 /* NOTE: we don't use devm version here since it's released /
1134 * re-acquired in PM callbacks.
1135 * It's released explicitly in snd_intel8x0m_free(), too.
1136 */
1137 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED,
1138 KBUILD_MODNAME, chip)) {
1139 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1140 return -EBUSY;
1141 }
1142 chip->irq = pci->irq;
1143 card->sync_irq = chip->irq;
1144
1145 card->private_free = snd_intel8x0m_free;
1146
1147 return 0;
1148 }
1149
1150 static struct shortname_table {
1151 unsigned int id;
1152 const char *s;
1153 } shortnames[] = {
1154 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1155 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1156 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1157 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1158 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1159 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1160 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1161 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1162 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1163 { 0x7446, "AMD AMD768" },
1164 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1165 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1166 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1167 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1168 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1169 { 0x746e, "AMD AMD8111" },
1170 #if 0
1171 { 0x5455, "ALi M5455" },
1172 #endif
1173 { 0 },
1174 };
1175
1176 static int __snd_intel8x0m_probe(struct pci_dev *pci,
1177 const struct pci_device_id *pci_id)
1178 {
1179 struct snd_card *card;
1180 struct intel8x0m *chip;
1181 int err;
1182 struct shortname_table *name;
1183
1184 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE,
1185 sizeof(*chip), &card);
1186 if (err < 0)
1187 return err;
1188 chip = card->private_data;
1189
1190 strcpy(card->driver, "ICH-MODEM");
1191 strcpy(card->shortname, "Intel ICH");
1192 for (name = shortnames; name->id; name++) {
1193 if (pci->device == name->id) {
1194 strcpy(card->shortname, name->s);
1195 break;
1196 }
1197 }
1198 strcat(card->shortname," Modem");
1199
1200 err = snd_intel8x0m_init(card, pci, pci_id->driver_data);
1201 if (err < 0)
1202 return err;
1203
1204 err = snd_intel8x0m_mixer(chip, ac97_clock);
1205 if (err < 0)
1206 return err;
1207 err = snd_intel8x0m_pcm(chip);
1208 if (err < 0)
1209 return err;
1210
1211 snd_intel8x0m_proc_init(chip);
1212
1213 sprintf(card->longname, "%s at irq %i",
1214 card->shortname, chip->irq);
1215
1216 err = snd_card_register(card);
1217 if (err < 0)
1218 return err;
1219 pci_set_drvdata(pci, card);
1220 return 0;
1221 }
1222
1223 static int snd_intel8x0m_probe(struct pci_dev *pci,
1224 const struct pci_device_id *pci_id)
1225 {
1226 return snd_card_free_on_error(&pci->dev, __snd_intel8x0m_probe(pci, pci_id));
1227 }
1228
1229 static struct pci_driver intel8x0m_driver = {
1230 .name = KBUILD_MODNAME,
1231 .id_table = snd_intel8x0m_ids,
1232 .probe = snd_intel8x0m_probe,
1233 .driver = {
1234 .pm = &intel8x0m_pm,
1235 },
1236 };
1237
1238 module_pci_driver(intel8x0m_driver);
1239
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