1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
4 *
5 * Copyright (c) 2002 Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 */
9
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
18 #include <linux/io.h>
19 #include <linux/nospec.h>
20
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
30
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
33
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
37
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_FIRMWARE("rpm_firmware.bin");
48 MODULE_FIRMWARE("multiface_firmware.bin");
49 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
50 MODULE_FIRMWARE("digiface_firmware.bin");
51 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
52
53 #define HDSP_MAX_CHANNELS 26
54 #define HDSP_MAX_DS_CHANNELS 14
55 #define HDSP_MAX_QS_CHANNELS 8
56 #define DIGIFACE_SS_CHANNELS 26
57 #define DIGIFACE_DS_CHANNELS 14
58 #define MULTIFACE_SS_CHANNELS 18
59 #define MULTIFACE_DS_CHANNELS 14
60 #define H9652_SS_CHANNELS 26
61 #define H9652_DS_CHANNELS 14
62 /* This does not include possible Analog Extension Boards
63 AEBs are detected at card initialization
64 */
65 #define H9632_SS_CHANNELS 12
66 #define H9632_DS_CHANNELS 8
67 #define H9632_QS_CHANNELS 4
68 #define RPM_CHANNELS 6
69
70 /* Write registers. These are defined as byte-offsets from the iobase value.
71 */
72 #define HDSP_resetPointer 0
73 #define HDSP_freqReg 0
74 #define HDSP_outputBufferAddress 32
75 #define HDSP_inputBufferAddress 36
76 #define HDSP_controlRegister 64
77 #define HDSP_interruptConfirmation 96
78 #define HDSP_outputEnable 128
79 #define HDSP_control2Reg 256
80 #define HDSP_midiDataOut0 352
81 #define HDSP_midiDataOut1 356
82 #define HDSP_fifoData 368
83 #define HDSP_inputEnable 384
84
85 /* Read registers. These are defined as byte-offsets from the iobase value
86 */
87
88 #define HDSP_statusRegister 0
89 #define HDSP_timecode 128
90 #define HDSP_status2Register 192
91 #define HDSP_midiDataIn0 360
92 #define HDSP_midiDataIn1 364
93 #define HDSP_midiStatusOut0 384
94 #define HDSP_midiStatusOut1 388
95 #define HDSP_midiStatusIn0 392
96 #define HDSP_midiStatusIn1 396
97 #define HDSP_fifoStatus 400
98
99 /* the meters are regular i/o-mapped registers, but offset
100 considerably from the rest. the peak registers are reset
101 when read; the least-significant 4 bits are full-scale counters;
102 the actual peak value is in the most-significant 24 bits.
103 */
104
105 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
106 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
107 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
108 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
109 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
110
111
112 /* This is for H9652 cards
113 Peak values are read downward from the base
114 Rms values are read upward
115 There are rms values for the outputs too
116 26*3 values are read in ss mode
117 14*3 in ds mode, with no gap between values
118 */
119 #define HDSP_9652_peakBase 7164
120 #define HDSP_9652_rmsBase 4096
121
122 /* c.f. the hdsp_9632_meters_t struct */
123 #define HDSP_9632_metersBase 4096
124
125 #define HDSP_IO_EXTENT 7168
126
127 /* control2 register bits */
128
129 #define HDSP_TMS 0x01
130 #define HDSP_TCK 0x02
131 #define HDSP_TDI 0x04
132 #define HDSP_JTAG 0x08
133 #define HDSP_PWDN 0x10
134 #define HDSP_PROGRAM 0x020
135 #define HDSP_CONFIG_MODE_0 0x040
136 #define HDSP_CONFIG_MODE_1 0x080
137 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
138 #define HDSP_BIGENDIAN_MODE 0x200
139 #define HDSP_RD_MULTIPLE 0x400
140 #define HDSP_9652_ENABLE_MIXER 0x800
141 #define HDSP_S200 0x800
142 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
143 #define HDSP_CYCLIC_MODE 0x1000
144 #define HDSP_TDO 0x10000000
145
146 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
147 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
148
149 /* Control Register bits */
150
151 #define HDSP_Start (1<<0) /* start engine */
152 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
153 #define HDSP_Latency1 (1<<2) /* [ see above ] */
154 #define HDSP_Latency2 (1<<3) /* [ see above ] */
155 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
156 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
157 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
158 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
159 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
160 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
161 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
162 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
163 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
164 #define HDSP_SyncRef2 (1<<13)
165 #define HDSP_SPDIFInputSelect0 (1<<14)
166 #define HDSP_SPDIFInputSelect1 (1<<15)
167 #define HDSP_SyncRef0 (1<<16)
168 #define HDSP_SyncRef1 (1<<17)
169 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
170 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
171 #define HDSP_Midi0InterruptEnable (1<<22)
172 #define HDSP_Midi1InterruptEnable (1<<23)
173 #define HDSP_LineOut (1<<24)
174 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
175 #define HDSP_ADGain1 (1<<26)
176 #define HDSP_DAGain0 (1<<27)
177 #define HDSP_DAGain1 (1<<28)
178 #define HDSP_PhoneGain0 (1<<29)
179 #define HDSP_PhoneGain1 (1<<30)
180 #define HDSP_QuadSpeed (1<<31)
181
182 /* RPM uses some of the registers for special purposes */
183 #define HDSP_RPM_Inp12 0x04A00
184 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
185 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
186 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
187 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
188 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
189
190 #define HDSP_RPM_Inp34 0x32000
191 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
192 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
193 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
194 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
195 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
196
197 #define HDSP_RPM_Bypass 0x01000
198
199 #define HDSP_RPM_Disconnect 0x00001
200
201 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
202 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
203 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
204 #define HDSP_ADGainLowGain 0
205
206 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
207 #define HDSP_DAGainHighGain HDSP_DAGainMask
208 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
209 #define HDSP_DAGainMinus10dBV 0
210
211 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
212 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
213 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
214 #define HDSP_PhoneGainMinus12dB 0
215
216 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
217 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
218
219 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
220 #define HDSP_SPDIFInputADAT1 0
221 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
222 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
224
225 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
226 #define HDSP_SyncRef_ADAT1 0
227 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
228 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
229 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
230 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
231 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
232
233 /* Sample Clock Sources */
234
235 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
236 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
237 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
238 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
239 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
240 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
241 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
242 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
243 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
244 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
245
246 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
247
248 #define HDSP_SYNC_FROM_WORD 0
249 #define HDSP_SYNC_FROM_SPDIF 1
250 #define HDSP_SYNC_FROM_ADAT1 2
251 #define HDSP_SYNC_FROM_ADAT_SYNC 3
252 #define HDSP_SYNC_FROM_ADAT2 4
253 #define HDSP_SYNC_FROM_ADAT3 5
254
255 /* SyncCheck status */
256
257 #define HDSP_SYNC_CHECK_NO_LOCK 0
258 #define HDSP_SYNC_CHECK_LOCK 1
259 #define HDSP_SYNC_CHECK_SYNC 2
260
261 /* AutoSync references - used by "autosync_ref" control switch */
262
263 #define HDSP_AUTOSYNC_FROM_WORD 0
264 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
265 #define HDSP_AUTOSYNC_FROM_SPDIF 2
266 #define HDSP_AUTOSYNC_FROM_NONE 3
267 #define HDSP_AUTOSYNC_FROM_ADAT1 4
268 #define HDSP_AUTOSYNC_FROM_ADAT2 5
269 #define HDSP_AUTOSYNC_FROM_ADAT3 6
270
271 /* Possible sources of S/PDIF input */
272
273 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
274 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
275 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
276 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
277
278 #define HDSP_Frequency32KHz HDSP_Frequency0
279 #define HDSP_Frequency44_1KHz HDSP_Frequency1
280 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
281 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
282 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
283 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
284 /* For H9632 cards */
285 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
286 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
287 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
288 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
289 return 104857600000000 / rate; // 100 MHz
290 return 110100480000000 / rate; // 105 MHz
291 */
292 #define DDS_NUMERATOR 104857600000000ULL /* = 2^20 * 10^8 */
293
294 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
295 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
296
297 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
298 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
299
300 /* Status Register bits */
301
302 #define HDSP_audioIRQPending (1<<0)
303 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
304 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
305 #define HDSP_Lock1 (1<<2)
306 #define HDSP_Lock0 (1<<3)
307 #define HDSP_SPDIFSync (1<<4)
308 #define HDSP_TimecodeLock (1<<5)
309 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
310 #define HDSP_Sync2 (1<<16)
311 #define HDSP_Sync1 (1<<17)
312 #define HDSP_Sync0 (1<<18)
313 #define HDSP_DoubleSpeedStatus (1<<19)
314 #define HDSP_ConfigError (1<<20)
315 #define HDSP_DllError (1<<21)
316 #define HDSP_spdifFrequency0 (1<<22)
317 #define HDSP_spdifFrequency1 (1<<23)
318 #define HDSP_spdifFrequency2 (1<<24)
319 #define HDSP_SPDIFErrorFlag (1<<25)
320 #define HDSP_BufferID (1<<26)
321 #define HDSP_TimecodeSync (1<<27)
322 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
323 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
324 #define HDSP_midi0IRQPending (1<<30)
325 #define HDSP_midi1IRQPending (1<<31)
326
327 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
328 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
329 HDSP_spdifFrequency1|\
330 HDSP_spdifFrequency2|\
331 HDSP_spdifFrequency3)
332
333 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
334 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
335 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
336
337 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
338 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
339 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
340
341 /* This is for H9632 cards */
342 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
343 HDSP_spdifFrequency1|\
344 HDSP_spdifFrequency2)
345 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
346 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
347
348 /* Status2 Register bits */
349
350 #define HDSP_version0 (1<<0)
351 #define HDSP_version1 (1<<1)
352 #define HDSP_version2 (1<<2)
353 #define HDSP_wc_lock (1<<3)
354 #define HDSP_wc_sync (1<<4)
355 #define HDSP_inp_freq0 (1<<5)
356 #define HDSP_inp_freq1 (1<<6)
357 #define HDSP_inp_freq2 (1<<7)
358 #define HDSP_SelSyncRef0 (1<<8)
359 #define HDSP_SelSyncRef1 (1<<9)
360 #define HDSP_SelSyncRef2 (1<<10)
361
362 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
363
364 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
365 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
366 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
367 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
368 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
369 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
370 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
371 /* FIXME : more values for 9632 cards ? */
372
373 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
374 #define HDSP_SelSyncRef_ADAT1 0
375 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
376 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
377 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
378 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
379 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
380
381 /* Card state flags */
382
383 #define HDSP_InitializationComplete (1<<0)
384 #define HDSP_FirmwareLoaded (1<<1)
385 #define HDSP_FirmwareCached (1<<2)
386
387 /* FIFO wait times, defined in terms of 1/10ths of msecs */
388
389 #define HDSP_LONG_WAIT 5000
390 #define HDSP_SHORT_WAIT 30
391
392 #define UNITY_GAIN 32768
393 #define MINUS_INFINITY_GAIN 0
394
395 /* the size of a substream (1 mono data stream) */
396
397 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
398 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
399
400 /* the size of the area we need to allocate for DMA transfers. the
401 size is the same regardless of the number of channels - the
402 Multiface still uses the same memory area.
403
404 Note that we allocate 1 more channel than is apparently needed
405 because the h/w seems to write 1 byte beyond the end of the last
406 page. Sigh.
407 */
408
409 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
410 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
411
412 #define HDSP_FIRMWARE_SIZE (24413 * 4)
413
414 struct hdsp_9632_meters {
415 u32 input_peak[16];
416 u32 playback_peak[16];
417 u32 output_peak[16];
418 u32 xxx_peak[16];
419 u32 padding[64];
420 u32 input_rms_low[16];
421 u32 playback_rms_low[16];
422 u32 output_rms_low[16];
423 u32 xxx_rms_low[16];
424 u32 input_rms_high[16];
425 u32 playback_rms_high[16];
426 u32 output_rms_high[16];
427 u32 xxx_rms_high[16];
428 };
429
430 struct hdsp_midi {
431 struct hdsp *hdsp;
432 int id;
433 struct snd_rawmidi *rmidi;
434 struct snd_rawmidi_substream *input;
435 struct snd_rawmidi_substream *output;
436 signed char istimer; /* timer in use */
437 struct timer_list timer;
438 spinlock_t lock;
439 int pending;
440 };
441
442 struct hdsp {
443 spinlock_t lock;
444 struct snd_pcm_substream *capture_substream;
445 struct snd_pcm_substream *playback_substream;
446 struct hdsp_midi midi[2];
447 struct work_struct midi_work;
448 int use_midi_work;
449 int precise_ptr;
450 u32 control_register; /* cached value */
451 u32 control2_register; /* cached value */
452 u32 creg_spdif;
453 u32 creg_spdif_stream;
454 int clock_source_locked;
455 char *card_name; /* digiface/multiface/rpm */
456 enum HDSP_IO_Type io_type; /* ditto, but for code use */
457 unsigned short firmware_rev;
458 unsigned short state; /* stores state bits */
459 const struct firmware *firmware;
460 u32 *fw_uploaded;
461 size_t period_bytes; /* guess what this is */
462 unsigned char max_channels;
463 unsigned char qs_in_channels; /* quad speed mode for H9632 */
464 unsigned char ds_in_channels;
465 unsigned char ss_in_channels; /* different for multiface/digiface */
466 unsigned char qs_out_channels;
467 unsigned char ds_out_channels;
468 unsigned char ss_out_channels;
469 u32 io_loopback; /* output loopback channel states*/
470
471 /* DMA buffers; those are copied instances from the original snd_dma_buf
472 * objects (which are managed via devres) for the address alignments
473 */
474 struct snd_dma_buffer capture_dma_buf;
475 struct snd_dma_buffer playback_dma_buf;
476 unsigned char *capture_buffer; /* suitably aligned address */
477 unsigned char *playback_buffer; /* suitably aligned address */
478
479 pid_t capture_pid;
480 pid_t playback_pid;
481 int running;
482 int system_sample_rate;
483 const signed char *channel_map;
484 int dev;
485 int irq;
486 unsigned long port;
487 void __iomem *iobase;
488 struct snd_card *card;
489 struct snd_pcm *pcm;
490 struct snd_hwdep *hwdep;
491 struct pci_dev *pci;
492 struct snd_kcontrol *spdif_ctl;
493 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
494 unsigned int dds_value; /* last value written to freq register */
495 };
496
497 /* These tables map the ALSA channels 1..N to the channels that we
498 need to use in order to find the relevant channel buffer. RME
499 refer to this kind of mapping as between "the ADAT channel and
500 the DMA channel." We index it using the logical audio channel,
501 and the value is the DMA channel (i.e. channel buffer number)
502 where the data for that channel can be read/written from/to.
503 */
504
505 static const signed char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
506 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
507 18, 19, 20, 21, 22, 23, 24, 25
508 };
509
510 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
511 /* Analog */
512 0, 1, 2, 3, 4, 5, 6, 7,
513 /* ADAT 2 */
514 16, 17, 18, 19, 20, 21, 22, 23,
515 /* SPDIF */
516 24, 25,
517 -1, -1, -1, -1, -1, -1, -1, -1
518 };
519
520 static const signed char channel_map_ds[HDSP_MAX_CHANNELS] = {
521 /* ADAT channels are remapped */
522 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
523 /* channels 12 and 13 are S/PDIF */
524 24, 25,
525 /* others don't exist */
526 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
527 };
528
529 static const signed char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
530 /* ADAT channels */
531 0, 1, 2, 3, 4, 5, 6, 7,
532 /* SPDIF */
533 8, 9,
534 /* Analog */
535 10, 11,
536 /* AO4S-192 and AI4S-192 extension boards */
537 12, 13, 14, 15,
538 /* others don't exist */
539 -1, -1, -1, -1, -1, -1, -1, -1,
540 -1, -1
541 };
542
543 static const signed char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
544 /* ADAT */
545 1, 3, 5, 7,
546 /* SPDIF */
547 8, 9,
548 /* Analog */
549 10, 11,
550 /* AO4S-192 and AI4S-192 extension boards */
551 12, 13, 14, 15,
552 /* others don't exist */
553 -1, -1, -1, -1, -1, -1, -1, -1,
554 -1, -1, -1, -1, -1, -1
555 };
556
557 static const signed char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
558 /* ADAT is disabled in this mode */
559 /* SPDIF */
560 8, 9,
561 /* Analog */
562 10, 11,
563 /* AO4S-192 and AI4S-192 extension boards */
564 12, 13, 14, 15,
565 /* others don't exist */
566 -1, -1, -1, -1, -1, -1, -1, -1,
567 -1, -1, -1, -1, -1, -1, -1, -1,
568 -1, -1
569 };
570
571 static struct snd_dma_buffer *
572 snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
573 {
574 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);
575 }
576
577 static const struct pci_device_id snd_hdsp_ids[] = {
578 {
579 .vendor = PCI_VENDOR_ID_XILINX,
580 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
581 .subvendor = PCI_ANY_ID,
582 .subdevice = PCI_ANY_ID,
583 }, /* RME Hammerfall-DSP */
584 { 0, },
585 };
586
587 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
588
589 /* prototypes */
590 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
591 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
592 static int snd_hdsp_enable_io (struct hdsp *hdsp);
593 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
594 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
595 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
596 static int hdsp_autosync_ref(struct hdsp *hdsp);
597 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
598 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
599
600 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
601 {
602 switch (hdsp->io_type) {
603 case Multiface:
604 case Digiface:
605 case RPM:
606 default:
607 if (hdsp->firmware_rev == 0xa)
608 return (64 * out) + (32 + (in));
609 else
610 return (52 * out) + (26 + (in));
611 case H9632:
612 return (32 * out) + (16 + (in));
613 case H9652:
614 return (52 * out) + (26 + (in));
615 }
616 }
617
618 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
619 {
620 switch (hdsp->io_type) {
621 case Multiface:
622 case Digiface:
623 case RPM:
624 default:
625 if (hdsp->firmware_rev == 0xa)
626 return (64 * out) + in;
627 else
628 return (52 * out) + in;
629 case H9632:
630 return (32 * out) + in;
631 case H9652:
632 return (52 * out) + in;
633 }
634 }
635
636 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
637 {
638 writel(val, hdsp->iobase + reg);
639 }
640
641 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
642 {
643 return readl (hdsp->iobase + reg);
644 }
645
646 static int hdsp_check_for_iobox (struct hdsp *hdsp)
647 {
648 int i;
649
650 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
651 for (i = 0; i < 500; i++) {
652 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
653 HDSP_ConfigError)) {
654 if (i) {
655 dev_dbg(hdsp->card->dev,
656 "IO box found after %d ms\n",
657 (20 * i));
658 }
659 return 0;
660 }
661 msleep(20);
662 }
663 dev_err(hdsp->card->dev, "no IO box connected!\n");
664 hdsp->state &= ~HDSP_FirmwareLoaded;
665 return -EIO;
666 }
667
668 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
669 unsigned int delay)
670 {
671 unsigned int i;
672
673 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
674 return 0;
675
676 for (i = 0; i != loops; ++i) {
677 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
678 msleep(delay);
679 else {
680 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
681 i * delay);
682 return 0;
683 }
684 }
685
686 dev_info(hdsp->card->dev, "no IO box connected!\n");
687 hdsp->state &= ~HDSP_FirmwareLoaded;
688 return -EIO;
689 }
690
691 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
692
693 int i;
694 unsigned long flags;
695 const u32 *cache;
696
697 if (hdsp->fw_uploaded)
698 cache = hdsp->fw_uploaded;
699 else {
700 if (!hdsp->firmware)
701 return -ENODEV;
702 cache = (u32 *)hdsp->firmware->data;
703 if (!cache)
704 return -ENODEV;
705 }
706
707 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
708
709 dev_info(hdsp->card->dev, "loading firmware\n");
710
711 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
712 hdsp_write (hdsp, HDSP_fifoData, 0);
713
714 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
715 dev_info(hdsp->card->dev,
716 "timeout waiting for download preparation\n");
717 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
718 return -EIO;
719 }
720
721 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
722
723 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
724 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
725 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
726 dev_info(hdsp->card->dev,
727 "timeout during firmware loading\n");
728 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
729 return -EIO;
730 }
731 }
732
733 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
734 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
735
736 ssleep(3);
737 #ifdef SNDRV_BIG_ENDIAN
738 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
739 #else
740 hdsp->control2_register = 0;
741 #endif
742 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
743 dev_info(hdsp->card->dev, "finished firmware loading\n");
744
745 }
746 if (hdsp->state & HDSP_InitializationComplete) {
747 dev_info(hdsp->card->dev,
748 "firmware loaded from cache, restoring defaults\n");
749 spin_lock_irqsave(&hdsp->lock, flags);
750 snd_hdsp_set_defaults(hdsp);
751 spin_unlock_irqrestore(&hdsp->lock, flags);
752 }
753
754 hdsp->state |= HDSP_FirmwareLoaded;
755
756 return 0;
757 }
758
759 static int hdsp_get_iobox_version (struct hdsp *hdsp)
760 {
761 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
762
763 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
764 hdsp_write(hdsp, HDSP_fifoData, 0);
765
766 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
767 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
768 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
769 }
770
771 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
772 hdsp_write (hdsp, HDSP_fifoData, 0);
773 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
774 goto set_multi;
775
776 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
777 hdsp_write(hdsp, HDSP_fifoData, 0);
778 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
779 hdsp->io_type = Digiface;
780 dev_info(hdsp->card->dev, "Digiface found\n");
781 return 0;
782 }
783
784 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
785 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
786 hdsp_write(hdsp, HDSP_fifoData, 0);
787 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
788 goto set_multi;
789
790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
792 hdsp_write(hdsp, HDSP_fifoData, 0);
793 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
794 goto set_multi;
795
796 hdsp->io_type = RPM;
797 dev_info(hdsp->card->dev, "RPM found\n");
798 return 0;
799 } else {
800 /* firmware was already loaded, get iobox type */
801 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
802 hdsp->io_type = RPM;
803 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
804 hdsp->io_type = Multiface;
805 else
806 hdsp->io_type = Digiface;
807 }
808 return 0;
809
810 set_multi:
811 hdsp->io_type = Multiface;
812 dev_info(hdsp->card->dev, "Multiface found\n");
813 return 0;
814 }
815
816
817 static int hdsp_request_fw_loader(struct hdsp *hdsp);
818
819 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
820 {
821 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
822 return 0;
823 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
824 hdsp->state &= ~HDSP_FirmwareLoaded;
825 if (! load_on_demand)
826 return -EIO;
827 dev_err(hdsp->card->dev, "firmware not present.\n");
828 /* try to load firmware */
829 if (! (hdsp->state & HDSP_FirmwareCached)) {
830 if (! hdsp_request_fw_loader(hdsp))
831 return 0;
832 dev_err(hdsp->card->dev,
833 "No firmware loaded nor cached, please upload firmware.\n");
834 return -EIO;
835 }
836 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
837 dev_err(hdsp->card->dev,
838 "Firmware loading from cache failed, please upload manually.\n");
839 return -EIO;
840 }
841 }
842 return 0;
843 }
844
845
846 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
847 {
848 int i;
849
850 /* the fifoStatus registers reports on how many words
851 are available in the command FIFO.
852 */
853
854 for (i = 0; i < timeout; i++) {
855
856 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
857 return 0;
858
859 /* not very friendly, but we only do this during a firmware
860 load and changing the mixer, so we just put up with it.
861 */
862
863 udelay (100);
864 }
865
866 dev_warn(hdsp->card->dev,
867 "wait for FIFO status <= %d failed after %d iterations\n",
868 count, timeout);
869 return -1;
870 }
871
872 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
873 {
874 if (addr >= HDSP_MATRIX_MIXER_SIZE)
875 return 0;
876
877 return hdsp->mixer_matrix[addr];
878 }
879
880 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
881 {
882 unsigned int ad;
883
884 if (addr >= HDSP_MATRIX_MIXER_SIZE)
885 return -1;
886
887 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
888
889 /* from martin bjornsen:
890
891 "You can only write dwords to the
892 mixer memory which contain two
893 mixer values in the low and high
894 word. So if you want to change
895 value 0 you have to read value 1
896 from the cache and write both to
897 the first dword in the mixer
898 memory."
899 */
900
901 if (hdsp->io_type == H9632 && addr >= 512)
902 return 0;
903
904 if (hdsp->io_type == H9652 && addr >= 1352)
905 return 0;
906
907 hdsp->mixer_matrix[addr] = data;
908
909
910 /* `addr' addresses a 16-bit wide address, but
911 the address space accessed via hdsp_write
912 uses byte offsets. put another way, addr
913 varies from 0 to 1351, but to access the
914 corresponding memory location, we need
915 to access 0 to 2703 ...
916 */
917 ad = addr/2;
918
919 hdsp_write (hdsp, 4096 + (ad*4),
920 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
921 hdsp->mixer_matrix[addr&0x7fe]);
922
923 return 0;
924
925 } else {
926
927 ad = (addr << 16) + data;
928
929 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
930 return -1;
931
932 hdsp_write (hdsp, HDSP_fifoData, ad);
933 hdsp->mixer_matrix[addr] = data;
934
935 }
936
937 return 0;
938 }
939
940 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
941 {
942 unsigned long flags;
943 int ret = 1;
944
945 spin_lock_irqsave(&hdsp->lock, flags);
946 if ((hdsp->playback_pid != hdsp->capture_pid) &&
947 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
948 ret = 0;
949 spin_unlock_irqrestore(&hdsp->lock, flags);
950 return ret;
951 }
952
953 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
954 {
955 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
956 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
957
958 /* For the 9632, the mask is different */
959 if (hdsp->io_type == H9632)
960 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
961
962 if (status & HDSP_SPDIFErrorFlag)
963 return 0;
964
965 switch (rate_bits) {
966 case HDSP_spdifFrequency32KHz: return 32000;
967 case HDSP_spdifFrequency44_1KHz: return 44100;
968 case HDSP_spdifFrequency48KHz: return 48000;
969 case HDSP_spdifFrequency64KHz: return 64000;
970 case HDSP_spdifFrequency88_2KHz: return 88200;
971 case HDSP_spdifFrequency96KHz: return 96000;
972 case HDSP_spdifFrequency128KHz:
973 if (hdsp->io_type == H9632) return 128000;
974 break;
975 case HDSP_spdifFrequency176_4KHz:
976 if (hdsp->io_type == H9632) return 176400;
977 break;
978 case HDSP_spdifFrequency192KHz:
979 if (hdsp->io_type == H9632) return 192000;
980 break;
981 default:
982 break;
983 }
984 dev_warn(hdsp->card->dev,
985 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
986 rate_bits, status);
987 return 0;
988 }
989
990 static int hdsp_external_sample_rate(struct hdsp *hdsp)
991 {
992 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
993 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
994
995 /* For the 9632 card, there seems to be no bit for indicating external
996 * sample rate greater than 96kHz. The card reports the corresponding
997 * single speed. So the best means seems to get spdif rate when
998 * autosync reference is spdif */
999 if (hdsp->io_type == H9632 &&
1000 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1001 return hdsp_spdif_sample_rate(hdsp);
1002
1003 switch (rate_bits) {
1004 case HDSP_systemFrequency32: return 32000;
1005 case HDSP_systemFrequency44_1: return 44100;
1006 case HDSP_systemFrequency48: return 48000;
1007 case HDSP_systemFrequency64: return 64000;
1008 case HDSP_systemFrequency88_2: return 88200;
1009 case HDSP_systemFrequency96: return 96000;
1010 default:
1011 return 0;
1012 }
1013 }
1014
1015 static void hdsp_compute_period_size(struct hdsp *hdsp)
1016 {
1017 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1018 }
1019
1020 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1021 {
1022 int position;
1023
1024 position = hdsp_read(hdsp, HDSP_statusRegister);
1025
1026 if (!hdsp->precise_ptr)
1027 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1028
1029 position &= HDSP_BufferPositionMask;
1030 position /= 4;
1031 position &= (hdsp->period_bytes/2) - 1;
1032 return position;
1033 }
1034
1035 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1036 {
1037 hdsp_write (hdsp, HDSP_resetPointer, 0);
1038 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1039 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1040 * requires (?) to write again DDS value after a reset pointer
1041 * (at least, it works like this) */
1042 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1043 }
1044
1045 static void hdsp_start_audio(struct hdsp *s)
1046 {
1047 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1048 hdsp_write(s, HDSP_controlRegister, s->control_register);
1049 }
1050
1051 static void hdsp_stop_audio(struct hdsp *s)
1052 {
1053 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1054 hdsp_write(s, HDSP_controlRegister, s->control_register);
1055 }
1056
1057 static void hdsp_silence_playback(struct hdsp *hdsp)
1058 {
1059 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1060 }
1061
1062 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1063 {
1064 int n;
1065
1066 spin_lock_irq(&s->lock);
1067
1068 frames >>= 7;
1069 n = 0;
1070 while (frames) {
1071 n++;
1072 frames >>= 1;
1073 }
1074
1075 s->control_register &= ~HDSP_LatencyMask;
1076 s->control_register |= hdsp_encode_latency(n);
1077
1078 hdsp_write(s, HDSP_controlRegister, s->control_register);
1079
1080 hdsp_compute_period_size(s);
1081
1082 spin_unlock_irq(&s->lock);
1083
1084 return 0;
1085 }
1086
1087 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1088 {
1089 u64 n;
1090
1091 if (rate >= 112000)
1092 rate /= 4;
1093 else if (rate >= 56000)
1094 rate /= 2;
1095
1096 n = DDS_NUMERATOR;
1097 n = div_u64(n, rate);
1098 /* n should be less than 2^32 for being written to FREQ register */
1099 snd_BUG_ON(n >> 32);
1100 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1101 value to write it after a reset */
1102 hdsp->dds_value = n;
1103 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1104 }
1105
1106 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1107 {
1108 int reject_if_open = 0;
1109 int current_rate;
1110 int rate_bits;
1111
1112 /* ASSUMPTION: hdsp->lock is either held, or
1113 there is no need for it (e.g. during module
1114 initialization).
1115 */
1116
1117 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1118 if (called_internally) {
1119 /* request from ctl or card initialization */
1120 dev_err(hdsp->card->dev,
1121 "device is not running as a clock master: cannot set sample rate.\n");
1122 return -1;
1123 } else {
1124 /* hw_param request while in AutoSync mode */
1125 int external_freq = hdsp_external_sample_rate(hdsp);
1126 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1127
1128 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1129 dev_info(hdsp->card->dev,
1130 "Detected ADAT in double speed mode\n");
1131 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1132 dev_info(hdsp->card->dev,
1133 "Detected ADAT in quad speed mode\n");
1134 else if (rate != external_freq) {
1135 dev_info(hdsp->card->dev,
1136 "No AutoSync source for requested rate\n");
1137 return -1;
1138 }
1139 }
1140 }
1141
1142 current_rate = hdsp->system_sample_rate;
1143
1144 /* Changing from a "single speed" to a "double speed" rate is
1145 not allowed if any substreams are open. This is because
1146 such a change causes a shift in the location of
1147 the DMA buffers and a reduction in the number of available
1148 buffers.
1149
1150 Note that a similar but essentially insoluble problem
1151 exists for externally-driven rate changes. All we can do
1152 is to flag rate changes in the read/write routines. */
1153
1154 if (rate > 96000 && hdsp->io_type != H9632)
1155 return -EINVAL;
1156
1157 switch (rate) {
1158 case 32000:
1159 if (current_rate > 48000)
1160 reject_if_open = 1;
1161 rate_bits = HDSP_Frequency32KHz;
1162 break;
1163 case 44100:
1164 if (current_rate > 48000)
1165 reject_if_open = 1;
1166 rate_bits = HDSP_Frequency44_1KHz;
1167 break;
1168 case 48000:
1169 if (current_rate > 48000)
1170 reject_if_open = 1;
1171 rate_bits = HDSP_Frequency48KHz;
1172 break;
1173 case 64000:
1174 if (current_rate <= 48000 || current_rate > 96000)
1175 reject_if_open = 1;
1176 rate_bits = HDSP_Frequency64KHz;
1177 break;
1178 case 88200:
1179 if (current_rate <= 48000 || current_rate > 96000)
1180 reject_if_open = 1;
1181 rate_bits = HDSP_Frequency88_2KHz;
1182 break;
1183 case 96000:
1184 if (current_rate <= 48000 || current_rate > 96000)
1185 reject_if_open = 1;
1186 rate_bits = HDSP_Frequency96KHz;
1187 break;
1188 case 128000:
1189 if (current_rate < 128000)
1190 reject_if_open = 1;
1191 rate_bits = HDSP_Frequency128KHz;
1192 break;
1193 case 176400:
1194 if (current_rate < 128000)
1195 reject_if_open = 1;
1196 rate_bits = HDSP_Frequency176_4KHz;
1197 break;
1198 case 192000:
1199 if (current_rate < 128000)
1200 reject_if_open = 1;
1201 rate_bits = HDSP_Frequency192KHz;
1202 break;
1203 default:
1204 return -EINVAL;
1205 }
1206
1207 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1208 dev_warn(hdsp->card->dev,
1209 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1210 hdsp->capture_pid,
1211 hdsp->playback_pid);
1212 return -EBUSY;
1213 }
1214
1215 hdsp->control_register &= ~HDSP_FrequencyMask;
1216 hdsp->control_register |= rate_bits;
1217 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1218
1219 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1220 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1221 hdsp_set_dds_value(hdsp, rate);
1222
1223 if (rate >= 128000) {
1224 hdsp->channel_map = channel_map_H9632_qs;
1225 } else if (rate > 48000) {
1226 if (hdsp->io_type == H9632)
1227 hdsp->channel_map = channel_map_H9632_ds;
1228 else
1229 hdsp->channel_map = channel_map_ds;
1230 } else {
1231 switch (hdsp->io_type) {
1232 case RPM:
1233 case Multiface:
1234 hdsp->channel_map = channel_map_mf_ss;
1235 break;
1236 case Digiface:
1237 case H9652:
1238 hdsp->channel_map = channel_map_df_ss;
1239 break;
1240 case H9632:
1241 hdsp->channel_map = channel_map_H9632_ss;
1242 break;
1243 default:
1244 /* should never happen */
1245 break;
1246 }
1247 }
1248
1249 hdsp->system_sample_rate = rate;
1250
1251 return 0;
1252 }
1253
1254 /*----------------------------------------------------------------------------
1255 MIDI
1256 ----------------------------------------------------------------------------*/
1257
1258 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1259 {
1260 /* the hardware already does the relevant bit-mask with 0xff */
1261 if (id)
1262 return hdsp_read(hdsp, HDSP_midiDataIn1);
1263 else
1264 return hdsp_read(hdsp, HDSP_midiDataIn0);
1265 }
1266
1267 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1268 {
1269 /* the hardware already does the relevant bit-mask with 0xff */
1270 if (id)
1271 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1272 else
1273 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1274 }
1275
1276 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1277 {
1278 if (id)
1279 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1280 else
1281 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1282 }
1283
1284 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1285 {
1286 int fifo_bytes_used;
1287
1288 if (id)
1289 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1290 else
1291 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1292
1293 if (fifo_bytes_used < 128)
1294 return 128 - fifo_bytes_used;
1295 else
1296 return 0;
1297 }
1298
1299 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1300 {
1301 while (snd_hdsp_midi_input_available (hdsp, id))
1302 snd_hdsp_midi_read_byte (hdsp, id);
1303 }
1304
1305 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1306 {
1307 unsigned long flags;
1308 int n_pending;
1309 int to_write;
1310 int i;
1311 unsigned char buf[128];
1312
1313 /* Output is not interrupt driven */
1314
1315 spin_lock_irqsave (&hmidi->lock, flags);
1316 if (hmidi->output) {
1317 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1318 n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);
1319 if (n_pending > 0) {
1320 if (n_pending > (int)sizeof (buf))
1321 n_pending = sizeof (buf);
1322
1323 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);
1324 if (to_write > 0) {
1325 for (i = 0; i < to_write; ++i)
1326 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1327 }
1328 }
1329 }
1330 }
1331 spin_unlock_irqrestore (&hmidi->lock, flags);
1332 return 0;
1333 }
1334
1335 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1336 {
1337 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1338 unsigned long flags;
1339 int n_pending;
1340 int i;
1341
1342 spin_lock_irqsave (&hmidi->lock, flags);
1343 n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);
1344 if (n_pending > 0) {
1345 if (hmidi->input) {
1346 if (n_pending > (int)sizeof (buf))
1347 n_pending = sizeof (buf);
1348 for (i = 0; i < n_pending; ++i)
1349 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1350 if (n_pending)
1351 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1352 } else {
1353 /* flush the MIDI input FIFO */
1354 while (--n_pending)
1355 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1356 }
1357 }
1358 hmidi->pending = 0;
1359 if (hmidi->id)
1360 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1361 else
1362 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1363 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1364 spin_unlock_irqrestore (&hmidi->lock, flags);
1365 return snd_hdsp_midi_output_write (hmidi);
1366 }
1367
1368 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1369 {
1370 struct hdsp *hdsp;
1371 struct hdsp_midi *hmidi;
1372 unsigned long flags;
1373 u32 ie;
1374
1375 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1376 hdsp = hmidi->hdsp;
1377 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1378 spin_lock_irqsave (&hdsp->lock, flags);
1379 if (up) {
1380 if (!(hdsp->control_register & ie)) {
1381 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1382 hdsp->control_register |= ie;
1383 }
1384 } else {
1385 hdsp->control_register &= ~ie;
1386 }
1387
1388 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1389 spin_unlock_irqrestore (&hdsp->lock, flags);
1390 }
1391
1392 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1393 {
1394 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1395 unsigned long flags;
1396
1397 snd_hdsp_midi_output_write(hmidi);
1398 spin_lock_irqsave (&hmidi->lock, flags);
1399
1400 /* this does not bump hmidi->istimer, because the
1401 kernel automatically removed the timer when it
1402 expired, and we are now adding it back, thus
1403 leaving istimer wherever it was set before.
1404 */
1405
1406 if (hmidi->istimer)
1407 mod_timer(&hmidi->timer, 1 + jiffies);
1408
1409 spin_unlock_irqrestore (&hmidi->lock, flags);
1410 }
1411
1412 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1413 {
1414 struct hdsp_midi *hmidi;
1415 unsigned long flags;
1416
1417 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1418 spin_lock_irqsave (&hmidi->lock, flags);
1419 if (up) {
1420 if (!hmidi->istimer) {
1421 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1422 0);
1423 mod_timer(&hmidi->timer, 1 + jiffies);
1424 hmidi->istimer++;
1425 }
1426 } else {
1427 if (hmidi->istimer && --hmidi->istimer <= 0)
1428 del_timer (&hmidi->timer);
1429 }
1430 spin_unlock_irqrestore (&hmidi->lock, flags);
1431 if (up)
1432 snd_hdsp_midi_output_write(hmidi);
1433 }
1434
1435 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1436 {
1437 struct hdsp_midi *hmidi;
1438
1439 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1440 spin_lock_irq (&hmidi->lock);
1441 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1442 hmidi->input = substream;
1443 spin_unlock_irq (&hmidi->lock);
1444
1445 return 0;
1446 }
1447
1448 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1449 {
1450 struct hdsp_midi *hmidi;
1451
1452 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1453 spin_lock_irq (&hmidi->lock);
1454 hmidi->output = substream;
1455 spin_unlock_irq (&hmidi->lock);
1456
1457 return 0;
1458 }
1459
1460 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1461 {
1462 struct hdsp_midi *hmidi;
1463
1464 snd_hdsp_midi_input_trigger (substream, 0);
1465
1466 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1467 spin_lock_irq (&hmidi->lock);
1468 hmidi->input = NULL;
1469 spin_unlock_irq (&hmidi->lock);
1470
1471 return 0;
1472 }
1473
1474 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1475 {
1476 struct hdsp_midi *hmidi;
1477
1478 snd_hdsp_midi_output_trigger (substream, 0);
1479
1480 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1481 spin_lock_irq (&hmidi->lock);
1482 hmidi->output = NULL;
1483 spin_unlock_irq (&hmidi->lock);
1484
1485 return 0;
1486 }
1487
1488 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1489 {
1490 .open = snd_hdsp_midi_output_open,
1491 .close = snd_hdsp_midi_output_close,
1492 .trigger = snd_hdsp_midi_output_trigger,
1493 };
1494
1495 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1496 {
1497 .open = snd_hdsp_midi_input_open,
1498 .close = snd_hdsp_midi_input_close,
1499 .trigger = snd_hdsp_midi_input_trigger,
1500 };
1501
1502 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1503 {
1504 char buf[40];
1505
1506 hdsp->midi[id].id = id;
1507 hdsp->midi[id].rmidi = NULL;
1508 hdsp->midi[id].input = NULL;
1509 hdsp->midi[id].output = NULL;
1510 hdsp->midi[id].hdsp = hdsp;
1511 hdsp->midi[id].istimer = 0;
1512 hdsp->midi[id].pending = 0;
1513 spin_lock_init (&hdsp->midi[id].lock);
1514
1515 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1516 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1517 return -1;
1518
1519 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1520 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1521
1522 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1523 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1524
1525 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1526 SNDRV_RAWMIDI_INFO_INPUT |
1527 SNDRV_RAWMIDI_INFO_DUPLEX;
1528
1529 return 0;
1530 }
1531
1532 /*-----------------------------------------------------------------------------
1533 Control Interface
1534 ----------------------------------------------------------------------------*/
1535
1536 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1537 {
1538 u32 val = 0;
1539 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1540 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1541 if (val & HDSP_SPDIFProfessional)
1542 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1543 else
1544 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1545 return val;
1546 }
1547
1548 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1549 {
1550 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1551 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1552 if (val & HDSP_SPDIFProfessional)
1553 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1554 else
1555 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1556 }
1557
1558 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1559 {
1560 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1561 uinfo->count = 1;
1562 return 0;
1563 }
1564
1565 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1566 {
1567 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1568
1569 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1570 return 0;
1571 }
1572
1573 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1574 {
1575 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1576 int change;
1577 u32 val;
1578
1579 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1580 spin_lock_irq(&hdsp->lock);
1581 change = val != hdsp->creg_spdif;
1582 hdsp->creg_spdif = val;
1583 spin_unlock_irq(&hdsp->lock);
1584 return change;
1585 }
1586
1587 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1588 {
1589 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1590 uinfo->count = 1;
1591 return 0;
1592 }
1593
1594 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1595 {
1596 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1597
1598 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1599 return 0;
1600 }
1601
1602 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1603 {
1604 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1605 int change;
1606 u32 val;
1607
1608 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1609 spin_lock_irq(&hdsp->lock);
1610 change = val != hdsp->creg_spdif_stream;
1611 hdsp->creg_spdif_stream = val;
1612 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1613 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1614 spin_unlock_irq(&hdsp->lock);
1615 return change;
1616 }
1617
1618 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1619 {
1620 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1621 uinfo->count = 1;
1622 return 0;
1623 }
1624
1625 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1626 {
1627 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1628 return 0;
1629 }
1630
1631 #define HDSP_SPDIF_IN(xname, xindex) \
1632 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1633 .name = xname, \
1634 .index = xindex, \
1635 .info = snd_hdsp_info_spdif_in, \
1636 .get = snd_hdsp_get_spdif_in, \
1637 .put = snd_hdsp_put_spdif_in }
1638
1639 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1640 {
1641 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1642 }
1643
1644 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1645 {
1646 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1647 hdsp->control_register |= hdsp_encode_spdif_in(in);
1648 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1649 return 0;
1650 }
1651
1652 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1653 {
1654 static const char * const texts[4] = {
1655 "Optical", "Coaxial", "Internal", "AES"
1656 };
1657 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1658
1659 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1660 texts);
1661 }
1662
1663 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1664 {
1665 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1666
1667 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1668 return 0;
1669 }
1670
1671 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1672 {
1673 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1674 int change;
1675 unsigned int val;
1676
1677 if (!snd_hdsp_use_is_exclusive(hdsp))
1678 return -EBUSY;
1679 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1680 spin_lock_irq(&hdsp->lock);
1681 change = val != hdsp_spdif_in(hdsp);
1682 if (change)
1683 hdsp_set_spdif_input(hdsp, val);
1684 spin_unlock_irq(&hdsp->lock);
1685 return change;
1686 }
1687
1688 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1689 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1690 .name = xname, \
1691 .private_value = xindex, \
1692 .info = snd_hdsp_info_toggle_setting, \
1693 .get = snd_hdsp_get_toggle_setting, \
1694 .put = snd_hdsp_put_toggle_setting \
1695 }
1696
1697 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1698 {
1699 return (hdsp->control_register & regmask) ? 1 : 0;
1700 }
1701
1702 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1703 {
1704 if (out)
1705 hdsp->control_register |= regmask;
1706 else
1707 hdsp->control_register &= ~regmask;
1708 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1709
1710 return 0;
1711 }
1712
1713 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1714
1715 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1716 struct snd_ctl_elem_value *ucontrol)
1717 {
1718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1719 u32 regmask = kcontrol->private_value;
1720
1721 spin_lock_irq(&hdsp->lock);
1722 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1723 spin_unlock_irq(&hdsp->lock);
1724 return 0;
1725 }
1726
1727 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1728 struct snd_ctl_elem_value *ucontrol)
1729 {
1730 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1731 u32 regmask = kcontrol->private_value;
1732 int change;
1733 unsigned int val;
1734
1735 if (!snd_hdsp_use_is_exclusive(hdsp))
1736 return -EBUSY;
1737 val = ucontrol->value.integer.value[0] & 1;
1738 spin_lock_irq(&hdsp->lock);
1739 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1740 if (change)
1741 hdsp_set_toggle_setting(hdsp, regmask, val);
1742 spin_unlock_irq(&hdsp->lock);
1743 return change;
1744 }
1745
1746 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1747 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1748 .name = xname, \
1749 .index = xindex, \
1750 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1751 .info = snd_hdsp_info_spdif_sample_rate, \
1752 .get = snd_hdsp_get_spdif_sample_rate \
1753 }
1754
1755 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1756 {
1757 static const char * const texts[] = {
1758 "32000", "44100", "48000", "64000", "88200", "96000",
1759 "None", "128000", "176400", "192000"
1760 };
1761 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1762
1763 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1764 texts);
1765 }
1766
1767 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1768 {
1769 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1770
1771 switch (hdsp_spdif_sample_rate(hdsp)) {
1772 case 32000:
1773 ucontrol->value.enumerated.item[0] = 0;
1774 break;
1775 case 44100:
1776 ucontrol->value.enumerated.item[0] = 1;
1777 break;
1778 case 48000:
1779 ucontrol->value.enumerated.item[0] = 2;
1780 break;
1781 case 64000:
1782 ucontrol->value.enumerated.item[0] = 3;
1783 break;
1784 case 88200:
1785 ucontrol->value.enumerated.item[0] = 4;
1786 break;
1787 case 96000:
1788 ucontrol->value.enumerated.item[0] = 5;
1789 break;
1790 case 128000:
1791 ucontrol->value.enumerated.item[0] = 7;
1792 break;
1793 case 176400:
1794 ucontrol->value.enumerated.item[0] = 8;
1795 break;
1796 case 192000:
1797 ucontrol->value.enumerated.item[0] = 9;
1798 break;
1799 default:
1800 ucontrol->value.enumerated.item[0] = 6;
1801 }
1802 return 0;
1803 }
1804
1805 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1806 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1807 .name = xname, \
1808 .index = xindex, \
1809 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1810 .info = snd_hdsp_info_system_sample_rate, \
1811 .get = snd_hdsp_get_system_sample_rate \
1812 }
1813
1814 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1815 {
1816 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1817 uinfo->count = 1;
1818 return 0;
1819 }
1820
1821 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1822 {
1823 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1824
1825 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1826 return 0;
1827 }
1828
1829 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1831 .name = xname, \
1832 .index = xindex, \
1833 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1834 .info = snd_hdsp_info_autosync_sample_rate, \
1835 .get = snd_hdsp_get_autosync_sample_rate \
1836 }
1837
1838 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1839 {
1840 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1841 static const char * const texts[] = {
1842 "32000", "44100", "48000", "64000", "88200", "96000",
1843 "None", "128000", "176400", "192000"
1844 };
1845
1846 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1847 texts);
1848 }
1849
1850 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1851 {
1852 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1853
1854 switch (hdsp_external_sample_rate(hdsp)) {
1855 case 32000:
1856 ucontrol->value.enumerated.item[0] = 0;
1857 break;
1858 case 44100:
1859 ucontrol->value.enumerated.item[0] = 1;
1860 break;
1861 case 48000:
1862 ucontrol->value.enumerated.item[0] = 2;
1863 break;
1864 case 64000:
1865 ucontrol->value.enumerated.item[0] = 3;
1866 break;
1867 case 88200:
1868 ucontrol->value.enumerated.item[0] = 4;
1869 break;
1870 case 96000:
1871 ucontrol->value.enumerated.item[0] = 5;
1872 break;
1873 case 128000:
1874 ucontrol->value.enumerated.item[0] = 7;
1875 break;
1876 case 176400:
1877 ucontrol->value.enumerated.item[0] = 8;
1878 break;
1879 case 192000:
1880 ucontrol->value.enumerated.item[0] = 9;
1881 break;
1882 default:
1883 ucontrol->value.enumerated.item[0] = 6;
1884 }
1885 return 0;
1886 }
1887
1888 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1889 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1890 .name = xname, \
1891 .index = xindex, \
1892 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1893 .info = snd_hdsp_info_system_clock_mode, \
1894 .get = snd_hdsp_get_system_clock_mode \
1895 }
1896
1897 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1898 {
1899 if (hdsp->control_register & HDSP_ClockModeMaster)
1900 return 0;
1901 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1902 return 0;
1903 return 1;
1904 }
1905
1906 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1907 {
1908 static const char * const texts[] = {"Master", "Slave" };
1909
1910 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1911 }
1912
1913 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1914 {
1915 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1916
1917 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1918 return 0;
1919 }
1920
1921 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1922 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1923 .name = xname, \
1924 .index = xindex, \
1925 .info = snd_hdsp_info_clock_source, \
1926 .get = snd_hdsp_get_clock_source, \
1927 .put = snd_hdsp_put_clock_source \
1928 }
1929
1930 static int hdsp_clock_source(struct hdsp *hdsp)
1931 {
1932 if (hdsp->control_register & HDSP_ClockModeMaster) {
1933 switch (hdsp->system_sample_rate) {
1934 case 32000:
1935 return 1;
1936 case 44100:
1937 return 2;
1938 case 48000:
1939 return 3;
1940 case 64000:
1941 return 4;
1942 case 88200:
1943 return 5;
1944 case 96000:
1945 return 6;
1946 case 128000:
1947 return 7;
1948 case 176400:
1949 return 8;
1950 case 192000:
1951 return 9;
1952 default:
1953 return 3;
1954 }
1955 } else {
1956 return 0;
1957 }
1958 }
1959
1960 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1961 {
1962 int rate;
1963 switch (mode) {
1964 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1965 if (hdsp_external_sample_rate(hdsp) != 0) {
1966 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1967 hdsp->control_register &= ~HDSP_ClockModeMaster;
1968 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1969 return 0;
1970 }
1971 }
1972 return -1;
1973 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1974 rate = 32000;
1975 break;
1976 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1977 rate = 44100;
1978 break;
1979 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1980 rate = 48000;
1981 break;
1982 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1983 rate = 64000;
1984 break;
1985 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1986 rate = 88200;
1987 break;
1988 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1989 rate = 96000;
1990 break;
1991 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1992 rate = 128000;
1993 break;
1994 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1995 rate = 176400;
1996 break;
1997 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
1998 rate = 192000;
1999 break;
2000 default:
2001 rate = 48000;
2002 }
2003 hdsp->control_register |= HDSP_ClockModeMaster;
2004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2005 hdsp_set_rate(hdsp, rate, 1);
2006 return 0;
2007 }
2008
2009 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2010 {
2011 static const char * const texts[] = {
2012 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2013 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2014 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2015 "Internal 192.0 KHz"
2016 };
2017 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2018
2019 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2020 texts);
2021 }
2022
2023 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2024 {
2025 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2026
2027 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2028 return 0;
2029 }
2030
2031 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2032 {
2033 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2034 int change;
2035 int val;
2036
2037 if (!snd_hdsp_use_is_exclusive(hdsp))
2038 return -EBUSY;
2039 val = ucontrol->value.enumerated.item[0];
2040 if (val < 0) val = 0;
2041 if (hdsp->io_type == H9632) {
2042 if (val > 9)
2043 val = 9;
2044 } else {
2045 if (val > 6)
2046 val = 6;
2047 }
2048 spin_lock_irq(&hdsp->lock);
2049 if (val != hdsp_clock_source(hdsp))
2050 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2051 else
2052 change = 0;
2053 spin_unlock_irq(&hdsp->lock);
2054 return change;
2055 }
2056
2057 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2058
2059 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2060 {
2061 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2062
2063 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2064 return 0;
2065 }
2066
2067 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2068 {
2069 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2070 int change;
2071
2072 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2073 if (change)
2074 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2075 return change;
2076 }
2077
2078 #define HDSP_DA_GAIN(xname, xindex) \
2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2080 .name = xname, \
2081 .index = xindex, \
2082 .info = snd_hdsp_info_da_gain, \
2083 .get = snd_hdsp_get_da_gain, \
2084 .put = snd_hdsp_put_da_gain \
2085 }
2086
2087 static int hdsp_da_gain(struct hdsp *hdsp)
2088 {
2089 switch (hdsp->control_register & HDSP_DAGainMask) {
2090 case HDSP_DAGainHighGain:
2091 return 0;
2092 case HDSP_DAGainPlus4dBu:
2093 return 1;
2094 case HDSP_DAGainMinus10dBV:
2095 return 2;
2096 default:
2097 return 1;
2098 }
2099 }
2100
2101 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2102 {
2103 hdsp->control_register &= ~HDSP_DAGainMask;
2104 switch (mode) {
2105 case 0:
2106 hdsp->control_register |= HDSP_DAGainHighGain;
2107 break;
2108 case 1:
2109 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2110 break;
2111 case 2:
2112 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2113 break;
2114 default:
2115 return -1;
2116
2117 }
2118 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2119 return 0;
2120 }
2121
2122 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2123 {
2124 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2125
2126 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2127 }
2128
2129 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2130 {
2131 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2132
2133 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2134 return 0;
2135 }
2136
2137 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2138 {
2139 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2140 int change;
2141 int val;
2142
2143 if (!snd_hdsp_use_is_exclusive(hdsp))
2144 return -EBUSY;
2145 val = ucontrol->value.enumerated.item[0];
2146 if (val < 0) val = 0;
2147 if (val > 2) val = 2;
2148 spin_lock_irq(&hdsp->lock);
2149 if (val != hdsp_da_gain(hdsp))
2150 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2151 else
2152 change = 0;
2153 spin_unlock_irq(&hdsp->lock);
2154 return change;
2155 }
2156
2157 #define HDSP_AD_GAIN(xname, xindex) \
2158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2159 .name = xname, \
2160 .index = xindex, \
2161 .info = snd_hdsp_info_ad_gain, \
2162 .get = snd_hdsp_get_ad_gain, \
2163 .put = snd_hdsp_put_ad_gain \
2164 }
2165
2166 static int hdsp_ad_gain(struct hdsp *hdsp)
2167 {
2168 switch (hdsp->control_register & HDSP_ADGainMask) {
2169 case HDSP_ADGainMinus10dBV:
2170 return 0;
2171 case HDSP_ADGainPlus4dBu:
2172 return 1;
2173 case HDSP_ADGainLowGain:
2174 return 2;
2175 default:
2176 return 1;
2177 }
2178 }
2179
2180 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2181 {
2182 hdsp->control_register &= ~HDSP_ADGainMask;
2183 switch (mode) {
2184 case 0:
2185 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2186 break;
2187 case 1:
2188 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2189 break;
2190 case 2:
2191 hdsp->control_register |= HDSP_ADGainLowGain;
2192 break;
2193 default:
2194 return -1;
2195
2196 }
2197 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2198 return 0;
2199 }
2200
2201 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2202 {
2203 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2204
2205 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2206 }
2207
2208 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2209 {
2210 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2211
2212 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2213 return 0;
2214 }
2215
2216 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2217 {
2218 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2219 int change;
2220 int val;
2221
2222 if (!snd_hdsp_use_is_exclusive(hdsp))
2223 return -EBUSY;
2224 val = ucontrol->value.enumerated.item[0];
2225 if (val < 0) val = 0;
2226 if (val > 2) val = 2;
2227 spin_lock_irq(&hdsp->lock);
2228 if (val != hdsp_ad_gain(hdsp))
2229 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2230 else
2231 change = 0;
2232 spin_unlock_irq(&hdsp->lock);
2233 return change;
2234 }
2235
2236 #define HDSP_PHONE_GAIN(xname, xindex) \
2237 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2238 .name = xname, \
2239 .index = xindex, \
2240 .info = snd_hdsp_info_phone_gain, \
2241 .get = snd_hdsp_get_phone_gain, \
2242 .put = snd_hdsp_put_phone_gain \
2243 }
2244
2245 static int hdsp_phone_gain(struct hdsp *hdsp)
2246 {
2247 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2248 case HDSP_PhoneGain0dB:
2249 return 0;
2250 case HDSP_PhoneGainMinus6dB:
2251 return 1;
2252 case HDSP_PhoneGainMinus12dB:
2253 return 2;
2254 default:
2255 return 0;
2256 }
2257 }
2258
2259 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2260 {
2261 hdsp->control_register &= ~HDSP_PhoneGainMask;
2262 switch (mode) {
2263 case 0:
2264 hdsp->control_register |= HDSP_PhoneGain0dB;
2265 break;
2266 case 1:
2267 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2268 break;
2269 case 2:
2270 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2271 break;
2272 default:
2273 return -1;
2274
2275 }
2276 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2277 return 0;
2278 }
2279
2280 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2281 {
2282 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2283
2284 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2285 }
2286
2287 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2288 {
2289 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2290
2291 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2292 return 0;
2293 }
2294
2295 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2296 {
2297 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2298 int change;
2299 int val;
2300
2301 if (!snd_hdsp_use_is_exclusive(hdsp))
2302 return -EBUSY;
2303 val = ucontrol->value.enumerated.item[0];
2304 if (val < 0) val = 0;
2305 if (val > 2) val = 2;
2306 spin_lock_irq(&hdsp->lock);
2307 if (val != hdsp_phone_gain(hdsp))
2308 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2309 else
2310 change = 0;
2311 spin_unlock_irq(&hdsp->lock);
2312 return change;
2313 }
2314
2315 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2316 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2317 .name = xname, \
2318 .index = xindex, \
2319 .info = snd_hdsp_info_pref_sync_ref, \
2320 .get = snd_hdsp_get_pref_sync_ref, \
2321 .put = snd_hdsp_put_pref_sync_ref \
2322 }
2323
2324 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2325 {
2326 /* Notice that this looks at the requested sync source,
2327 not the one actually in use.
2328 */
2329
2330 switch (hdsp->control_register & HDSP_SyncRefMask) {
2331 case HDSP_SyncRef_ADAT1:
2332 return HDSP_SYNC_FROM_ADAT1;
2333 case HDSP_SyncRef_ADAT2:
2334 return HDSP_SYNC_FROM_ADAT2;
2335 case HDSP_SyncRef_ADAT3:
2336 return HDSP_SYNC_FROM_ADAT3;
2337 case HDSP_SyncRef_SPDIF:
2338 return HDSP_SYNC_FROM_SPDIF;
2339 case HDSP_SyncRef_WORD:
2340 return HDSP_SYNC_FROM_WORD;
2341 case HDSP_SyncRef_ADAT_SYNC:
2342 return HDSP_SYNC_FROM_ADAT_SYNC;
2343 default:
2344 return HDSP_SYNC_FROM_WORD;
2345 }
2346 return 0;
2347 }
2348
2349 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2350 {
2351 hdsp->control_register &= ~HDSP_SyncRefMask;
2352 switch (pref) {
2353 case HDSP_SYNC_FROM_ADAT1:
2354 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2355 break;
2356 case HDSP_SYNC_FROM_ADAT2:
2357 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2358 break;
2359 case HDSP_SYNC_FROM_ADAT3:
2360 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2361 break;
2362 case HDSP_SYNC_FROM_SPDIF:
2363 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2364 break;
2365 case HDSP_SYNC_FROM_WORD:
2366 hdsp->control_register |= HDSP_SyncRef_WORD;
2367 break;
2368 case HDSP_SYNC_FROM_ADAT_SYNC:
2369 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2370 break;
2371 default:
2372 return -1;
2373 }
2374 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2375 return 0;
2376 }
2377
2378 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2379 {
2380 static const char * const texts[] = {
2381 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2382 };
2383 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2384 int num_items;
2385
2386 switch (hdsp->io_type) {
2387 case Digiface:
2388 case H9652:
2389 num_items = 6;
2390 break;
2391 case Multiface:
2392 num_items = 4;
2393 break;
2394 case H9632:
2395 num_items = 3;
2396 break;
2397 default:
2398 return -EINVAL;
2399 }
2400
2401 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2402 }
2403
2404 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2405 {
2406 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2407
2408 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2409 return 0;
2410 }
2411
2412 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2413 {
2414 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2415 int change, max;
2416 unsigned int val;
2417
2418 if (!snd_hdsp_use_is_exclusive(hdsp))
2419 return -EBUSY;
2420
2421 switch (hdsp->io_type) {
2422 case Digiface:
2423 case H9652:
2424 max = 6;
2425 break;
2426 case Multiface:
2427 max = 4;
2428 break;
2429 case H9632:
2430 max = 3;
2431 break;
2432 default:
2433 return -EIO;
2434 }
2435
2436 val = ucontrol->value.enumerated.item[0] % max;
2437 spin_lock_irq(&hdsp->lock);
2438 change = (int)val != hdsp_pref_sync_ref(hdsp);
2439 hdsp_set_pref_sync_ref(hdsp, val);
2440 spin_unlock_irq(&hdsp->lock);
2441 return change;
2442 }
2443
2444 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2445 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2446 .name = xname, \
2447 .index = xindex, \
2448 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2449 .info = snd_hdsp_info_autosync_ref, \
2450 .get = snd_hdsp_get_autosync_ref, \
2451 }
2452
2453 static int hdsp_autosync_ref(struct hdsp *hdsp)
2454 {
2455 /* This looks at the autosync selected sync reference */
2456 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2457
2458 switch (status2 & HDSP_SelSyncRefMask) {
2459 case HDSP_SelSyncRef_WORD:
2460 return HDSP_AUTOSYNC_FROM_WORD;
2461 case HDSP_SelSyncRef_ADAT_SYNC:
2462 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2463 case HDSP_SelSyncRef_SPDIF:
2464 return HDSP_AUTOSYNC_FROM_SPDIF;
2465 case HDSP_SelSyncRefMask:
2466 return HDSP_AUTOSYNC_FROM_NONE;
2467 case HDSP_SelSyncRef_ADAT1:
2468 return HDSP_AUTOSYNC_FROM_ADAT1;
2469 case HDSP_SelSyncRef_ADAT2:
2470 return HDSP_AUTOSYNC_FROM_ADAT2;
2471 case HDSP_SelSyncRef_ADAT3:
2472 return HDSP_AUTOSYNC_FROM_ADAT3;
2473 default:
2474 return HDSP_AUTOSYNC_FROM_WORD;
2475 }
2476 return 0;
2477 }
2478
2479 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2480 {
2481 static const char * const texts[] = {
2482 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2483 };
2484
2485 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2486 }
2487
2488 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2489 {
2490 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2491
2492 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2493 return 0;
2494 }
2495
2496 #define HDSP_PRECISE_POINTER(xname, xindex) \
2497 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2498 .name = xname, \
2499 .index = xindex, \
2500 .info = snd_hdsp_info_precise_pointer, \
2501 .get = snd_hdsp_get_precise_pointer, \
2502 .put = snd_hdsp_put_precise_pointer \
2503 }
2504
2505 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2506 {
2507 if (precise)
2508 hdsp->precise_ptr = 1;
2509 else
2510 hdsp->precise_ptr = 0;
2511 return 0;
2512 }
2513
2514 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2515
2516 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2517 {
2518 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2519
2520 spin_lock_irq(&hdsp->lock);
2521 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2522 spin_unlock_irq(&hdsp->lock);
2523 return 0;
2524 }
2525
2526 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2527 {
2528 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2529 int change;
2530 unsigned int val;
2531
2532 if (!snd_hdsp_use_is_exclusive(hdsp))
2533 return -EBUSY;
2534 val = ucontrol->value.integer.value[0] & 1;
2535 spin_lock_irq(&hdsp->lock);
2536 change = (int)val != hdsp->precise_ptr;
2537 hdsp_set_precise_pointer(hdsp, val);
2538 spin_unlock_irq(&hdsp->lock);
2539 return change;
2540 }
2541
2542 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2543 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2544 .name = xname, \
2545 .index = xindex, \
2546 .info = snd_hdsp_info_use_midi_work, \
2547 .get = snd_hdsp_get_use_midi_work, \
2548 .put = snd_hdsp_put_use_midi_work \
2549 }
2550
2551 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2552 {
2553 if (use_work)
2554 hdsp->use_midi_work = 1;
2555 else
2556 hdsp->use_midi_work = 0;
2557 return 0;
2558 }
2559
2560 #define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info
2561
2562 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2563 {
2564 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2565
2566 spin_lock_irq(&hdsp->lock);
2567 ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2568 spin_unlock_irq(&hdsp->lock);
2569 return 0;
2570 }
2571
2572 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2573 {
2574 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2575 int change;
2576 unsigned int val;
2577
2578 if (!snd_hdsp_use_is_exclusive(hdsp))
2579 return -EBUSY;
2580 val = ucontrol->value.integer.value[0] & 1;
2581 spin_lock_irq(&hdsp->lock);
2582 change = (int)val != hdsp->use_midi_work;
2583 hdsp_set_use_midi_work(hdsp, val);
2584 spin_unlock_irq(&hdsp->lock);
2585 return change;
2586 }
2587
2588 #define HDSP_MIXER(xname, xindex) \
2589 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2590 .name = xname, \
2591 .index = xindex, \
2592 .device = 0, \
2593 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2594 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2595 .info = snd_hdsp_info_mixer, \
2596 .get = snd_hdsp_get_mixer, \
2597 .put = snd_hdsp_put_mixer \
2598 }
2599
2600 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2601 {
2602 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2603 uinfo->count = 3;
2604 uinfo->value.integer.min = 0;
2605 uinfo->value.integer.max = 65536;
2606 uinfo->value.integer.step = 1;
2607 return 0;
2608 }
2609
2610 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2611 {
2612 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2613 int source;
2614 int destination;
2615 int addr;
2616
2617 source = ucontrol->value.integer.value[0];
2618 destination = ucontrol->value.integer.value[1];
2619
2620 if (source >= hdsp->max_channels)
2621 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2622 else
2623 addr = hdsp_input_to_output_key(hdsp,source, destination);
2624
2625 spin_lock_irq(&hdsp->lock);
2626 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2627 spin_unlock_irq(&hdsp->lock);
2628 return 0;
2629 }
2630
2631 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2632 {
2633 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2634 int change;
2635 int source;
2636 int destination;
2637 int gain;
2638 int addr;
2639
2640 if (!snd_hdsp_use_is_exclusive(hdsp))
2641 return -EBUSY;
2642
2643 source = ucontrol->value.integer.value[0];
2644 destination = ucontrol->value.integer.value[1];
2645
2646 if (source >= hdsp->max_channels)
2647 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2648 else
2649 addr = hdsp_input_to_output_key(hdsp,source, destination);
2650
2651 gain = ucontrol->value.integer.value[2];
2652
2653 spin_lock_irq(&hdsp->lock);
2654 change = gain != hdsp_read_gain(hdsp, addr);
2655 if (change)
2656 hdsp_write_gain(hdsp, addr, gain);
2657 spin_unlock_irq(&hdsp->lock);
2658 return change;
2659 }
2660
2661 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2662 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2663 .name = xname, \
2664 .index = xindex, \
2665 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2666 .info = snd_hdsp_info_sync_check, \
2667 .get = snd_hdsp_get_wc_sync_check \
2668 }
2669
2670 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2671 {
2672 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2673
2674 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2675 }
2676
2677 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2678 {
2679 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2680 if (status2 & HDSP_wc_lock) {
2681 if (status2 & HDSP_wc_sync)
2682 return 2;
2683 else
2684 return 1;
2685 } else
2686 return 0;
2687 return 0;
2688 }
2689
2690 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2691 {
2692 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2693
2694 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2695 return 0;
2696 }
2697
2698 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2699 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2700 .name = xname, \
2701 .index = xindex, \
2702 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2703 .info = snd_hdsp_info_sync_check, \
2704 .get = snd_hdsp_get_spdif_sync_check \
2705 }
2706
2707 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2708 {
2709 int status = hdsp_read(hdsp, HDSP_statusRegister);
2710 if (status & HDSP_SPDIFErrorFlag)
2711 return 0;
2712 else {
2713 if (status & HDSP_SPDIFSync)
2714 return 2;
2715 else
2716 return 1;
2717 }
2718 return 0;
2719 }
2720
2721 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2722 {
2723 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2724
2725 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2726 return 0;
2727 }
2728
2729 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2730 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2731 .name = xname, \
2732 .index = xindex, \
2733 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2734 .info = snd_hdsp_info_sync_check, \
2735 .get = snd_hdsp_get_adatsync_sync_check \
2736 }
2737
2738 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2739 {
2740 int status = hdsp_read(hdsp, HDSP_statusRegister);
2741 if (status & HDSP_TimecodeLock) {
2742 if (status & HDSP_TimecodeSync)
2743 return 2;
2744 else
2745 return 1;
2746 } else
2747 return 0;
2748 }
2749
2750 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2751 {
2752 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2753
2754 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2755 return 0;
2756 }
2757
2758 #define HDSP_ADAT_SYNC_CHECK \
2759 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2760 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2761 .info = snd_hdsp_info_sync_check, \
2762 .get = snd_hdsp_get_adat_sync_check \
2763 }
2764
2765 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2766 {
2767 int status = hdsp_read(hdsp, HDSP_statusRegister);
2768
2769 if (status & (HDSP_Lock0>>idx)) {
2770 if (status & (HDSP_Sync0>>idx))
2771 return 2;
2772 else
2773 return 1;
2774 } else
2775 return 0;
2776 }
2777
2778 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2779 {
2780 int offset;
2781 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2782
2783 offset = ucontrol->id.index - 1;
2784 if (snd_BUG_ON(offset < 0))
2785 return -EINVAL;
2786
2787 switch (hdsp->io_type) {
2788 case Digiface:
2789 case H9652:
2790 if (offset >= 3)
2791 return -EINVAL;
2792 break;
2793 case Multiface:
2794 case H9632:
2795 if (offset >= 1)
2796 return -EINVAL;
2797 break;
2798 default:
2799 return -EIO;
2800 }
2801
2802 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2803 return 0;
2804 }
2805
2806 #define HDSP_DDS_OFFSET(xname, xindex) \
2807 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2808 .name = xname, \
2809 .index = xindex, \
2810 .info = snd_hdsp_info_dds_offset, \
2811 .get = snd_hdsp_get_dds_offset, \
2812 .put = snd_hdsp_put_dds_offset \
2813 }
2814
2815 static int hdsp_dds_offset(struct hdsp *hdsp)
2816 {
2817 u64 n;
2818 unsigned int dds_value = hdsp->dds_value;
2819 int system_sample_rate = hdsp->system_sample_rate;
2820
2821 if (!dds_value)
2822 return 0;
2823
2824 n = DDS_NUMERATOR;
2825 /*
2826 * dds_value = n / rate
2827 * rate = n / dds_value
2828 */
2829 n = div_u64(n, dds_value);
2830 if (system_sample_rate >= 112000)
2831 n *= 4;
2832 else if (system_sample_rate >= 56000)
2833 n *= 2;
2834 return ((int)n) - system_sample_rate;
2835 }
2836
2837 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2838 {
2839 int rate = hdsp->system_sample_rate + offset_hz;
2840 hdsp_set_dds_value(hdsp, rate);
2841 return 0;
2842 }
2843
2844 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2845 {
2846 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2847 uinfo->count = 1;
2848 uinfo->value.integer.min = -5000;
2849 uinfo->value.integer.max = 5000;
2850 return 0;
2851 }
2852
2853 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2854 {
2855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2856
2857 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2858 return 0;
2859 }
2860
2861 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2862 {
2863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2864 int change;
2865 int val;
2866
2867 if (!snd_hdsp_use_is_exclusive(hdsp))
2868 return -EBUSY;
2869 val = ucontrol->value.integer.value[0];
2870 spin_lock_irq(&hdsp->lock);
2871 if (val != hdsp_dds_offset(hdsp))
2872 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2873 else
2874 change = 0;
2875 spin_unlock_irq(&hdsp->lock);
2876 return change;
2877 }
2878
2879 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2880 HDSP_DA_GAIN("DA Gain", 0),
2881 HDSP_AD_GAIN("AD Gain", 0),
2882 HDSP_PHONE_GAIN("Phones Gain", 0),
2883 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2884 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2885 };
2886
2887 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2888 {
2889 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2890 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2891 .info = snd_hdsp_control_spdif_info,
2892 .get = snd_hdsp_control_spdif_get,
2893 .put = snd_hdsp_control_spdif_put,
2894 },
2895 {
2896 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2897 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2898 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2899 .info = snd_hdsp_control_spdif_stream_info,
2900 .get = snd_hdsp_control_spdif_stream_get,
2901 .put = snd_hdsp_control_spdif_stream_put,
2902 },
2903 {
2904 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2905 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2906 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2907 .info = snd_hdsp_control_spdif_mask_info,
2908 .get = snd_hdsp_control_spdif_mask_get,
2909 .private_value = IEC958_AES0_NONAUDIO |
2910 IEC958_AES0_PROFESSIONAL |
2911 IEC958_AES0_CON_EMPHASIS,
2912 },
2913 {
2914 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2915 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2916 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2917 .info = snd_hdsp_control_spdif_mask_info,
2918 .get = snd_hdsp_control_spdif_mask_get,
2919 .private_value = IEC958_AES0_NONAUDIO |
2920 IEC958_AES0_PROFESSIONAL |
2921 IEC958_AES0_PRO_EMPHASIS,
2922 },
2923 HDSP_MIXER("Mixer", 0),
2924 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2925 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2926 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2927 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2928 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2929 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2930 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2931 {
2932 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2933 .name = "Sample Clock Source Locking",
2934 .info = snd_hdsp_info_clock_source_lock,
2935 .get = snd_hdsp_get_clock_source_lock,
2936 .put = snd_hdsp_put_clock_source_lock,
2937 },
2938 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2939 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2940 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2941 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2942 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2943 /* 'External Rate' complies with the alsa control naming scheme */
2944 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2945 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2946 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2947 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2948 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2949 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2950 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2951 };
2952
2953
2954 static int hdsp_rpm_input12(struct hdsp *hdsp)
2955 {
2956 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2957 case HDSP_RPM_Inp12_Phon_6dB:
2958 return 0;
2959 case HDSP_RPM_Inp12_Phon_n6dB:
2960 return 2;
2961 case HDSP_RPM_Inp12_Line_0dB:
2962 return 3;
2963 case HDSP_RPM_Inp12_Line_n6dB:
2964 return 4;
2965 }
2966 return 1;
2967 }
2968
2969
2970 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2971 {
2972 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2973
2974 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2975 return 0;
2976 }
2977
2978
2979 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2980 {
2981 hdsp->control_register &= ~HDSP_RPM_Inp12;
2982 switch (mode) {
2983 case 0:
2984 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2985 break;
2986 case 1:
2987 break;
2988 case 2:
2989 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2990 break;
2991 case 3:
2992 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2993 break;
2994 case 4:
2995 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2996 break;
2997 default:
2998 return -1;
2999 }
3000
3001 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3002 return 0;
3003 }
3004
3005
3006 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3007 {
3008 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3009 int change;
3010 int val;
3011
3012 if (!snd_hdsp_use_is_exclusive(hdsp))
3013 return -EBUSY;
3014 val = ucontrol->value.enumerated.item[0];
3015 if (val < 0)
3016 val = 0;
3017 if (val > 4)
3018 val = 4;
3019 spin_lock_irq(&hdsp->lock);
3020 if (val != hdsp_rpm_input12(hdsp))
3021 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3022 else
3023 change = 0;
3024 spin_unlock_irq(&hdsp->lock);
3025 return change;
3026 }
3027
3028
3029 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3030 {
3031 static const char * const texts[] = {
3032 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3033 };
3034
3035 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3036 }
3037
3038
3039 static int hdsp_rpm_input34(struct hdsp *hdsp)
3040 {
3041 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3042 case HDSP_RPM_Inp34_Phon_6dB:
3043 return 0;
3044 case HDSP_RPM_Inp34_Phon_n6dB:
3045 return 2;
3046 case HDSP_RPM_Inp34_Line_0dB:
3047 return 3;
3048 case HDSP_RPM_Inp34_Line_n6dB:
3049 return 4;
3050 }
3051 return 1;
3052 }
3053
3054
3055 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3056 {
3057 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3058
3059 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3060 return 0;
3061 }
3062
3063
3064 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3065 {
3066 hdsp->control_register &= ~HDSP_RPM_Inp34;
3067 switch (mode) {
3068 case 0:
3069 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3070 break;
3071 case 1:
3072 break;
3073 case 2:
3074 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3075 break;
3076 case 3:
3077 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3078 break;
3079 case 4:
3080 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3081 break;
3082 default:
3083 return -1;
3084 }
3085
3086 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3087 return 0;
3088 }
3089
3090
3091 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3092 {
3093 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3094 int change;
3095 int val;
3096
3097 if (!snd_hdsp_use_is_exclusive(hdsp))
3098 return -EBUSY;
3099 val = ucontrol->value.enumerated.item[0];
3100 if (val < 0)
3101 val = 0;
3102 if (val > 4)
3103 val = 4;
3104 spin_lock_irq(&hdsp->lock);
3105 if (val != hdsp_rpm_input34(hdsp))
3106 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3107 else
3108 change = 0;
3109 spin_unlock_irq(&hdsp->lock);
3110 return change;
3111 }
3112
3113
3114 /* RPM Bypass switch */
3115 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3116 {
3117 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3118 }
3119
3120
3121 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3122 {
3123 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3124
3125 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3126 return 0;
3127 }
3128
3129
3130 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3131 {
3132 if (on)
3133 hdsp->control_register |= HDSP_RPM_Bypass;
3134 else
3135 hdsp->control_register &= ~HDSP_RPM_Bypass;
3136 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3137 return 0;
3138 }
3139
3140
3141 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3142 {
3143 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3144 int change;
3145 unsigned int val;
3146
3147 if (!snd_hdsp_use_is_exclusive(hdsp))
3148 return -EBUSY;
3149 val = ucontrol->value.integer.value[0] & 1;
3150 spin_lock_irq(&hdsp->lock);
3151 change = (int)val != hdsp_rpm_bypass(hdsp);
3152 hdsp_set_rpm_bypass(hdsp, val);
3153 spin_unlock_irq(&hdsp->lock);
3154 return change;
3155 }
3156
3157
3158 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3159 {
3160 static const char * const texts[] = {"On", "Off"};
3161
3162 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3163 }
3164
3165
3166 /* RPM Disconnect switch */
3167 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3168 {
3169 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3170 }
3171
3172
3173 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3174 {
3175 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3176
3177 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3178 return 0;
3179 }
3180
3181
3182 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3183 {
3184 if (on)
3185 hdsp->control_register |= HDSP_RPM_Disconnect;
3186 else
3187 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3188 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3189 return 0;
3190 }
3191
3192
3193 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3194 {
3195 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3196 int change;
3197 unsigned int val;
3198
3199 if (!snd_hdsp_use_is_exclusive(hdsp))
3200 return -EBUSY;
3201 val = ucontrol->value.integer.value[0] & 1;
3202 spin_lock_irq(&hdsp->lock);
3203 change = (int)val != hdsp_rpm_disconnect(hdsp);
3204 hdsp_set_rpm_disconnect(hdsp, val);
3205 spin_unlock_irq(&hdsp->lock);
3206 return change;
3207 }
3208
3209 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3210 {
3211 static const char * const texts[] = {"On", "Off"};
3212
3213 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3214 }
3215
3216 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3217 {
3218 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3219 .name = "RPM Bypass",
3220 .get = snd_hdsp_get_rpm_bypass,
3221 .put = snd_hdsp_put_rpm_bypass,
3222 .info = snd_hdsp_info_rpm_bypass
3223 },
3224 {
3225 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3226 .name = "RPM Disconnect",
3227 .get = snd_hdsp_get_rpm_disconnect,
3228 .put = snd_hdsp_put_rpm_disconnect,
3229 .info = snd_hdsp_info_rpm_disconnect
3230 },
3231 {
3232 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3233 .name = "Input 1/2",
3234 .get = snd_hdsp_get_rpm_input12,
3235 .put = snd_hdsp_put_rpm_input12,
3236 .info = snd_hdsp_info_rpm_input
3237 },
3238 {
3239 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3240 .name = "Input 3/4",
3241 .get = snd_hdsp_get_rpm_input34,
3242 .put = snd_hdsp_put_rpm_input34,
3243 .info = snd_hdsp_info_rpm_input
3244 },
3245 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3246 HDSP_MIXER("Mixer", 0)
3247 };
3248
3249 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3250 HDSP_TOGGLE_SETTING("Analog Extension Board",
3251 HDSP_AnalogExtensionBoard);
3252 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3253
3254
3255 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3256 {
3257 return hdsp->io_loopback & (1 << channel);
3258 }
3259
3260 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3261 {
3262 if (hdsp_loopback_get(hdsp, channel) == enable)
3263 return 0;
3264
3265 hdsp->io_loopback ^= (1 << channel);
3266
3267 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3268
3269 return 1;
3270 }
3271
3272 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3273 struct snd_ctl_elem_value *const ucontrol)
3274 {
3275 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3276 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3277
3278 if (channel >= hdsp->max_channels)
3279 return -ENOENT;
3280
3281 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3282
3283 return 0;
3284 }
3285
3286 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3287 struct snd_ctl_elem_value *const ucontrol)
3288 {
3289 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3290 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3291 const bool enable = ucontrol->value.integer.value[0] & 1;
3292
3293 if (channel >= hdsp->max_channels)
3294 return -ENOENT;
3295
3296 return hdsp_loopback_set(hdsp, channel, enable);
3297 }
3298
3299 static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3300 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3301 .name = "Output Loopback",
3302 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3303 .info = snd_ctl_boolean_mono_info,
3304 .get = snd_hdsp_loopback_get,
3305 .put = snd_hdsp_loopback_put
3306 };
3307
3308 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3309 {
3310 unsigned int idx;
3311 int err;
3312 struct snd_kcontrol *kctl;
3313
3314 if (hdsp->io_type == RPM) {
3315 /* RPM Bypass, Disconnect and Input switches */
3316 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3317 err = snd_ctl_add(card, snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3318 if (err < 0)
3319 return err;
3320 }
3321 return 0;
3322 }
3323
3324 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3325 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp);
3326 err = snd_ctl_add(card, kctl);
3327 if (err < 0)
3328 return err;
3329 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3330 hdsp->spdif_ctl = kctl;
3331 }
3332
3333 /* ADAT SyncCheck status */
3334 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3335 snd_hdsp_adat_sync_check.index = 1;
3336 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3337 err = snd_ctl_add(card, kctl);
3338 if (err < 0)
3339 return err;
3340 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3341 for (idx = 1; idx < 3; ++idx) {
3342 snd_hdsp_adat_sync_check.index = idx+1;
3343 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3344 err = snd_ctl_add(card, kctl);
3345 if (err < 0)
3346 return err;
3347 }
3348 }
3349
3350 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3351 if (hdsp->io_type == H9632) {
3352 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3353 kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp);
3354 err = snd_ctl_add(card, kctl);
3355 if (err < 0)
3356 return err;
3357 }
3358 }
3359
3360 /* Output loopback controls for H9632 cards */
3361 if (hdsp->io_type == H9632) {
3362 snd_hdsp_loopback_control.count = hdsp->max_channels;
3363 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3364 if (kctl == NULL)
3365 return -ENOMEM;
3366 err = snd_ctl_add(card, kctl);
3367 if (err < 0)
3368 return err;
3369 }
3370
3371 /* AEB control for H96xx card */
3372 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3373 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp);
3374 err = snd_ctl_add(card, kctl);
3375 if (err < 0)
3376 return err;
3377 }
3378
3379 return 0;
3380 }
3381
3382 /*------------------------------------------------------------
3383 /proc interface
3384 ------------------------------------------------------------*/
3385
3386 static void
3387 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3388 {
3389 struct hdsp *hdsp = entry->private_data;
3390 unsigned int status;
3391 unsigned int status2;
3392 char *pref_sync_ref;
3393 char *autosync_ref;
3394 char *system_clock_mode;
3395 char *clock_source;
3396 int x;
3397
3398 status = hdsp_read(hdsp, HDSP_statusRegister);
3399 status2 = hdsp_read(hdsp, HDSP_status2Register);
3400
3401 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3402 hdsp->card->number + 1);
3403 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3404 hdsp->capture_buffer, hdsp->playback_buffer);
3405 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3406 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3407 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3408 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3409 hdsp->control2_register);
3410 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3411 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3412
3413 if (hdsp_check_for_iobox(hdsp)) {
3414 snd_iprintf(buffer, "No I/O box connected.\n"
3415 "Please connect one and upload firmware.\n");
3416 return;
3417 }
3418
3419 if (hdsp_check_for_firmware(hdsp, 0)) {
3420 if (hdsp->state & HDSP_FirmwareCached) {
3421 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3422 snd_iprintf(buffer, "Firmware loading from "
3423 "cache failed, "
3424 "please upload manually.\n");
3425 return;
3426 }
3427 } else {
3428 int err;
3429
3430 err = hdsp_request_fw_loader(hdsp);
3431 if (err < 0) {
3432 snd_iprintf(buffer,
3433 "No firmware loaded nor cached, "
3434 "please upload firmware.\n");
3435 return;
3436 }
3437 }
3438 }
3439
3440 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3441 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3442 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3443 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3444 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3445 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3446
3447 snd_iprintf(buffer, "\n");
3448
3449 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3450
3451 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3452 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3453 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3454 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3455
3456 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3457
3458 snd_iprintf(buffer, "\n");
3459
3460 switch (hdsp_clock_source(hdsp)) {
3461 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3462 clock_source = "AutoSync";
3463 break;
3464 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3465 clock_source = "Internal 32 kHz";
3466 break;
3467 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3468 clock_source = "Internal 44.1 kHz";
3469 break;
3470 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3471 clock_source = "Internal 48 kHz";
3472 break;
3473 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3474 clock_source = "Internal 64 kHz";
3475 break;
3476 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3477 clock_source = "Internal 88.2 kHz";
3478 break;
3479 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3480 clock_source = "Internal 96 kHz";
3481 break;
3482 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3483 clock_source = "Internal 128 kHz";
3484 break;
3485 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3486 clock_source = "Internal 176.4 kHz";
3487 break;
3488 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3489 clock_source = "Internal 192 kHz";
3490 break;
3491 default:
3492 clock_source = "Error";
3493 }
3494 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3495
3496 if (hdsp_system_clock_mode(hdsp))
3497 system_clock_mode = "Slave";
3498 else
3499 system_clock_mode = "Master";
3500
3501 switch (hdsp_pref_sync_ref (hdsp)) {
3502 case HDSP_SYNC_FROM_WORD:
3503 pref_sync_ref = "Word Clock";
3504 break;
3505 case HDSP_SYNC_FROM_ADAT_SYNC:
3506 pref_sync_ref = "ADAT Sync";
3507 break;
3508 case HDSP_SYNC_FROM_SPDIF:
3509 pref_sync_ref = "SPDIF";
3510 break;
3511 case HDSP_SYNC_FROM_ADAT1:
3512 pref_sync_ref = "ADAT1";
3513 break;
3514 case HDSP_SYNC_FROM_ADAT2:
3515 pref_sync_ref = "ADAT2";
3516 break;
3517 case HDSP_SYNC_FROM_ADAT3:
3518 pref_sync_ref = "ADAT3";
3519 break;
3520 default:
3521 pref_sync_ref = "Word Clock";
3522 break;
3523 }
3524 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3525
3526 switch (hdsp_autosync_ref (hdsp)) {
3527 case HDSP_AUTOSYNC_FROM_WORD:
3528 autosync_ref = "Word Clock";
3529 break;
3530 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3531 autosync_ref = "ADAT Sync";
3532 break;
3533 case HDSP_AUTOSYNC_FROM_SPDIF:
3534 autosync_ref = "SPDIF";
3535 break;
3536 case HDSP_AUTOSYNC_FROM_NONE:
3537 autosync_ref = "None";
3538 break;
3539 case HDSP_AUTOSYNC_FROM_ADAT1:
3540 autosync_ref = "ADAT1";
3541 break;
3542 case HDSP_AUTOSYNC_FROM_ADAT2:
3543 autosync_ref = "ADAT2";
3544 break;
3545 case HDSP_AUTOSYNC_FROM_ADAT3:
3546 autosync_ref = "ADAT3";
3547 break;
3548 default:
3549 autosync_ref = "---";
3550 break;
3551 }
3552 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3553
3554 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3555
3556 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3557
3558 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3559 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3560
3561 snd_iprintf(buffer, "\n");
3562
3563 if (hdsp->io_type != RPM) {
3564 switch (hdsp_spdif_in(hdsp)) {
3565 case HDSP_SPDIFIN_OPTICAL:
3566 snd_iprintf(buffer, "IEC958 input: Optical\n");
3567 break;
3568 case HDSP_SPDIFIN_COAXIAL:
3569 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3570 break;
3571 case HDSP_SPDIFIN_INTERNAL:
3572 snd_iprintf(buffer, "IEC958 input: Internal\n");
3573 break;
3574 case HDSP_SPDIFIN_AES:
3575 snd_iprintf(buffer, "IEC958 input: AES\n");
3576 break;
3577 default:
3578 snd_iprintf(buffer, "IEC958 input: ???\n");
3579 break;
3580 }
3581 }
3582
3583 if (RPM == hdsp->io_type) {
3584 if (hdsp->control_register & HDSP_RPM_Bypass)
3585 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3586 else
3587 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3588 if (hdsp->control_register & HDSP_RPM_Disconnect)
3589 snd_iprintf(buffer, "RPM disconnected\n");
3590 else
3591 snd_iprintf(buffer, "RPM connected\n");
3592
3593 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3594 case HDSP_RPM_Inp12_Phon_6dB:
3595 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3596 break;
3597 case HDSP_RPM_Inp12_Phon_0dB:
3598 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3599 break;
3600 case HDSP_RPM_Inp12_Phon_n6dB:
3601 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3602 break;
3603 case HDSP_RPM_Inp12_Line_0dB:
3604 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3605 break;
3606 case HDSP_RPM_Inp12_Line_n6dB:
3607 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3608 break;
3609 default:
3610 snd_iprintf(buffer, "Input 1/2: ???\n");
3611 }
3612
3613 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3614 case HDSP_RPM_Inp34_Phon_6dB:
3615 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3616 break;
3617 case HDSP_RPM_Inp34_Phon_0dB:
3618 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3619 break;
3620 case HDSP_RPM_Inp34_Phon_n6dB:
3621 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3622 break;
3623 case HDSP_RPM_Inp34_Line_0dB:
3624 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3625 break;
3626 case HDSP_RPM_Inp34_Line_n6dB:
3627 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3628 break;
3629 default:
3630 snd_iprintf(buffer, "Input 3/4: ???\n");
3631 }
3632
3633 } else {
3634 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3635 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3636 else
3637 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3638
3639 if (hdsp->control_register & HDSP_SPDIFProfessional)
3640 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3641 else
3642 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3643
3644 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3645 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3646 else
3647 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3648
3649 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3650 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3651 else
3652 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3653 x = hdsp_spdif_sample_rate(hdsp);
3654 if (x != 0)
3655 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3656 else
3657 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3658 }
3659 snd_iprintf(buffer, "\n");
3660
3661 /* Sync Check */
3662 x = status & HDSP_Sync0;
3663 if (status & HDSP_Lock0)
3664 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3665 else
3666 snd_iprintf(buffer, "ADAT1: No Lock\n");
3667
3668 switch (hdsp->io_type) {
3669 case Digiface:
3670 case H9652:
3671 x = status & HDSP_Sync1;
3672 if (status & HDSP_Lock1)
3673 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3674 else
3675 snd_iprintf(buffer, "ADAT2: No Lock\n");
3676 x = status & HDSP_Sync2;
3677 if (status & HDSP_Lock2)
3678 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3679 else
3680 snd_iprintf(buffer, "ADAT3: No Lock\n");
3681 break;
3682 default:
3683 /* relax */
3684 break;
3685 }
3686
3687 x = status & HDSP_SPDIFSync;
3688 if (status & HDSP_SPDIFErrorFlag)
3689 snd_iprintf (buffer, "SPDIF: No Lock\n");
3690 else
3691 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3692
3693 x = status2 & HDSP_wc_sync;
3694 if (status2 & HDSP_wc_lock)
3695 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3696 else
3697 snd_iprintf (buffer, "Word Clock: No Lock\n");
3698
3699 x = status & HDSP_TimecodeSync;
3700 if (status & HDSP_TimecodeLock)
3701 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3702 else
3703 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3704
3705 snd_iprintf(buffer, "\n");
3706
3707 /* Informations about H9632 specific controls */
3708 if (hdsp->io_type == H9632) {
3709 char *tmp;
3710
3711 switch (hdsp_ad_gain(hdsp)) {
3712 case 0:
3713 tmp = "-10 dBV";
3714 break;
3715 case 1:
3716 tmp = "+4 dBu";
3717 break;
3718 default:
3719 tmp = "Lo Gain";
3720 break;
3721 }
3722 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3723
3724 switch (hdsp_da_gain(hdsp)) {
3725 case 0:
3726 tmp = "Hi Gain";
3727 break;
3728 case 1:
3729 tmp = "+4 dBu";
3730 break;
3731 default:
3732 tmp = "-10 dBV";
3733 break;
3734 }
3735 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3736
3737 switch (hdsp_phone_gain(hdsp)) {
3738 case 0:
3739 tmp = "0 dB";
3740 break;
3741 case 1:
3742 tmp = "-6 dB";
3743 break;
3744 default:
3745 tmp = "-12 dB";
3746 break;
3747 }
3748 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3749
3750 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3751 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3752 "yes" : "no");
3753
3754 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3755 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3756 else
3757 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3758 snd_iprintf(buffer, "\n");
3759 }
3760
3761 }
3762
3763 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3764 {
3765 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3766 }
3767
3768 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3769 {
3770 struct snd_dma_buffer *capture_dma, *playback_dma;
3771
3772 capture_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3773 playback_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3774 if (!capture_dma || !playback_dma) {
3775 dev_err(hdsp->card->dev,
3776 "%s: no buffers available\n", hdsp->card_name);
3777 return -ENOMEM;
3778 }
3779
3780 /* copy to the own data for alignment */
3781 hdsp->capture_dma_buf = *capture_dma;
3782 hdsp->playback_dma_buf = *playback_dma;
3783
3784 /* Align to bus-space 64K boundary */
3785 hdsp->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);
3786 hdsp->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);
3787
3788 /* Tell the card where it is */
3789 hdsp_write(hdsp, HDSP_inputBufferAddress, hdsp->capture_dma_buf.addr);
3790 hdsp_write(hdsp, HDSP_outputBufferAddress, hdsp->playback_dma_buf.addr);
3791
3792 hdsp->capture_dma_buf.area += hdsp->capture_dma_buf.addr - capture_dma->addr;
3793 hdsp->playback_dma_buf.area += hdsp->playback_dma_buf.addr - playback_dma->addr;
3794 hdsp->capture_buffer = hdsp->capture_dma_buf.area;
3795 hdsp->playback_buffer = hdsp->playback_dma_buf.area;
3796
3797 return 0;
3798 }
3799
3800 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3801 {
3802 unsigned int i;
3803
3804 /* ASSUMPTION: hdsp->lock is either held, or
3805 there is no need to hold it (e.g. during module
3806 initialization).
3807 */
3808
3809 /* set defaults:
3810
3811 SPDIF Input via Coax
3812 Master clock mode
3813 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3814 which implies 2 4096 sample, 32Kbyte periods).
3815 Enable line out.
3816 */
3817
3818 hdsp->control_register = HDSP_ClockModeMaster |
3819 HDSP_SPDIFInputCoaxial |
3820 hdsp_encode_latency(7) |
3821 HDSP_LineOut;
3822
3823
3824 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3825
3826 #ifdef SNDRV_BIG_ENDIAN
3827 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3828 #else
3829 hdsp->control2_register = 0;
3830 #endif
3831 if (hdsp->io_type == H9652)
3832 snd_hdsp_9652_enable_mixer (hdsp);
3833 else
3834 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3835
3836 hdsp_reset_hw_pointer(hdsp);
3837 hdsp_compute_period_size(hdsp);
3838
3839 /* silence everything */
3840
3841 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3842 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3843
3844 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3845 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3846 return -EIO;
3847 }
3848
3849 /* H9632 specific defaults */
3850 if (hdsp->io_type == H9632) {
3851 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3852 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3853 }
3854
3855 /* set a default rate so that the channel map is set up.
3856 */
3857
3858 hdsp_set_rate(hdsp, 48000, 1);
3859
3860 return 0;
3861 }
3862
3863 static void hdsp_midi_work(struct work_struct *work)
3864 {
3865 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3866
3867 if (hdsp->midi[0].pending)
3868 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3869 if (hdsp->midi[1].pending)
3870 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3871 }
3872
3873 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3874 {
3875 struct hdsp *hdsp = (struct hdsp *) dev_id;
3876 unsigned int status;
3877 int audio;
3878 int midi0;
3879 int midi1;
3880 unsigned int midi0status;
3881 unsigned int midi1status;
3882 int schedule = 0;
3883
3884 status = hdsp_read(hdsp, HDSP_statusRegister);
3885
3886 audio = status & HDSP_audioIRQPending;
3887 midi0 = status & HDSP_midi0IRQPending;
3888 midi1 = status & HDSP_midi1IRQPending;
3889
3890 if (!audio && !midi0 && !midi1)
3891 return IRQ_NONE;
3892
3893 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3894
3895 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3896 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3897
3898 if (!(hdsp->state & HDSP_InitializationComplete))
3899 return IRQ_HANDLED;
3900
3901 if (audio) {
3902 if (hdsp->capture_substream)
3903 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3904
3905 if (hdsp->playback_substream)
3906 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3907 }
3908
3909 if (midi0 && midi0status) {
3910 if (hdsp->use_midi_work) {
3911 /* we disable interrupts for this input until processing is done */
3912 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3913 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3914 hdsp->midi[0].pending = 1;
3915 schedule = 1;
3916 } else {
3917 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3918 }
3919 }
3920 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3921 if (hdsp->use_midi_work) {
3922 /* we disable interrupts for this input until processing is done */
3923 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3924 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3925 hdsp->midi[1].pending = 1;
3926 schedule = 1;
3927 } else {
3928 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3929 }
3930 }
3931 if (hdsp->use_midi_work && schedule)
3932 queue_work(system_highpri_wq, &hdsp->midi_work);
3933 return IRQ_HANDLED;
3934 }
3935
3936 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3937 {
3938 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3939 return hdsp_hw_pointer(hdsp);
3940 }
3941
3942 static signed char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3943 int stream,
3944 int channel)
3945
3946 {
3947 int mapped_channel;
3948
3949 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3950 return NULL;
3951
3952 mapped_channel = hdsp->channel_map[channel];
3953 if (mapped_channel < 0)
3954 return NULL;
3955
3956 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3957 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3958 else
3959 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3960 }
3961
3962 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3963 int channel, unsigned long pos,
3964 struct iov_iter *src, unsigned long count)
3965 {
3966 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3967 signed char *channel_buf;
3968
3969 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3970 return -EINVAL;
3971
3972 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3973 if (snd_BUG_ON(!channel_buf))
3974 return -EIO;
3975 if (copy_from_iter(channel_buf + pos, count, src) != count)
3976 return -EFAULT;
3977 return 0;
3978 }
3979
3980 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3981 int channel, unsigned long pos,
3982 struct iov_iter *dst, unsigned long count)
3983 {
3984 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3985 signed char *channel_buf;
3986
3987 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3988 return -EINVAL;
3989
3990 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3991 if (snd_BUG_ON(!channel_buf))
3992 return -EIO;
3993 if (copy_to_iter(channel_buf + pos, count, dst) != count)
3994 return -EFAULT;
3995 return 0;
3996 }
3997
3998 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3999 int channel, unsigned long pos,
4000 unsigned long count)
4001 {
4002 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4003 signed char *channel_buf;
4004
4005 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4006 if (snd_BUG_ON(!channel_buf))
4007 return -EIO;
4008 memset(channel_buf + pos, 0, count);
4009 return 0;
4010 }
4011
4012 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4013 {
4014 struct snd_pcm_runtime *runtime = substream->runtime;
4015 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4016 struct snd_pcm_substream *other;
4017 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4018 other = hdsp->capture_substream;
4019 else
4020 other = hdsp->playback_substream;
4021 if (hdsp->running)
4022 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4023 else
4024 runtime->status->hw_ptr = 0;
4025 if (other) {
4026 struct snd_pcm_substream *s;
4027 struct snd_pcm_runtime *oruntime = other->runtime;
4028 snd_pcm_group_for_each_entry(s, substream) {
4029 if (s == other) {
4030 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4031 break;
4032 }
4033 }
4034 }
4035 return 0;
4036 }
4037
4038 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4039 struct snd_pcm_hw_params *params)
4040 {
4041 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4042 int err;
4043 pid_t this_pid;
4044 pid_t other_pid;
4045
4046 if (hdsp_check_for_iobox (hdsp))
4047 return -EIO;
4048
4049 if (hdsp_check_for_firmware(hdsp, 1))
4050 return -EIO;
4051
4052 spin_lock_irq(&hdsp->lock);
4053
4054 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4055 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4056 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4057 this_pid = hdsp->playback_pid;
4058 other_pid = hdsp->capture_pid;
4059 } else {
4060 this_pid = hdsp->capture_pid;
4061 other_pid = hdsp->playback_pid;
4062 }
4063
4064 if ((other_pid > 0) && (this_pid != other_pid)) {
4065
4066 /* The other stream is open, and not by the same
4067 task as this one. Make sure that the parameters
4068 that matter are the same.
4069 */
4070
4071 if (params_rate(params) != hdsp->system_sample_rate) {
4072 spin_unlock_irq(&hdsp->lock);
4073 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4074 return -EBUSY;
4075 }
4076
4077 if (params_period_size(params) != hdsp->period_bytes / 4) {
4078 spin_unlock_irq(&hdsp->lock);
4079 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4080 return -EBUSY;
4081 }
4082
4083 /* We're fine. */
4084
4085 spin_unlock_irq(&hdsp->lock);
4086 return 0;
4087
4088 } else {
4089 spin_unlock_irq(&hdsp->lock);
4090 }
4091
4092 /* how to make sure that the rate matches an externally-set one ?
4093 */
4094
4095 spin_lock_irq(&hdsp->lock);
4096 if (! hdsp->clock_source_locked) {
4097 err = hdsp_set_rate(hdsp, params_rate(params), 0);
4098 if (err < 0) {
4099 spin_unlock_irq(&hdsp->lock);
4100 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4101 return err;
4102 }
4103 }
4104 spin_unlock_irq(&hdsp->lock);
4105
4106 err = hdsp_set_interrupt_interval(hdsp, params_period_size(params));
4107 if (err < 0) {
4108 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4109 return err;
4110 }
4111
4112 return 0;
4113 }
4114
4115 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4116 struct snd_pcm_channel_info *info)
4117 {
4118 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4119 unsigned int channel = info->channel;
4120
4121 if (snd_BUG_ON(channel >= hdsp->max_channels))
4122 return -EINVAL;
4123 channel = array_index_nospec(channel, hdsp->max_channels);
4124
4125 if (hdsp->channel_map[channel] < 0)
4126 return -EINVAL;
4127
4128 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4129 info->first = 0;
4130 info->step = 32;
4131 return 0;
4132 }
4133
4134 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4135 unsigned int cmd, void *arg)
4136 {
4137 switch (cmd) {
4138 case SNDRV_PCM_IOCTL1_RESET:
4139 return snd_hdsp_reset(substream);
4140 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4141 return snd_hdsp_channel_info(substream, arg);
4142 default:
4143 break;
4144 }
4145
4146 return snd_pcm_lib_ioctl(substream, cmd, arg);
4147 }
4148
4149 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4150 {
4151 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4152 struct snd_pcm_substream *other;
4153 int running;
4154
4155 if (hdsp_check_for_iobox (hdsp))
4156 return -EIO;
4157
4158 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4159 return -EIO;
4160
4161 spin_lock(&hdsp->lock);
4162 running = hdsp->running;
4163 switch (cmd) {
4164 case SNDRV_PCM_TRIGGER_START:
4165 running |= 1 << substream->stream;
4166 break;
4167 case SNDRV_PCM_TRIGGER_STOP:
4168 running &= ~(1 << substream->stream);
4169 break;
4170 default:
4171 snd_BUG();
4172 spin_unlock(&hdsp->lock);
4173 return -EINVAL;
4174 }
4175 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4176 other = hdsp->capture_substream;
4177 else
4178 other = hdsp->playback_substream;
4179
4180 if (other) {
4181 struct snd_pcm_substream *s;
4182 snd_pcm_group_for_each_entry(s, substream) {
4183 if (s == other) {
4184 snd_pcm_trigger_done(s, substream);
4185 if (cmd == SNDRV_PCM_TRIGGER_START)
4186 running |= 1 << s->stream;
4187 else
4188 running &= ~(1 << s->stream);
4189 goto _ok;
4190 }
4191 }
4192 if (cmd == SNDRV_PCM_TRIGGER_START) {
4193 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4194 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4195 hdsp_silence_playback(hdsp);
4196 } else {
4197 if (running &&
4198 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4199 hdsp_silence_playback(hdsp);
4200 }
4201 } else {
4202 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4203 hdsp_silence_playback(hdsp);
4204 }
4205 _ok:
4206 snd_pcm_trigger_done(substream, substream);
4207 if (!hdsp->running && running)
4208 hdsp_start_audio(hdsp);
4209 else if (hdsp->running && !running)
4210 hdsp_stop_audio(hdsp);
4211 hdsp->running = running;
4212 spin_unlock(&hdsp->lock);
4213
4214 return 0;
4215 }
4216
4217 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4218 {
4219 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4220 int result = 0;
4221
4222 if (hdsp_check_for_iobox (hdsp))
4223 return -EIO;
4224
4225 if (hdsp_check_for_firmware(hdsp, 1))
4226 return -EIO;
4227
4228 spin_lock_irq(&hdsp->lock);
4229 if (!hdsp->running)
4230 hdsp_reset_hw_pointer(hdsp);
4231 spin_unlock_irq(&hdsp->lock);
4232 return result;
4233 }
4234
4235 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4236 {
4237 .info = (SNDRV_PCM_INFO_MMAP |
4238 SNDRV_PCM_INFO_MMAP_VALID |
4239 SNDRV_PCM_INFO_NONINTERLEAVED |
4240 SNDRV_PCM_INFO_SYNC_START |
4241 SNDRV_PCM_INFO_DOUBLE),
4242 #ifdef SNDRV_BIG_ENDIAN
4243 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4244 #else
4245 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4246 #endif
4247 .rates = (SNDRV_PCM_RATE_32000 |
4248 SNDRV_PCM_RATE_44100 |
4249 SNDRV_PCM_RATE_48000 |
4250 SNDRV_PCM_RATE_64000 |
4251 SNDRV_PCM_RATE_88200 |
4252 SNDRV_PCM_RATE_96000),
4253 .rate_min = 32000,
4254 .rate_max = 96000,
4255 .channels_min = 6,
4256 .channels_max = HDSP_MAX_CHANNELS,
4257 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4258 .period_bytes_min = (64 * 4) * 10,
4259 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4260 .periods_min = 2,
4261 .periods_max = 2,
4262 .fifo_size = 0
4263 };
4264
4265 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4266 {
4267 .info = (SNDRV_PCM_INFO_MMAP |
4268 SNDRV_PCM_INFO_MMAP_VALID |
4269 SNDRV_PCM_INFO_NONINTERLEAVED |
4270 SNDRV_PCM_INFO_SYNC_START),
4271 #ifdef SNDRV_BIG_ENDIAN
4272 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4273 #else
4274 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4275 #endif
4276 .rates = (SNDRV_PCM_RATE_32000 |
4277 SNDRV_PCM_RATE_44100 |
4278 SNDRV_PCM_RATE_48000 |
4279 SNDRV_PCM_RATE_64000 |
4280 SNDRV_PCM_RATE_88200 |
4281 SNDRV_PCM_RATE_96000),
4282 .rate_min = 32000,
4283 .rate_max = 96000,
4284 .channels_min = 5,
4285 .channels_max = HDSP_MAX_CHANNELS,
4286 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4287 .period_bytes_min = (64 * 4) * 10,
4288 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4289 .periods_min = 2,
4290 .periods_max = 2,
4291 .fifo_size = 0
4292 };
4293
4294 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4295
4296 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4297 .count = ARRAY_SIZE(hdsp_period_sizes),
4298 .list = hdsp_period_sizes,
4299 .mask = 0
4300 };
4301
4302 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4303
4304 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4305 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4306 .list = hdsp_9632_sample_rates,
4307 .mask = 0
4308 };
4309
4310 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4311 struct snd_pcm_hw_rule *rule)
4312 {
4313 struct hdsp *hdsp = rule->private;
4314 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4315 if (hdsp->io_type == H9632) {
4316 unsigned int list[3];
4317 list[0] = hdsp->qs_in_channels;
4318 list[1] = hdsp->ds_in_channels;
4319 list[2] = hdsp->ss_in_channels;
4320 return snd_interval_list(c, 3, list, 0);
4321 } else {
4322 unsigned int list[2];
4323 list[0] = hdsp->ds_in_channels;
4324 list[1] = hdsp->ss_in_channels;
4325 return snd_interval_list(c, 2, list, 0);
4326 }
4327 }
4328
4329 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4330 struct snd_pcm_hw_rule *rule)
4331 {
4332 unsigned int list[3];
4333 struct hdsp *hdsp = rule->private;
4334 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4335 if (hdsp->io_type == H9632) {
4336 list[0] = hdsp->qs_out_channels;
4337 list[1] = hdsp->ds_out_channels;
4338 list[2] = hdsp->ss_out_channels;
4339 return snd_interval_list(c, 3, list, 0);
4340 } else {
4341 list[0] = hdsp->ds_out_channels;
4342 list[1] = hdsp->ss_out_channels;
4343 }
4344 return snd_interval_list(c, 2, list, 0);
4345 }
4346
4347 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4348 struct snd_pcm_hw_rule *rule)
4349 {
4350 struct hdsp *hdsp = rule->private;
4351 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4352 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4353 if (r->min > 96000 && hdsp->io_type == H9632) {
4354 struct snd_interval t = {
4355 .min = hdsp->qs_in_channels,
4356 .max = hdsp->qs_in_channels,
4357 .integer = 1,
4358 };
4359 return snd_interval_refine(c, &t);
4360 } else if (r->min > 48000 && r->max <= 96000) {
4361 struct snd_interval t = {
4362 .min = hdsp->ds_in_channels,
4363 .max = hdsp->ds_in_channels,
4364 .integer = 1,
4365 };
4366 return snd_interval_refine(c, &t);
4367 } else if (r->max < 64000) {
4368 struct snd_interval t = {
4369 .min = hdsp->ss_in_channels,
4370 .max = hdsp->ss_in_channels,
4371 .integer = 1,
4372 };
4373 return snd_interval_refine(c, &t);
4374 }
4375 return 0;
4376 }
4377
4378 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4379 struct snd_pcm_hw_rule *rule)
4380 {
4381 struct hdsp *hdsp = rule->private;
4382 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4383 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4384 if (r->min > 96000 && hdsp->io_type == H9632) {
4385 struct snd_interval t = {
4386 .min = hdsp->qs_out_channels,
4387 .max = hdsp->qs_out_channels,
4388 .integer = 1,
4389 };
4390 return snd_interval_refine(c, &t);
4391 } else if (r->min > 48000 && r->max <= 96000) {
4392 struct snd_interval t = {
4393 .min = hdsp->ds_out_channels,
4394 .max = hdsp->ds_out_channels,
4395 .integer = 1,
4396 };
4397 return snd_interval_refine(c, &t);
4398 } else if (r->max < 64000) {
4399 struct snd_interval t = {
4400 .min = hdsp->ss_out_channels,
4401 .max = hdsp->ss_out_channels,
4402 .integer = 1,
4403 };
4404 return snd_interval_refine(c, &t);
4405 }
4406 return 0;
4407 }
4408
4409 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4410 struct snd_pcm_hw_rule *rule)
4411 {
4412 struct hdsp *hdsp = rule->private;
4413 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4414 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4415 if (c->min >= hdsp->ss_out_channels) {
4416 struct snd_interval t = {
4417 .min = 32000,
4418 .max = 48000,
4419 .integer = 1,
4420 };
4421 return snd_interval_refine(r, &t);
4422 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4423 struct snd_interval t = {
4424 .min = 128000,
4425 .max = 192000,
4426 .integer = 1,
4427 };
4428 return snd_interval_refine(r, &t);
4429 } else if (c->max <= hdsp->ds_out_channels) {
4430 struct snd_interval t = {
4431 .min = 64000,
4432 .max = 96000,
4433 .integer = 1,
4434 };
4435 return snd_interval_refine(r, &t);
4436 }
4437 return 0;
4438 }
4439
4440 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4441 struct snd_pcm_hw_rule *rule)
4442 {
4443 struct hdsp *hdsp = rule->private;
4444 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4445 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4446 if (c->min >= hdsp->ss_in_channels) {
4447 struct snd_interval t = {
4448 .min = 32000,
4449 .max = 48000,
4450 .integer = 1,
4451 };
4452 return snd_interval_refine(r, &t);
4453 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4454 struct snd_interval t = {
4455 .min = 128000,
4456 .max = 192000,
4457 .integer = 1,
4458 };
4459 return snd_interval_refine(r, &t);
4460 } else if (c->max <= hdsp->ds_in_channels) {
4461 struct snd_interval t = {
4462 .min = 64000,
4463 .max = 96000,
4464 .integer = 1,
4465 };
4466 return snd_interval_refine(r, &t);
4467 }
4468 return 0;
4469 }
4470
4471 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4472 {
4473 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4474 struct snd_pcm_runtime *runtime = substream->runtime;
4475
4476 if (hdsp_check_for_iobox (hdsp))
4477 return -EIO;
4478
4479 if (hdsp_check_for_firmware(hdsp, 1))
4480 return -EIO;
4481
4482 spin_lock_irq(&hdsp->lock);
4483
4484 snd_pcm_set_sync(substream);
4485
4486 runtime->hw = snd_hdsp_playback_subinfo;
4487 snd_pcm_set_runtime_buffer(substream, &hdsp->playback_dma_buf);
4488
4489 hdsp->playback_pid = current->pid;
4490 hdsp->playback_substream = substream;
4491
4492 spin_unlock_irq(&hdsp->lock);
4493
4494 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4495 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4496 if (hdsp->clock_source_locked) {
4497 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4498 } else if (hdsp->io_type == H9632) {
4499 runtime->hw.rate_max = 192000;
4500 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4501 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4502 }
4503 if (hdsp->io_type == H9632) {
4504 runtime->hw.channels_min = hdsp->qs_out_channels;
4505 runtime->hw.channels_max = hdsp->ss_out_channels;
4506 }
4507
4508 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4509 snd_hdsp_hw_rule_out_channels, hdsp,
4510 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4511 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4512 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4513 SNDRV_PCM_HW_PARAM_RATE, -1);
4514 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4515 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4516 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4517
4518 if (RPM != hdsp->io_type) {
4519 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4520 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4521 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4522 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4523 }
4524 return 0;
4525 }
4526
4527 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4528 {
4529 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4530
4531 spin_lock_irq(&hdsp->lock);
4532
4533 hdsp->playback_pid = -1;
4534 hdsp->playback_substream = NULL;
4535
4536 spin_unlock_irq(&hdsp->lock);
4537
4538 if (RPM != hdsp->io_type) {
4539 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4540 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4541 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4542 }
4543 return 0;
4544 }
4545
4546
4547 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4548 {
4549 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4550 struct snd_pcm_runtime *runtime = substream->runtime;
4551
4552 if (hdsp_check_for_iobox (hdsp))
4553 return -EIO;
4554
4555 if (hdsp_check_for_firmware(hdsp, 1))
4556 return -EIO;
4557
4558 spin_lock_irq(&hdsp->lock);
4559
4560 snd_pcm_set_sync(substream);
4561
4562 runtime->hw = snd_hdsp_capture_subinfo;
4563 snd_pcm_set_runtime_buffer(substream, &hdsp->capture_dma_buf);
4564
4565 hdsp->capture_pid = current->pid;
4566 hdsp->capture_substream = substream;
4567
4568 spin_unlock_irq(&hdsp->lock);
4569
4570 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4571 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4572 if (hdsp->io_type == H9632) {
4573 runtime->hw.channels_min = hdsp->qs_in_channels;
4574 runtime->hw.channels_max = hdsp->ss_in_channels;
4575 runtime->hw.rate_max = 192000;
4576 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4577 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4578 }
4579 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4580 snd_hdsp_hw_rule_in_channels, hdsp,
4581 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4582 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4583 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4584 SNDRV_PCM_HW_PARAM_RATE, -1);
4585 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4586 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4587 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4588 return 0;
4589 }
4590
4591 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4592 {
4593 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4594
4595 spin_lock_irq(&hdsp->lock);
4596
4597 hdsp->capture_pid = -1;
4598 hdsp->capture_substream = NULL;
4599
4600 spin_unlock_irq(&hdsp->lock);
4601 return 0;
4602 }
4603
4604 /* helper functions for copying meter values */
4605 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4606 {
4607 u32 val = readl(src);
4608 return copy_to_user(dest, &val, 4);
4609 }
4610
4611 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4612 {
4613 u32 rms_low, rms_high;
4614 u64 rms;
4615 rms_low = readl(src_low);
4616 rms_high = readl(src_high);
4617 rms = ((u64)rms_high << 32) | rms_low;
4618 return copy_to_user(dest, &rms, 8);
4619 }
4620
4621 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4622 {
4623 u32 rms_low, rms_high;
4624 u64 rms;
4625 rms_low = readl(src_low) & 0xffffff00;
4626 rms_high = readl(src_high) & 0xffffff00;
4627 rms = ((u64)rms_high << 32) | rms_low;
4628 return copy_to_user(dest, &rms, 8);
4629 }
4630
4631 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4632 {
4633 int doublespeed = 0;
4634 int i, j, channels, ofs;
4635
4636 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4637 doublespeed = 1;
4638 channels = doublespeed ? 14 : 26;
4639 for (i = 0, j = 0; i < 26; ++i) {
4640 if (doublespeed && (i & 4))
4641 continue;
4642 ofs = HDSP_9652_peakBase - j * 4;
4643 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4644 return -EFAULT;
4645 ofs -= channels * 4;
4646 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4647 return -EFAULT;
4648 ofs -= channels * 4;
4649 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4650 return -EFAULT;
4651 ofs = HDSP_9652_rmsBase + j * 8;
4652 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4653 hdsp->iobase + ofs + 4))
4654 return -EFAULT;
4655 ofs += channels * 8;
4656 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4657 hdsp->iobase + ofs + 4))
4658 return -EFAULT;
4659 ofs += channels * 8;
4660 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4661 hdsp->iobase + ofs + 4))
4662 return -EFAULT;
4663 j++;
4664 }
4665 return 0;
4666 }
4667
4668 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4669 {
4670 int i, j;
4671 struct hdsp_9632_meters __iomem *m;
4672 int doublespeed = 0;
4673
4674 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4675 doublespeed = 1;
4676 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4677 for (i = 0, j = 0; i < 16; ++i, ++j) {
4678 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4679 return -EFAULT;
4680 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4681 return -EFAULT;
4682 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4683 return -EFAULT;
4684 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4685 &m->input_rms_high[j]))
4686 return -EFAULT;
4687 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4688 &m->playback_rms_high[j]))
4689 return -EFAULT;
4690 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4691 &m->output_rms_high[j]))
4692 return -EFAULT;
4693 if (doublespeed && i == 3) i += 4;
4694 }
4695 return 0;
4696 }
4697
4698 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4699 {
4700 int i;
4701
4702 for (i = 0; i < 26; i++) {
4703 if (copy_u32_le(&peak_rms->playback_peaks[i],
4704 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4705 return -EFAULT;
4706 if (copy_u32_le(&peak_rms->input_peaks[i],
4707 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4708 return -EFAULT;
4709 }
4710 for (i = 0; i < 28; i++) {
4711 if (copy_u32_le(&peak_rms->output_peaks[i],
4712 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4713 return -EFAULT;
4714 }
4715 for (i = 0; i < 26; ++i) {
4716 if (copy_u64_le(&peak_rms->playback_rms[i],
4717 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4718 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4719 return -EFAULT;
4720 if (copy_u64_le(&peak_rms->input_rms[i],
4721 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4722 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4723 return -EFAULT;
4724 }
4725 return 0;
4726 }
4727
4728 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4729 {
4730 struct hdsp *hdsp = hw->private_data;
4731 void __user *argp = (void __user *)arg;
4732 int err;
4733
4734 switch (cmd) {
4735 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4736 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4737
4738 err = hdsp_check_for_iobox(hdsp);
4739 if (err < 0)
4740 return err;
4741
4742 err = hdsp_check_for_firmware(hdsp, 1);
4743 if (err < 0)
4744 return err;
4745
4746 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4747 dev_err(hdsp->card->dev,
4748 "firmware needs to be uploaded to the card.\n");
4749 return -EINVAL;
4750 }
4751
4752 switch (hdsp->io_type) {
4753 case H9652:
4754 return hdsp_9652_get_peak(hdsp, peak_rms);
4755 case H9632:
4756 return hdsp_9632_get_peak(hdsp, peak_rms);
4757 default:
4758 return hdsp_get_peak(hdsp, peak_rms);
4759 }
4760 }
4761 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4762 struct hdsp_config_info info;
4763 unsigned long flags;
4764 int i;
4765
4766 err = hdsp_check_for_iobox(hdsp);
4767 if (err < 0)
4768 return err;
4769
4770 err = hdsp_check_for_firmware(hdsp, 1);
4771 if (err < 0)
4772 return err;
4773
4774 memset(&info, 0, sizeof(info));
4775 spin_lock_irqsave(&hdsp->lock, flags);
4776 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4777 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4778 if (hdsp->io_type != H9632)
4779 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4780 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4781 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4782 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4783 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4784 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4785 HDSP_SPDIFOpticalOut);
4786 info.spdif_professional = (unsigned char)
4787 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4788 info.spdif_emphasis = (unsigned char)
4789 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4790 info.spdif_nonaudio = (unsigned char)
4791 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4792 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4793 info.system_sample_rate = hdsp->system_sample_rate;
4794 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4795 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4796 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4797 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4798 info.line_out = (unsigned char)
4799 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4800 if (hdsp->io_type == H9632) {
4801 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4802 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4803 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4804 info.xlr_breakout_cable =
4805 (unsigned char)hdsp_toggle_setting(hdsp,
4806 HDSP_XLRBreakoutCable);
4807
4808 } else if (hdsp->io_type == RPM) {
4809 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4810 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4811 }
4812 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4813 info.analog_extension_board =
4814 (unsigned char)hdsp_toggle_setting(hdsp,
4815 HDSP_AnalogExtensionBoard);
4816 spin_unlock_irqrestore(&hdsp->lock, flags);
4817 if (copy_to_user(argp, &info, sizeof(info)))
4818 return -EFAULT;
4819 break;
4820 }
4821 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4822 struct hdsp_9632_aeb h9632_aeb;
4823
4824 if (hdsp->io_type != H9632) return -EINVAL;
4825 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4826 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4827 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4828 return -EFAULT;
4829 break;
4830 }
4831 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4832 struct hdsp_version hdsp_version;
4833 int err;
4834
4835 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4836 if (hdsp->io_type == Undefined) {
4837 err = hdsp_get_iobox_version(hdsp);
4838 if (err < 0)
4839 return err;
4840 }
4841 memset(&hdsp_version, 0, sizeof(hdsp_version));
4842 hdsp_version.io_type = hdsp->io_type;
4843 hdsp_version.firmware_rev = hdsp->firmware_rev;
4844 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))
4845 return -EFAULT;
4846 break;
4847 }
4848 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4849 struct hdsp_firmware firmware;
4850 u32 __user *firmware_data;
4851 int err;
4852
4853 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4854 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4855 if (hdsp->io_type == Undefined) return -EINVAL;
4856
4857 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4858 return -EBUSY;
4859
4860 dev_info(hdsp->card->dev,
4861 "initializing firmware upload\n");
4862 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4863 return -EFAULT;
4864 firmware_data = (u32 __user *)firmware.firmware_data;
4865
4866 if (hdsp_check_for_iobox (hdsp))
4867 return -EIO;
4868
4869 if (!hdsp->fw_uploaded) {
4870 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4871 if (!hdsp->fw_uploaded)
4872 return -ENOMEM;
4873 }
4874
4875 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4876 HDSP_FIRMWARE_SIZE)) {
4877 vfree(hdsp->fw_uploaded);
4878 hdsp->fw_uploaded = NULL;
4879 return -EFAULT;
4880 }
4881
4882 hdsp->state |= HDSP_FirmwareCached;
4883
4884 err = snd_hdsp_load_firmware_from_cache(hdsp);
4885 if (err < 0)
4886 return err;
4887
4888 if (!(hdsp->state & HDSP_InitializationComplete)) {
4889 err = snd_hdsp_enable_io(hdsp);
4890 if (err < 0)
4891 return err;
4892
4893 snd_hdsp_initialize_channels(hdsp);
4894 snd_hdsp_initialize_midi_flush(hdsp);
4895
4896 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
4897 if (err < 0) {
4898 dev_err(hdsp->card->dev,
4899 "error creating alsa devices\n");
4900 return err;
4901 }
4902 }
4903 break;
4904 }
4905 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4906 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4907 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4908 return -EFAULT;
4909 break;
4910 }
4911 default:
4912 return -EINVAL;
4913 }
4914 return 0;
4915 }
4916
4917 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4918 .open = snd_hdsp_playback_open,
4919 .close = snd_hdsp_playback_release,
4920 .ioctl = snd_hdsp_ioctl,
4921 .hw_params = snd_hdsp_hw_params,
4922 .prepare = snd_hdsp_prepare,
4923 .trigger = snd_hdsp_trigger,
4924 .pointer = snd_hdsp_hw_pointer,
4925 .copy = snd_hdsp_playback_copy,
4926 .fill_silence = snd_hdsp_hw_silence,
4927 };
4928
4929 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4930 .open = snd_hdsp_capture_open,
4931 .close = snd_hdsp_capture_release,
4932 .ioctl = snd_hdsp_ioctl,
4933 .hw_params = snd_hdsp_hw_params,
4934 .prepare = snd_hdsp_prepare,
4935 .trigger = snd_hdsp_trigger,
4936 .pointer = snd_hdsp_hw_pointer,
4937 .copy = snd_hdsp_capture_copy,
4938 };
4939
4940 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4941 {
4942 struct snd_hwdep *hw;
4943 int err;
4944
4945 err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw);
4946 if (err < 0)
4947 return err;
4948
4949 hdsp->hwdep = hw;
4950 hw->private_data = hdsp;
4951 strcpy(hw->name, "HDSP hwdep interface");
4952
4953 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4954 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4955
4956 return 0;
4957 }
4958
4959 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4960 {
4961 struct snd_pcm *pcm;
4962 int err;
4963
4964 err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm);
4965 if (err < 0)
4966 return err;
4967
4968 hdsp->pcm = pcm;
4969 pcm->private_data = hdsp;
4970 strcpy(pcm->name, hdsp->card_name);
4971
4972 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4973 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4974
4975 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4976
4977 return 0;
4978 }
4979
4980 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4981 {
4982 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4983 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4984 }
4985
4986 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4987 {
4988 int i;
4989
4990 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4991 dev_err(hdsp->card->dev,
4992 "enable_io fifo_wait failed\n");
4993 return -EIO;
4994 }
4995
4996 for (i = 0; i < hdsp->max_channels; ++i) {
4997 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4998 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4999 }
5000
5001 return 0;
5002 }
5003
5004 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5005 {
5006 int status, aebi_channels, aebo_channels, i;
5007
5008 switch (hdsp->io_type) {
5009 case Digiface:
5010 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5011 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5012 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5013 break;
5014
5015 case H9652:
5016 hdsp->card_name = "RME Hammerfall HDSP 9652";
5017 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5018 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5019 break;
5020
5021 case H9632:
5022 status = hdsp_read(hdsp, HDSP_statusRegister);
5023 /* HDSP_AEBx bits are low when AEB are connected */
5024 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5025 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5026 hdsp->card_name = "RME Hammerfall HDSP 9632";
5027 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5028 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5029 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5030 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5031 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5032 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5033 /* Disable loopback of output channels, as the set function
5034 * only sets on a change we fake all bits (channels) as enabled.
5035 */
5036 hdsp->io_loopback = 0xffffffff;
5037 for (i = 0; i < hdsp->max_channels; ++i)
5038 hdsp_loopback_set(hdsp, i, false);
5039 break;
5040
5041 case Multiface:
5042 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5043 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5044 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5045 break;
5046
5047 case RPM:
5048 hdsp->card_name = "RME Hammerfall DSP + RPM";
5049 hdsp->ss_in_channels = RPM_CHANNELS-1;
5050 hdsp->ss_out_channels = RPM_CHANNELS;
5051 hdsp->ds_in_channels = RPM_CHANNELS-1;
5052 hdsp->ds_out_channels = RPM_CHANNELS;
5053 break;
5054
5055 default:
5056 /* should never get here */
5057 break;
5058 }
5059 }
5060
5061 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5062 {
5063 snd_hdsp_flush_midi_input (hdsp, 0);
5064 snd_hdsp_flush_midi_input (hdsp, 1);
5065 }
5066
5067 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5068 {
5069 int err;
5070
5071 err = snd_hdsp_create_pcm(card, hdsp);
5072 if (err < 0) {
5073 dev_err(card->dev,
5074 "Error creating pcm interface\n");
5075 return err;
5076 }
5077
5078
5079 err = snd_hdsp_create_midi(card, hdsp, 0);
5080 if (err < 0) {
5081 dev_err(card->dev,
5082 "Error creating first midi interface\n");
5083 return err;
5084 }
5085
5086 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5087 err = snd_hdsp_create_midi(card, hdsp, 1);
5088 if (err < 0) {
5089 dev_err(card->dev,
5090 "Error creating second midi interface\n");
5091 return err;
5092 }
5093 }
5094
5095 err = snd_hdsp_create_controls(card, hdsp);
5096 if (err < 0) {
5097 dev_err(card->dev,
5098 "Error creating ctl interface\n");
5099 return err;
5100 }
5101
5102 snd_hdsp_proc_init(hdsp);
5103
5104 hdsp->system_sample_rate = -1;
5105 hdsp->playback_pid = -1;
5106 hdsp->capture_pid = -1;
5107 hdsp->capture_substream = NULL;
5108 hdsp->playback_substream = NULL;
5109
5110 err = snd_hdsp_set_defaults(hdsp);
5111 if (err < 0) {
5112 dev_err(card->dev,
5113 "Error setting default values\n");
5114 return err;
5115 }
5116
5117 if (!(hdsp->state & HDSP_InitializationComplete)) {
5118 strcpy(card->shortname, "Hammerfall DSP");
5119 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5120 hdsp->port, hdsp->irq);
5121
5122 err = snd_card_register(card);
5123 if (err < 0) {
5124 dev_err(card->dev,
5125 "error registering card\n");
5126 return err;
5127 }
5128 hdsp->state |= HDSP_InitializationComplete;
5129 }
5130
5131 return 0;
5132 }
5133
5134 /* load firmware via hotplug fw loader */
5135 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5136 {
5137 const char *fwfile;
5138 const struct firmware *fw;
5139 int err;
5140
5141 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5142 return 0;
5143 if (hdsp->io_type == Undefined) {
5144 err = hdsp_get_iobox_version(hdsp);
5145 if (err < 0)
5146 return err;
5147 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5148 return 0;
5149 }
5150
5151 /* caution: max length of firmware filename is 30! */
5152 switch (hdsp->io_type) {
5153 case RPM:
5154 fwfile = "rpm_firmware.bin";
5155 break;
5156 case Multiface:
5157 if (hdsp->firmware_rev == 0xa)
5158 fwfile = "multiface_firmware.bin";
5159 else
5160 fwfile = "multiface_firmware_rev11.bin";
5161 break;
5162 case Digiface:
5163 if (hdsp->firmware_rev == 0xa)
5164 fwfile = "digiface_firmware.bin";
5165 else
5166 fwfile = "digiface_firmware_rev11.bin";
5167 break;
5168 default:
5169 dev_err(hdsp->card->dev,
5170 "invalid io_type %d\n", hdsp->io_type);
5171 return -EINVAL;
5172 }
5173
5174 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5175 dev_err(hdsp->card->dev,
5176 "cannot load firmware %s\n", fwfile);
5177 return -ENOENT;
5178 }
5179 if (fw->size < HDSP_FIRMWARE_SIZE) {
5180 dev_err(hdsp->card->dev,
5181 "too short firmware size %d (expected %d)\n",
5182 (int)fw->size, HDSP_FIRMWARE_SIZE);
5183 release_firmware(fw);
5184 return -EINVAL;
5185 }
5186
5187 hdsp->firmware = fw;
5188
5189 hdsp->state |= HDSP_FirmwareCached;
5190
5191 err = snd_hdsp_load_firmware_from_cache(hdsp);
5192 if (err < 0)
5193 return err;
5194
5195 if (!(hdsp->state & HDSP_InitializationComplete)) {
5196 err = snd_hdsp_enable_io(hdsp);
5197 if (err < 0)
5198 return err;
5199
5200 err = snd_hdsp_create_hwdep(hdsp->card, hdsp);
5201 if (err < 0) {
5202 dev_err(hdsp->card->dev,
5203 "error creating hwdep device\n");
5204 return err;
5205 }
5206 snd_hdsp_initialize_channels(hdsp);
5207 snd_hdsp_initialize_midi_flush(hdsp);
5208 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
5209 if (err < 0) {
5210 dev_err(hdsp->card->dev,
5211 "error creating alsa devices\n");
5212 return err;
5213 }
5214 }
5215 return 0;
5216 }
5217
5218 static int snd_hdsp_create(struct snd_card *card,
5219 struct hdsp *hdsp)
5220 {
5221 struct pci_dev *pci = hdsp->pci;
5222 int err;
5223 int is_9652 = 0;
5224 int is_9632 = 0;
5225
5226 hdsp->irq = -1;
5227 hdsp->state = 0;
5228 hdsp->midi[0].rmidi = NULL;
5229 hdsp->midi[1].rmidi = NULL;
5230 hdsp->midi[0].input = NULL;
5231 hdsp->midi[1].input = NULL;
5232 hdsp->midi[0].output = NULL;
5233 hdsp->midi[1].output = NULL;
5234 hdsp->midi[0].pending = 0;
5235 hdsp->midi[1].pending = 0;
5236 spin_lock_init(&hdsp->midi[0].lock);
5237 spin_lock_init(&hdsp->midi[1].lock);
5238 hdsp->iobase = NULL;
5239 hdsp->control_register = 0;
5240 hdsp->control2_register = 0;
5241 hdsp->io_type = Undefined;
5242 hdsp->max_channels = 26;
5243
5244 hdsp->card = card;
5245
5246 spin_lock_init(&hdsp->lock);
5247
5248 INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5249
5250 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5251 hdsp->firmware_rev &= 0xff;
5252
5253 /* From Martin Bjoernsen :
5254 "It is important that the card's latency timer register in
5255 the PCI configuration space is set to a value much larger
5256 than 0 by the computer's BIOS or the driver.
5257 The windows driver always sets this 8 bit register [...]
5258 to its maximum 255 to avoid problems with some computers."
5259 */
5260 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5261
5262 strcpy(card->driver, "H-DSP");
5263 strcpy(card->mixername, "Xilinx FPGA");
5264
5265 if (hdsp->firmware_rev < 0xa)
5266 return -ENODEV;
5267 else if (hdsp->firmware_rev < 0x64)
5268 hdsp->card_name = "RME Hammerfall DSP";
5269 else if (hdsp->firmware_rev < 0x96) {
5270 hdsp->card_name = "RME HDSP 9652";
5271 is_9652 = 1;
5272 } else {
5273 hdsp->card_name = "RME HDSP 9632";
5274 hdsp->max_channels = 16;
5275 is_9632 = 1;
5276 }
5277
5278 err = pcim_enable_device(pci);
5279 if (err < 0)
5280 return err;
5281
5282 pci_set_master(hdsp->pci);
5283
5284 err = pci_request_regions(pci, "hdsp");
5285 if (err < 0)
5286 return err;
5287 hdsp->port = pci_resource_start(pci, 0);
5288 hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT);
5289 if (!hdsp->iobase) {
5290 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5291 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5292 return -EBUSY;
5293 }
5294
5295 if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt,
5296 IRQF_SHARED, KBUILD_MODNAME, hdsp)) {
5297 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5298 return -EBUSY;
5299 }
5300
5301 hdsp->irq = pci->irq;
5302 card->sync_irq = hdsp->irq;
5303 hdsp->precise_ptr = 0;
5304 hdsp->use_midi_work = 1;
5305 hdsp->dds_value = 0;
5306
5307 err = snd_hdsp_initialize_memory(hdsp);
5308 if (err < 0)
5309 return err;
5310
5311 if (!is_9652 && !is_9632) {
5312 /* we wait a maximum of 10 seconds to let freshly
5313 * inserted cardbus cards do their hardware init */
5314 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5315
5316 if (err < 0)
5317 return err;
5318
5319 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5320 err = hdsp_request_fw_loader(hdsp);
5321 if (err < 0)
5322 /* we don't fail as this can happen
5323 if userspace is not ready for
5324 firmware upload
5325 */
5326 dev_err(hdsp->card->dev,
5327 "couldn't get firmware from userspace. try using hdsploader\n");
5328 else
5329 /* init is complete, we return */
5330 return 0;
5331 /* we defer initialization */
5332 dev_info(hdsp->card->dev,
5333 "card initialization pending : waiting for firmware\n");
5334 err = snd_hdsp_create_hwdep(card, hdsp);
5335 if (err < 0)
5336 return err;
5337 return 0;
5338 } else {
5339 dev_info(hdsp->card->dev,
5340 "Firmware already present, initializing card.\n");
5341 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5342 hdsp->io_type = RPM;
5343 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5344 hdsp->io_type = Multiface;
5345 else
5346 hdsp->io_type = Digiface;
5347 }
5348 }
5349
5350 err = snd_hdsp_enable_io(hdsp);
5351 if (err)
5352 return err;
5353
5354 if (is_9652)
5355 hdsp->io_type = H9652;
5356
5357 if (is_9632)
5358 hdsp->io_type = H9632;
5359
5360 err = snd_hdsp_create_hwdep(card, hdsp);
5361 if (err < 0)
5362 return err;
5363
5364 snd_hdsp_initialize_channels(hdsp);
5365 snd_hdsp_initialize_midi_flush(hdsp);
5366
5367 hdsp->state |= HDSP_FirmwareLoaded;
5368
5369 err = snd_hdsp_create_alsa_devices(card, hdsp);
5370 if (err < 0)
5371 return err;
5372
5373 return 0;
5374 }
5375
5376 static void snd_hdsp_card_free(struct snd_card *card)
5377 {
5378 struct hdsp *hdsp = card->private_data;
5379
5380 if (hdsp->port) {
5381 /* stop the audio, and cancel all interrupts */
5382 cancel_work_sync(&hdsp->midi_work);
5383 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5384 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5385 }
5386
5387 release_firmware(hdsp->firmware);
5388 vfree(hdsp->fw_uploaded);
5389 }
5390
5391 static int snd_hdsp_probe(struct pci_dev *pci,
5392 const struct pci_device_id *pci_id)
5393 {
5394 static int dev;
5395 struct hdsp *hdsp;
5396 struct snd_card *card;
5397 int err;
5398
5399 if (dev >= SNDRV_CARDS)
5400 return -ENODEV;
5401 if (!enable[dev]) {
5402 dev++;
5403 return -ENOENT;
5404 }
5405
5406 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5407 sizeof(struct hdsp), &card);
5408 if (err < 0)
5409 return err;
5410
5411 hdsp = card->private_data;
5412 card->private_free = snd_hdsp_card_free;
5413 hdsp->dev = dev;
5414 hdsp->pci = pci;
5415 err = snd_hdsp_create(card, hdsp);
5416 if (err)
5417 goto error;
5418
5419 strcpy(card->shortname, "Hammerfall DSP");
5420 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5421 hdsp->port, hdsp->irq);
5422 err = snd_card_register(card);
5423 if (err)
5424 goto error;
5425 pci_set_drvdata(pci, card);
5426 dev++;
5427 return 0;
5428
5429 error:
5430 snd_card_free(card);
5431 return err;
5432 }
5433
5434 static struct pci_driver hdsp_driver = {
5435 .name = KBUILD_MODNAME,
5436 .id_table = snd_hdsp_ids,
5437 .probe = snd_hdsp_probe,
5438 };
5439
5440 module_pci_driver(hdsp_driver);
5441
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