1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Driver for Digigram VXpocket soundcards
4 *
5 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
6 */
7
8 #ifndef __VXPOCKET_H
9 #define __VXPOCKET_H
10
11 #include <sound/vx_core.h>
12
13 #include <pcmcia/cistpl.h>
14 #include <pcmcia/ds.h>
15
16 struct snd_vxpocket {
17
18 struct vx_core core;
19
20 unsigned long port;
21
22 int mic_level; /* analog mic level (or boost) */
23
24 unsigned int regCDSP; /* current CDSP register */
25 unsigned int regDIALOG; /* current DIALOG register */
26
27 int index; /* card index */
28
29 /* pcmcia stuff */
30 struct pcmcia_device *p_dev;
31 };
32
33 #define to_vxpocket(x) container_of(x, struct snd_vxpocket, core)
34
35 extern const struct snd_vx_ops snd_vxpocket_ops;
36
37 void vx_set_mic_boost(struct vx_core *chip, int boost);
38 void vx_set_mic_level(struct vx_core *chip, int level);
39
40 int vxp_add_mic_controls(struct vx_core *chip);
41
42 /* Constants used to access the CDSP register (0x08). */
43 #define CDSP_MAGIC 0xA7 /* magic value (for read) */
44 /* for write */
45 #define VXP_CDSP_CLOCKIN_SEL_MASK 0x80 /* 0 (internal), 1 (AES/EBU) */
46 #define VXP_CDSP_DATAIN_SEL_MASK 0x40 /* 0 (analog), 1 (UER) */
47 #define VXP_CDSP_SMPTE_SEL_MASK 0x20
48 #define VXP_CDSP_RESERVED_MASK 0x10
49 #define VXP_CDSP_MIC_SEL_MASK 0x08
50 #define VXP_CDSP_VALID_IRQ_MASK 0x04
51 #define VXP_CDSP_CODEC_RESET_MASK 0x02
52 #define VXP_CDSP_DSP_RESET_MASK 0x01
53 /* VXPOCKET 240/440 */
54 #define P24_CDSP_MICS_SEL_MASK 0x18
55 #define P24_CDSP_MIC20_SEL_MASK 0x10
56 #define P24_CDSP_MIC38_SEL_MASK 0x08
57
58 /* Constants used to access the MEMIRQ register (0x0C). */
59 #define P44_MEMIRQ_MASTER_SLAVE_SEL_MASK 0x08
60 #define P44_MEMIRQ_SYNCED_ALONE_SEL_MASK 0x04
61 #define P44_MEMIRQ_WCLK_OUT_IN_SEL_MASK 0x02 /* Not used */
62 #define P44_MEMIRQ_WCLK_UER_SEL_MASK 0x01 /* Not used */
63
64 /* Micro levels (0x0C) */
65
66 /* Constants used to access the DIALOG register (0x0D). */
67 #define VXP_DLG_XILINX_REPROG_MASK 0x80 /* W */
68 #define VXP_DLG_DATA_XICOR_MASK 0x80 /* R */
69 #define VXP_DLG_RESERVED4_0_MASK 0x40
70 #define VXP_DLG_RESERVED2_0_MASK 0x20
71 #define VXP_DLG_RESERVED1_0_MASK 0x10
72 #define VXP_DLG_DMAWRITE_SEL_MASK 0x08 /* W */
73 #define VXP_DLG_DMAREAD_SEL_MASK 0x04 /* W */
74 #define VXP_DLG_MEMIRQ_MASK 0x02 /* R */
75 #define VXP_DLG_DMA16_SEL_MASK 0x02 /* W */
76 #define VXP_DLG_ACK_MEMIRQ_MASK 0x01 /* R/W */
77
78
79 #endif /* __VXPOCKET_H */
80
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