1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11 #ifndef __AMD_ACP_H
12 #define __AMD_ACP_H
13
14 #include <sound/pcm.h>
15 #include <sound/soc.h>
16 #include <sound/soc-acpi.h>
17 #include <sound/soc-dai.h>
18
19 #include "chip_offset_byte.h"
20
21 #define ACP3X_DEV 3
22 #define ACP6X_DEV 6
23 #define ACP63_DEV 0x63
24 #define ACP70_DEV 0x70
25
26 #define DMIC_INSTANCE 0x00
27 #define I2S_SP_INSTANCE 0x01
28 #define I2S_BT_INSTANCE 0x02
29 #define I2S_HS_INSTANCE 0x03
30
31 #define MEM_WINDOW_START 0x4080000
32
33 #define ACP_I2S_REG_START 0x1242400
34 #define ACP_I2S_REG_END 0x1242810
35 #define ACP3x_I2STDM_REG_START 0x1242400
36 #define ACP3x_I2STDM_REG_END 0x1242410
37 #define ACP3x_BT_TDM_REG_START 0x1242800
38 #define ACP3x_BT_TDM_REG_END 0x1242810
39
40 #define THRESHOLD(bit, base) ((bit) + (base))
41 #define I2S_RX_THRESHOLD(base) THRESHOLD(7, base)
42 #define I2S_TX_THRESHOLD(base) THRESHOLD(8, base)
43 #define BT_TX_THRESHOLD(base) THRESHOLD(6, base)
44 #define BT_RX_THRESHOLD(base) THRESHOLD(5, base)
45 #define HS_TX_THRESHOLD(base) THRESHOLD(4, base)
46 #define HS_RX_THRESHOLD(base) THRESHOLD(3, base)
47
48 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
49 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
50 #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
51 #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
52 #define ACP_SRAM_PDM_PTE_OFFSET 0x400
53 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
54 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
55 #define PAGE_SIZE_4K_ENABLE 0x2
56
57 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
58 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
59 #define I2S_BT_TX_MEM_WINDOW_START 0x4040000
60 #define I2S_BT_RX_MEM_WINDOW_START 0x4060000
61 #define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
62 #define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
63
64 #define SP_PB_FIFO_ADDR_OFFSET 0x500
65 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
66 #define BT_PB_FIFO_ADDR_OFFSET 0x900
67 #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
68 #define HS_PB_FIFO_ADDR_OFFSET 0xD00
69 #define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
70 #define PLAYBACK_MIN_NUM_PERIODS 2
71 #define PLAYBACK_MAX_NUM_PERIODS 8
72 #define PLAYBACK_MAX_PERIOD_SIZE 8192
73 #define PLAYBACK_MIN_PERIOD_SIZE 1024
74 #define CAPTURE_MIN_NUM_PERIODS 2
75 #define CAPTURE_MAX_NUM_PERIODS 8
76 #define CAPTURE_MAX_PERIOD_SIZE 8192
77 #define CAPTURE_MIN_PERIOD_SIZE 1024
78
79 #define MAX_BUFFER 65536
80 #define MIN_BUFFER MAX_BUFFER
81 #define FIFO_SIZE 0x100
82 #define DMA_SIZE 0x40
83 #define FRM_LEN 0x100
84
85 #define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
86
87 #define ACP_MAX_STREAM 8
88
89 #define TDM_ENABLE 1
90 #define TDM_DISABLE 0
91
92 #define SLOT_WIDTH_8 0x8
93 #define SLOT_WIDTH_16 0x10
94 #define SLOT_WIDTH_24 0x18
95 #define SLOT_WIDTH_32 0x20
96
97 #define ACP6X_PGFSM_CONTROL 0x1024
98 #define ACP6X_PGFSM_STATUS 0x1028
99
100 #define ACP63_PGFSM_CONTROL ACP6X_PGFSM_CONTROL
101 #define ACP63_PGFSM_STATUS ACP6X_PGFSM_STATUS
102
103 #define ACP70_PGFSM_CONTROL ACP6X_PGFSM_CONTROL
104 #define ACP70_PGFSM_STATUS ACP6X_PGFSM_STATUS
105
106 #define ACP_ZSC_DSP_CTRL 0x0001014
107 #define ACP_ZSC_STS 0x0001018
108 #define ACP_SOFT_RST_DONE_MASK 0x00010001
109
110 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0xffffffff
111 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
112 #define ACP_PGFSM_STATUS_MASK 0x03
113 #define ACP_POWERED_ON 0x00
114 #define ACP_POWER_ON_IN_PROGRESS 0x01
115 #define ACP_POWERED_OFF 0x02
116 #define ACP_POWER_OFF_IN_PROGRESS 0x03
117
118 #define ACP_ERROR_MASK 0x20000000
119 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xffffffff
120
121 #define ACP_TIMEOUT 500
122 #define DELAY_US 5
123 #define ACP_SUSPEND_DELAY_MS 2000
124
125 #define PDM_DMA_STAT 0x10
126 #define PDM_DMA_INTR_MASK 0x10000
127 #define PDM_DEC_64 0x2
128 #define PDM_CLK_FREQ_MASK 0x07
129 #define PDM_MISC_CTRL_MASK 0x10
130 #define PDM_ENABLE 0x01
131 #define PDM_DISABLE 0x00
132 #define DMA_EN_MASK 0x02
133 #define DELAY_US 5
134 #define PDM_TIMEOUT 1000
135 #define ACP_REGION2_OFFSET 0x02000000
136
137 struct acp_chip_info {
138 char *name; /* Platform name */
139 unsigned int acp_rev; /* ACP Revision id */
140 void __iomem *base; /* ACP memory PCI base */
141 struct platform_device *chip_pdev;
142 unsigned int flag; /* Distinguish b/w Legacy or Only PDM */
143 bool is_pdm_dev; /* flag set to true when ACP PDM controller exists */
144 bool is_pdm_config; /* flag set to true when PDM configuration is selected from BIOS */
145 bool is_i2s_config; /* flag set to true when I2S configuration is selected from BIOS */
146 };
147
148 struct acp_stream {
149 struct list_head list;
150 struct snd_pcm_substream *substream;
151 int irq_bit;
152 int dai_id;
153 int id;
154 int dir;
155 u64 bytescount;
156 u32 reg_offset;
157 u32 pte_offset;
158 u32 fifo_offset;
159 };
160
161 struct acp_resource {
162 int offset;
163 int no_of_ctrls;
164 int irqp_used;
165 bool soc_mclk;
166 u32 irq_reg_offset;
167 u64 scratch_reg_offset;
168 u64 sram_pte_offset;
169 };
170
171 struct acp_dev_data {
172 char *name;
173 struct device *dev;
174 void __iomem *acp_base;
175 unsigned int i2s_irq;
176
177 bool tdm_mode;
178 bool is_i2s_config;
179 /* SOC specific dais */
180 struct snd_soc_dai_driver *dai_driver;
181 int num_dai;
182
183 struct list_head stream_list;
184 spinlock_t acp_lock;
185
186 struct snd_soc_acpi_mach *machines;
187 struct platform_device *mach_dev;
188
189 u32 bclk_div;
190 u32 lrclk_div;
191
192 struct acp_resource *rsrc;
193 u32 ch_mask;
194 u32 tdm_tx_fmt[3];
195 u32 tdm_rx_fmt[3];
196 u32 xfer_tx_resolution[3];
197 u32 xfer_rx_resolution[3];
198 unsigned int flag;
199 unsigned int platform;
200 };
201
202 enum acp_config {
203 ACP_CONFIG_0 = 0,
204 ACP_CONFIG_1,
205 ACP_CONFIG_2,
206 ACP_CONFIG_3,
207 ACP_CONFIG_4,
208 ACP_CONFIG_5,
209 ACP_CONFIG_6,
210 ACP_CONFIG_7,
211 ACP_CONFIG_8,
212 ACP_CONFIG_9,
213 ACP_CONFIG_10,
214 ACP_CONFIG_11,
215 ACP_CONFIG_12,
216 ACP_CONFIG_13,
217 ACP_CONFIG_14,
218 ACP_CONFIG_15,
219 ACP_CONFIG_16,
220 ACP_CONFIG_17,
221 ACP_CONFIG_18,
222 ACP_CONFIG_19,
223 ACP_CONFIG_20,
224 };
225
226 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
227 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
228
229 int acp_platform_register(struct device *dev);
230 int acp_platform_unregister(struct device *dev);
231
232 int acp_machine_select(struct acp_dev_data *adata);
233
234 int smn_read(struct pci_dev *dev, u32 smn_addr);
235 int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data);
236
237 int acp_init(struct acp_chip_info *chip);
238 int acp_deinit(struct acp_chip_info *chip);
239 void acp_enable_interrupts(struct acp_dev_data *adata);
240 void acp_disable_interrupts(struct acp_dev_data *adata);
241 /* Machine configuration */
242 int snd_amd_acp_find_config(struct pci_dev *pci);
243
244 void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream);
245 void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size);
246 void restore_acp_pdm_params(struct snd_pcm_substream *substream,
247 struct acp_dev_data *adata);
248
249 int restore_acp_i2s_params(struct snd_pcm_substream *substream,
250 struct acp_dev_data *adata, struct acp_stream *stream);
251
252 void check_acp_config(struct pci_dev *pci, struct acp_chip_info *chip);
253
254 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
255 {
256 u64 byte_count = 0, low = 0, high = 0;
257
258 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
259 switch (dai_id) {
260 case I2S_BT_INSTANCE:
261 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
262 low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
263 break;
264 case I2S_SP_INSTANCE:
265 high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
266 low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
267 break;
268 case I2S_HS_INSTANCE:
269 high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
270 low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
271 break;
272 default:
273 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
274 goto POINTER_RETURN_BYTES;
275 }
276 } else {
277 switch (dai_id) {
278 case I2S_BT_INSTANCE:
279 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
280 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
281 break;
282 case I2S_SP_INSTANCE:
283 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
284 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
285 break;
286 case I2S_HS_INSTANCE:
287 high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
288 low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
289 break;
290 case DMIC_INSTANCE:
291 high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
292 low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
293 break;
294 default:
295 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
296 goto POINTER_RETURN_BYTES;
297 }
298 }
299 /* Get 64 bit value from two 32 bit registers */
300 byte_count = (high << 32) | low;
301
302 POINTER_RETURN_BYTES:
303 return byte_count;
304 }
305 #endif
306
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