1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * AMD ALSA SoC PDM Driver
4 *
5 * Copyright 2020 Advanced Micro Devices, Inc.
6 */
7
8 #include "rn_chip_offset_byte.h"
9
10 #define ACP_DEVS 3
11 #define ACP_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_REG_START 0x1240000
13 #define ACP_REG_END 0x1250200
14
15 #define ACP_DEVICE_ID 0x15E2
16 #define ACP_POWER_ON 0x00
17 #define ACP_POWER_ON_IN_PROGRESS 0x01
18 #define ACP_POWER_OFF 0x02
19 #define ACP_POWER_OFF_IN_PROGRESS 0x03
20 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
21
22 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
23 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
24 #define ACP_PGFSM_STATUS_MASK 0x03
25 #define ACP_POWERED_ON 0x00
26 #define ACP_POWER_ON_IN_PROGRESS 0x01
27 #define ACP_POWERED_OFF 0x02
28 #define ACP_POWER_OFF_IN_PROGRESS 0x03
29
30 #define ACP_ERROR_MASK 0x20000000
31 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
32 #define PDM_DMA_STAT 0x10
33 #define PDM_DMA_INTR_MASK 0x10000
34 #define ACP_ERROR_STAT 29
35 #define PDM_DECIMATION_FACTOR 0x2
36 #define ACP_PDM_CLK_FREQ_MASK 0x07
37 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)
38 #define ACP_PDM_ENABLE 0x01
39 #define ACP_PDM_DISABLE 0x00
40 #define ACP_PDM_DMA_EN_STATUS 0x02
41 #define TWO_CH 0x02
42 #define DELAY_US 5
43 #define ACP_COUNTER 20000
44 /* time in ms for runtime suspend delay */
45 #define ACP_SUSPEND_DELAY_MS 2000
46
47 #define ACP_SRAM_PTE_OFFSET 0x02050000
48 #define PAGE_SIZE_4K_ENABLE 0x2
49 #define MEM_WINDOW_START 0x4000000
50
51 #define CAPTURE_MIN_NUM_PERIODS 4
52 #define CAPTURE_MAX_NUM_PERIODS 4
53 #define CAPTURE_MAX_PERIOD_SIZE 8192
54 #define CAPTURE_MIN_PERIOD_SIZE 4096
55
56 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
57 #define MIN_BUFFER MAX_BUFFER
58 #define ACP_DMIC_AUTO -1
59
60 struct pdm_dev_data {
61 u32 pdm_irq;
62 void __iomem *acp_base;
63 struct snd_pcm_substream *capture_stream;
64 };
65
66 struct pdm_stream_instance {
67 u16 num_pages;
68 u16 channels;
69 dma_addr_t dma_addr;
70 u64 bytescount;
71 void __iomem *acp_base;
72 };
73
74 union acp_pdm_dma_count {
75 struct {
76 u32 low;
77 u32 high;
78 } bcount;
79 u64 bytescount;
80 };
81
82 static inline u32 rn_readl(void __iomem *base_addr)
83 {
84 return readl(base_addr - ACP_PHY_BASE_ADDRESS);
85 }
86
87 static inline void rn_writel(u32 val, void __iomem *base_addr)
88 {
89 writel(val, base_addr - ACP_PHY_BASE_ADDRESS);
90 }
91
92 /* Machine configuration */
93 int snd_amd_acp_find_config(struct pci_dev *pci);
94
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