1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ACP 3.1 Register Documentation 4 * 5 * Copyright 2020 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _rn_OFFSET_HEADER 9 #define _rn_OFFSET_HEADER 10 // Registers from ACP_DMA block 11 12 #define ACP_DMA_CNTL_0 0x1240000 13 #define ACP_DMA_CNTL_1 0x1240004 14 #define ACP_DMA_CNTL_2 0x1240008 15 #define ACP_DMA_CNTL_3 0x124000C 16 #define ACP_DMA_CNTL_4 0x1240010 17 #define ACP_DMA_CNTL_5 0x1240014 18 #define ACP_DMA_CNTL_6 0x1240018 19 #define ACP_DMA_CNTL_7 0x124001C 20 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020 21 #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024 22 #define ACP_DMA_DSCR_STRT_IDX_2 0x1240028 23 #define ACP_DMA_DSCR_STRT_IDX_3 0x124002C 24 #define ACP_DMA_DSCR_STRT_IDX_4 0x1240030 25 #define ACP_DMA_DSCR_STRT_IDX_5 0x1240034 26 #define ACP_DMA_DSCR_STRT_IDX_6 0x1240038 27 #define ACP_DMA_DSCR_STRT_IDX_7 0x124003C 28 #define ACP_DMA_DSCR_CNT_0 0x1240040 29 #define ACP_DMA_DSCR_CNT_1 0x1240044 30 #define ACP_DMA_DSCR_CNT_2 0x1240048 31 #define ACP_DMA_DSCR_CNT_3 0x124004C 32 #define ACP_DMA_DSCR_CNT_4 0x1240050 33 #define ACP_DMA_DSCR_CNT_5 0x1240054 34 #define ACP_DMA_DSCR_CNT_6 0x1240058 35 #define ACP_DMA_DSCR_CNT_7 0x124005C 36 #define ACP_DMA_PRIO_0 0x1240060 37 #define ACP_DMA_PRIO_1 0x1240064 38 #define ACP_DMA_PRIO_2 0x1240068 39 #define ACP_DMA_PRIO_3 0x124006C 40 #define ACP_DMA_PRIO_4 0x1240070 41 #define ACP_DMA_PRIO_5 0x1240074 42 #define ACP_DMA_PRIO_6 0x1240078 43 #define ACP_DMA_PRIO_7 0x124007C 44 #define ACP_DMA_CUR_DSCR_0 0x1240080 45 #define ACP_DMA_CUR_DSCR_1 0x1240084 46 #define ACP_DMA_CUR_DSCR_2 0x1240088 47 #define ACP_DMA_CUR_DSCR_3 0x124008C 48 #define ACP_DMA_CUR_DSCR_4 0x1240090 49 #define ACP_DMA_CUR_DSCR_5 0x1240094 50 #define ACP_DMA_CUR_DSCR_6 0x1240098 51 #define ACP_DMA_CUR_DSCR_7 0x124009C 52 #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0 53 #define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4 54 #define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8 55 #define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC 56 #define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0 57 #define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4 58 #define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8 59 #define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC 60 #define ACP_DMA_ERR_STS_0 0x12400C0 61 #define ACP_DMA_ERR_STS_1 0x12400C4 62 #define ACP_DMA_ERR_STS_2 0x12400C8 63 #define ACP_DMA_ERR_STS_3 0x12400CC 64 #define ACP_DMA_ERR_STS_4 0x12400D0 65 #define ACP_DMA_ERR_STS_5 0x12400D4 66 #define ACP_DMA_ERR_STS_6 0x12400D8 67 #define ACP_DMA_ERR_STS_7 0x12400DC 68 #define ACP_DMA_DESC_BASE_ADDR 0x12400E0 69 #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 70 #define ACP_DMA_CH_STS 0x12400E8 71 #define ACP_DMA_CH_GROUP 0x12400EC 72 #define ACP_DMA_CH_RST_STS 0x12400F0 73 74 // Registers from ACP_AXI2AXIATU block 75 76 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00 77 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04 78 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08 79 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C 80 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10 81 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14 82 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18 83 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C 84 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20 85 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24 86 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28 87 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C 88 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30 89 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34 90 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38 91 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C 92 #define ACPAXI2AXI_ATU_CTRL 0x1240C40 93 94 // Registers from ACP_CLKRST block 95 96 #define ACP_SOFT_RESET 0x1241000 97 #define ACP_CONTROL 0x1241004 98 #define ACP_STATUS 0x1241008 99 #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 100 101 // Registers from ACP_MISC block 102 103 #define ACP_EXTERNAL_INTR_ENB 0x1241800 104 #define ACP_EXTERNAL_INTR_CNTL 0x1241804 105 #define ACP_EXTERNAL_INTR_STAT 0x1241808 106 #define ACP_PGMEM_CTRL 0x12418C0 107 #define ACP_ERROR_STATUS 0x12418C4 108 #define ACP_SW_I2S_ERROR_REASON 0x12418C8 109 #define ACP_MEM_PG_STS 0x12418CC 110 111 // Registers from ACP_PGFSM block 112 113 #define ACP_I2S_PIN_CONFIG 0x1241400 114 #define ACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404 115 #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408 116 #define ACP_SW_PAD_KEEPER_EN 0x124140C 117 #define ACP_PGFSM_CONTROL 0x124141C 118 #define ACP_PGFSM_STATUS 0x1241420 119 #define ACP_CLKMUX_SEL 0x1241424 120 #define ACP_DEVICE_STATE 0x1241428 121 #define AZ_DEVICE_STATE 0x124142C 122 #define ACP_INTR_URGENCY_TIMER 0x1241430 123 #define AZ_INTR_URGENCY_TIMER 0x1241434 124 125 // Registers from ACP_SCRATCH block 126 127 #define ACP_SCRATCH_REG_0 0x1250000 128 #define ACP_SCRATCH_REG_1 0x1250004 129 #define ACP_SCRATCH_REG_2 0x1250008 130 #define ACP_SCRATCH_REG_3 0x125000C 131 #define ACP_SCRATCH_REG_4 0x1250010 132 #define ACP_SCRATCH_REG_5 0x1250014 133 #define ACP_SCRATCH_REG_6 0x1250018 134 #define ACP_SCRATCH_REG_7 0x125001C 135 #define ACP_SCRATCH_REG_8 0x1250020 136 #define ACP_SCRATCH_REG_9 0x1250024 137 #define ACP_SCRATCH_REG_10 0x1250028 138 #define ACP_SCRATCH_REG_11 0x125002C 139 #define ACP_SCRATCH_REG_12 0x1250030 140 #define ACP_SCRATCH_REG_13 0x1250034 141 #define ACP_SCRATCH_REG_14 0x1250038 142 #define ACP_SCRATCH_REG_15 0x125003C 143 #define ACP_SCRATCH_REG_16 0x1250040 144 #define ACP_SCRATCH_REG_17 0x1250044 145 #define ACP_SCRATCH_REG_18 0x1250048 146 #define ACP_SCRATCH_REG_19 0x125004C 147 #define ACP_SCRATCH_REG_20 0x1250050 148 #define ACP_SCRATCH_REG_21 0x1250054 149 #define ACP_SCRATCH_REG_22 0x1250058 150 #define ACP_SCRATCH_REG_23 0x125005C 151 #define ACP_SCRATCH_REG_24 0x1250060 152 #define ACP_SCRATCH_REG_25 0x1250064 153 #define ACP_SCRATCH_REG_26 0x1250068 154 #define ACP_SCRATCH_REG_27 0x125006C 155 #define ACP_SCRATCH_REG_28 0x1250070 156 #define ACP_SCRATCH_REG_29 0x1250074 157 #define ACP_SCRATCH_REG_30 0x1250078 158 #define ACP_SCRATCH_REG_31 0x125007C 159 #define ACP_SCRATCH_REG_32 0x1250080 160 #define ACP_SCRATCH_REG_33 0x1250084 161 #define ACP_SCRATCH_REG_34 0x1250088 162 #define ACP_SCRATCH_REG_35 0x125008C 163 #define ACP_SCRATCH_REG_36 0x1250090 164 #define ACP_SCRATCH_REG_37 0x1250094 165 #define ACP_SCRATCH_REG_38 0x1250098 166 #define ACP_SCRATCH_REG_39 0x125009C 167 #define ACP_SCRATCH_REG_40 0x12500A0 168 #define ACP_SCRATCH_REG_41 0x12500A4 169 #define ACP_SCRATCH_REG_42 0x12500A8 170 #define ACP_SCRATCH_REG_43 0x12500AC 171 #define ACP_SCRATCH_REG_44 0x12500B0 172 #define ACP_SCRATCH_REG_45 0x12500B4 173 #define ACP_SCRATCH_REG_46 0x12500B8 174 #define ACP_SCRATCH_REG_47 0x12500BC 175 #define ACP_SCRATCH_REG_48 0x12500C0 176 #define ACP_SCRATCH_REG_49 0x12500C4 177 #define ACP_SCRATCH_REG_50 0x12500C8 178 #define ACP_SCRATCH_REG_51 0x12500CC 179 #define ACP_SCRATCH_REG_52 0x12500D0 180 #define ACP_SCRATCH_REG_53 0x12500D4 181 #define ACP_SCRATCH_REG_54 0x12500D8 182 #define ACP_SCRATCH_REG_55 0x12500DC 183 #define ACP_SCRATCH_REG_56 0x12500E0 184 #define ACP_SCRATCH_REG_57 0x12500E4 185 #define ACP_SCRATCH_REG_58 0x12500E8 186 #define ACP_SCRATCH_REG_59 0x12500EC 187 #define ACP_SCRATCH_REG_60 0x12500F0 188 #define ACP_SCRATCH_REG_61 0x12500F4 189 #define ACP_SCRATCH_REG_62 0x12500F8 190 #define ACP_SCRATCH_REG_63 0x12500FC 191 #define ACP_SCRATCH_REG_64 0x1250100 192 #define ACP_SCRATCH_REG_65 0x1250104 193 #define ACP_SCRATCH_REG_66 0x1250108 194 #define ACP_SCRATCH_REG_67 0x125010C 195 #define ACP_SCRATCH_REG_68 0x1250110 196 #define ACP_SCRATCH_REG_69 0x1250114 197 #define ACP_SCRATCH_REG_70 0x1250118 198 #define ACP_SCRATCH_REG_71 0x125011C 199 #define ACP_SCRATCH_REG_72 0x1250120 200 #define ACP_SCRATCH_REG_73 0x1250124 201 #define ACP_SCRATCH_REG_74 0x1250128 202 #define ACP_SCRATCH_REG_75 0x125012C 203 #define ACP_SCRATCH_REG_76 0x1250130 204 #define ACP_SCRATCH_REG_77 0x1250134 205 #define ACP_SCRATCH_REG_78 0x1250138 206 #define ACP_SCRATCH_REG_79 0x125013C 207 #define ACP_SCRATCH_REG_80 0x1250140 208 #define ACP_SCRATCH_REG_81 0x1250144 209 #define ACP_SCRATCH_REG_82 0x1250148 210 #define ACP_SCRATCH_REG_83 0x125014C 211 #define ACP_SCRATCH_REG_84 0x1250150 212 #define ACP_SCRATCH_REG_85 0x1250154 213 #define ACP_SCRATCH_REG_86 0x1250158 214 #define ACP_SCRATCH_REG_87 0x125015C 215 #define ACP_SCRATCH_REG_88 0x1250160 216 #define ACP_SCRATCH_REG_89 0x1250164 217 #define ACP_SCRATCH_REG_90 0x1250168 218 #define ACP_SCRATCH_REG_91 0x125016C 219 #define ACP_SCRATCH_REG_92 0x1250170 220 #define ACP_SCRATCH_REG_93 0x1250174 221 #define ACP_SCRATCH_REG_94 0x1250178 222 #define ACP_SCRATCH_REG_95 0x125017C 223 #define ACP_SCRATCH_REG_96 0x1250180 224 #define ACP_SCRATCH_REG_97 0x1250184 225 #define ACP_SCRATCH_REG_98 0x1250188 226 #define ACP_SCRATCH_REG_99 0x125018C 227 #define ACP_SCRATCH_REG_100 0x1250190 228 #define ACP_SCRATCH_REG_101 0x1250194 229 #define ACP_SCRATCH_REG_102 0x1250198 230 #define ACP_SCRATCH_REG_103 0x125019C 231 #define ACP_SCRATCH_REG_104 0x12501A0 232 #define ACP_SCRATCH_REG_105 0x12501A4 233 #define ACP_SCRATCH_REG_106 0x12501A8 234 #define ACP_SCRATCH_REG_107 0x12501AC 235 #define ACP_SCRATCH_REG_108 0x12501B0 236 #define ACP_SCRATCH_REG_109 0x12501B4 237 #define ACP_SCRATCH_REG_110 0x12501B8 238 #define ACP_SCRATCH_REG_111 0x12501BC 239 #define ACP_SCRATCH_REG_112 0x12501C0 240 #define ACP_SCRATCH_REG_113 0x12501C4 241 #define ACP_SCRATCH_REG_114 0x12501C8 242 #define ACP_SCRATCH_REG_115 0x12501CC 243 #define ACP_SCRATCH_REG_116 0x12501D0 244 #define ACP_SCRATCH_REG_117 0x12501D4 245 #define ACP_SCRATCH_REG_118 0x12501D8 246 #define ACP_SCRATCH_REG_119 0x12501DC 247 #define ACP_SCRATCH_REG_120 0x12501E0 248 #define ACP_SCRATCH_REG_121 0x12501E4 249 #define ACP_SCRATCH_REG_122 0x12501E8 250 #define ACP_SCRATCH_REG_123 0x12501EC 251 #define ACP_SCRATCH_REG_124 0x12501F0 252 #define ACP_SCRATCH_REG_125 0x12501F4 253 #define ACP_SCRATCH_REG_126 0x12501F8 254 #define ACP_SCRATCH_REG_127 0x12501FC 255 #define ACP_SCRATCH_REG_128 0x1250200 256 257 // Registers from ACP_AUDIO_BUFFERS block 258 259 #define ACP_I2S_RX_RINGBUFADDR 0x1242000 260 #define ACP_I2S_RX_RINGBUFSIZE 0x1242004 261 #define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008 262 #define ACP_I2S_RX_FIFOADDR 0x124200C 263 #define ACP_I2S_RX_FIFOSIZE 0x1242010 264 #define ACP_I2S_RX_DMA_SIZE 0x1242014 265 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018 266 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C 267 #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020 268 #define ACP_I2S_TX_RINGBUFADDR 0x1242024 269 #define ACP_I2S_TX_RINGBUFSIZE 0x1242028 270 #define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C 271 #define ACP_I2S_TX_FIFOADDR 0x1242030 272 #define ACP_I2S_TX_FIFOSIZE 0x1242034 273 #define ACP_I2S_TX_DMA_SIZE 0x1242038 274 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C 275 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040 276 #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044 277 #define ACP_BT_RX_RINGBUFADDR 0x1242048 278 #define ACP_BT_RX_RINGBUFSIZE 0x124204C 279 #define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050 280 #define ACP_BT_RX_FIFOADDR 0x1242054 281 #define ACP_BT_RX_FIFOSIZE 0x1242058 282 #define ACP_BT_RX_DMA_SIZE 0x124205C 283 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060 284 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064 285 #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068 286 #define ACP_BT_TX_RINGBUFADDR 0x124206C 287 #define ACP_BT_TX_RINGBUFSIZE 0x1242070 288 #define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074 289 #define ACP_BT_TX_FIFOADDR 0x1242078 290 #define ACP_BT_TX_FIFOSIZE 0x124207C 291 #define ACP_BT_TX_DMA_SIZE 0x1242080 292 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084 293 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088 294 #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C 295 #define ACP_HS_RX_RINGBUFADDR 0x1242090 296 #define ACP_HS_RX_RINGBUFSIZE 0x1242094 297 #define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098 298 #define ACP_HS_RX_FIFOADDR 0x124209C 299 #define ACP_HS_RX_FIFOSIZE 0x12420A0 300 #define ACP_HS_RX_DMA_SIZE 0x12420A4 301 #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8 302 #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC 303 #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0 304 #define ACP_HS_TX_RINGBUFADDR 0x12420B4 305 #define ACP_HS_TX_RINGBUFSIZE 0x12420B8 306 #define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC 307 #define ACP_HS_TX_FIFOADDR 0x12420C0 308 #define ACP_HS_TX_FIFOSIZE 0x12420C4 309 #define ACP_HS_TX_DMA_SIZE 0x12420C8 310 #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC 311 #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0 312 #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4 313 314 // Registers from ACP_I2S_TDM block 315 316 #define ACP_I2STDM_IER 0x1242400 317 #define ACP_I2STDM_IRER 0x1242404 318 #define ACP_I2STDM_RXFRMT 0x1242408 319 #define ACP_I2STDM_ITER 0x124240C 320 #define ACP_I2STDM_TXFRMT 0x1242410 321 322 // Registers from ACP_BT_TDM block 323 324 #define ACP_BTTDM_IER 0x1242800 325 #define ACP_BTTDM_IRER 0x1242804 326 #define ACP_BTTDM_RXFRMT 0x1242808 327 #define ACP_BTTDM_ITER 0x124280C 328 #define ACP_BTTDM_TXFRMT 0x1242810 329 330 // Registers from ACP_WOV block 331 332 #define ACP_WOV_PDM_ENABLE 0x1242C04 333 #define ACP_WOV_PDM_DMA_ENABLE 0x1242C08 334 #define ACP_WOV_RX_RINGBUFADDR 0x1242C0C 335 #define ACP_WOV_RX_RINGBUFSIZE 0x1242C10 336 #define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14 337 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18 338 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C 339 #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20 340 #define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24 341 #define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28 342 #define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C 343 #define ACP_WOV_PDM_VAD_CTRL 0x1242C30 344 #define ACP_WOV_BUFFER_STATUS 0x1242C58 345 #define ACP_WOV_MISC_CTRL 0x1242C5C 346 #define ACP_WOV_CLK_CTRL 0x1242C60 347 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64 348 #define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68 349 #endif 350
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