1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ACP 5.x Register Documentation 4 * 5 * Copyright 2021 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _acp_ip_OFFSET_HEADER 9 #define _acp_ip_OFFSET_HEADER 10 11 /* Registers from ACP_DMA block */ 12 #define ACP_DMA_CNTL_0 0x1240000 13 #define ACP_DMA_CNTL_1 0x1240004 14 #define ACP_DMA_CNTL_2 0x1240008 15 #define ACP_DMA_CNTL_3 0x124000C 16 #define ACP_DMA_CNTL_4 0x1240010 17 #define ACP_DMA_CNTL_5 0x1240014 18 #define ACP_DMA_CNTL_6 0x1240018 19 #define ACP_DMA_CNTL_7 0x124001C 20 #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020 21 #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024 22 #define ACP_DMA_DSCR_STRT_IDX_2 0x1240028 23 #define ACP_DMA_DSCR_STRT_IDX_3 0x124002C 24 #define ACP_DMA_DSCR_STRT_IDX_4 0x1240030 25 #define ACP_DMA_DSCR_STRT_IDX_5 0x1240034 26 #define ACP_DMA_DSCR_STRT_IDX_6 0x1240038 27 #define ACP_DMA_DSCR_STRT_IDX_7 0x124003C 28 #define ACP_DMA_DSCR_CNT_0 0x1240040 29 #define ACP_DMA_DSCR_CNT_1 0x1240044 30 #define ACP_DMA_DSCR_CNT_2 0x1240048 31 #define ACP_DMA_DSCR_CNT_3 0x124004C 32 #define ACP_DMA_DSCR_CNT_4 0x1240050 33 #define ACP_DMA_DSCR_CNT_5 0x1240054 34 #define ACP_DMA_DSCR_CNT_6 0x1240058 35 #define ACP_DMA_DSCR_CNT_7 0x124005C 36 #define ACP_DMA_PRIO_0 0x1240060 37 #define ACP_DMA_PRIO_1 0x1240064 38 #define ACP_DMA_PRIO_2 0x1240068 39 #define ACP_DMA_PRIO_3 0x124006C 40 #define ACP_DMA_PRIO_4 0x1240070 41 #define ACP_DMA_PRIO_5 0x1240074 42 #define ACP_DMA_PRIO_6 0x1240078 43 #define ACP_DMA_PRIO_7 0x124007C 44 #define ACP_DMA_CUR_DSCR_0 0x1240080 45 #define ACP_DMA_CUR_DSCR_1 0x1240084 46 #define ACP_DMA_CUR_DSCR_2 0x1240088 47 #define ACP_DMA_CUR_DSCR_3 0x124008C 48 #define ACP_DMA_CUR_DSCR_4 0x1240090 49 #define ACP_DMA_CUR_DSCR_5 0x1240094 50 #define ACP_DMA_CUR_DSCR_6 0x1240098 51 #define ACP_DMA_CUR_DSCR_7 0x124009C 52 #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0 53 #define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4 54 #define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8 55 #define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC 56 #define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0 57 #define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4 58 #define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8 59 #define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC 60 #define ACP_DMA_ERR_STS_0 0x12400C0 61 #define ACP_DMA_ERR_STS_1 0x12400C4 62 #define ACP_DMA_ERR_STS_2 0x12400C8 63 #define ACP_DMA_ERR_STS_3 0x12400CC 64 #define ACP_DMA_ERR_STS_4 0x12400D0 65 #define ACP_DMA_ERR_STS_5 0x12400D4 66 #define ACP_DMA_ERR_STS_6 0x12400D8 67 #define ACP_DMA_ERR_STS_7 0x12400DC 68 #define ACP_DMA_DESC_BASE_ADDR 0x12400E0 69 #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 70 #define ACP_DMA_CH_STS 0x12400E8 71 #define ACP_DMA_CH_GROUP 0x12400EC 72 #define ACP_DMA_CH_RST_STS 0x12400F0 73 74 /* Registers from ACP_AXI2AXIATU block */ 75 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00 76 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04 77 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08 78 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C 79 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10 80 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14 81 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18 82 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C 83 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20 84 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24 85 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28 86 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C 87 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30 88 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34 89 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38 90 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C 91 #define ACPAXI2AXI_ATU_CTRL 0x1240C40 92 93 /* Registers from ACP_CLKRST block */ 94 #define ACP_SOFT_RESET 0x1241000 95 #define ACP_CONTROL 0x1241004 96 #define ACP_STATUS 0x1241008 97 #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 98 99 /* Registers from ACP_MISC block */ 100 #define ACP_EXTERNAL_INTR_ENB 0x1241800 101 #define ACP_EXTERNAL_INTR_CNTL 0x1241804 102 #define ACP_EXTERNAL_INTR_STAT 0x1241808 103 #define ACP_ERROR_STATUS 0x12418C4 104 #define ACP_SW_I2S_ERROR_REASON 0x12418C8 105 #define ACP_MEM_PG_STS 0x12418CC 106 #define ACP_PGMEM_DEEP_SLEEP_CTRL 0x12418D0 107 #define ACP_PGMEM_SHUT_DOWN_CTRL 0x12418D4 108 109 /* Registers from ACP_PGFSM block */ 110 #define ACP_PIN_CONFIG 0x1241400 111 #define ACP_PAD_PULLUP_CTRL 0x1241404 112 #define ACP_PAD_PULLDOWN_CTRL 0x1241408 113 #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124140C 114 #define ACP_PAD_SCHMEN_CTRL 0x1241410 115 #define ACP_SW_PAD_KEEPER_EN 0x1241414 116 #define ACP_SW_WAKE_EN 0x1241418 117 #define ACP_I2S_WAKE_EN 0x124141C 118 #define ACP_PME_EN 0x1241420 119 #define ACP_PGFSM_CONTROL 0x1241424 120 #define ACP_PGFSM_STATUS 0x1241428 121 #define ACP_CLKMUX_SEL 0x124142C 122 #define ACP_DEVICE_STATE 0x1241430 123 #define AZ_DEVICE_STATE 0x1241434 124 #define ACP_INTR_URGENCY_TIMER 0x1241438 125 #define AZ_INTR_URGENCY_TIMER 0x124143C 126 #define ACP_AON_SW_INTR_TRIG 0x1241440 127 128 /* Registers from ACP_SCRATCH block */ 129 #define ACP_SCRATCH_REG_0 0x1250000 130 #define ACP_SCRATCH_REG_1 0x1250004 131 #define ACP_SCRATCH_REG_2 0x1250008 132 #define ACP_SCRATCH_REG_3 0x125000C 133 #define ACP_SCRATCH_REG_4 0x1250010 134 #define ACP_SCRATCH_REG_5 0x1250014 135 #define ACP_SCRATCH_REG_6 0x1250018 136 #define ACP_SCRATCH_REG_7 0x125001C 137 #define ACP_SCRATCH_REG_8 0x1250020 138 #define ACP_SCRATCH_REG_9 0x1250024 139 #define ACP_SCRATCH_REG_10 0x1250028 140 #define ACP_SCRATCH_REG_11 0x125002C 141 #define ACP_SCRATCH_REG_12 0x1250030 142 #define ACP_SCRATCH_REG_13 0x1250034 143 #define ACP_SCRATCH_REG_14 0x1250038 144 #define ACP_SCRATCH_REG_15 0x125003C 145 #define ACP_SCRATCH_REG_16 0x1250040 146 #define ACP_SCRATCH_REG_17 0x1250044 147 #define ACP_SCRATCH_REG_18 0x1250048 148 #define ACP_SCRATCH_REG_19 0x125004C 149 #define ACP_SCRATCH_REG_20 0x1250050 150 #define ACP_SCRATCH_REG_21 0x1250054 151 #define ACP_SCRATCH_REG_22 0x1250058 152 #define ACP_SCRATCH_REG_23 0x125005C 153 #define ACP_SCRATCH_REG_24 0x1250060 154 #define ACP_SCRATCH_REG_25 0x1250064 155 #define ACP_SCRATCH_REG_26 0x1250068 156 #define ACP_SCRATCH_REG_27 0x125006C 157 #define ACP_SCRATCH_REG_28 0x1250070 158 #define ACP_SCRATCH_REG_29 0x1250074 159 #define ACP_SCRATCH_REG_30 0x1250078 160 #define ACP_SCRATCH_REG_31 0x125007C 161 #define ACP_SCRATCH_REG_32 0x1250080 162 #define ACP_SCRATCH_REG_33 0x1250084 163 #define ACP_SCRATCH_REG_34 0x1250088 164 #define ACP_SCRATCH_REG_35 0x125008C 165 #define ACP_SCRATCH_REG_36 0x1250090 166 #define ACP_SCRATCH_REG_37 0x1250094 167 #define ACP_SCRATCH_REG_38 0x1250098 168 #define ACP_SCRATCH_REG_39 0x125009C 169 #define ACP_SCRATCH_REG_40 0x12500A0 170 #define ACP_SCRATCH_REG_41 0x12500A4 171 #define ACP_SCRATCH_REG_42 0x12500A8 172 #define ACP_SCRATCH_REG_43 0x12500AC 173 #define ACP_SCRATCH_REG_44 0x12500B0 174 #define ACP_SCRATCH_REG_45 0x12500B4 175 #define ACP_SCRATCH_REG_46 0x12500B8 176 #define ACP_SCRATCH_REG_47 0x12500BC 177 #define ACP_SCRATCH_REG_48 0x12500C0 178 #define ACP_SCRATCH_REG_49 0x12500C4 179 #define ACP_SCRATCH_REG_50 0x12500C8 180 #define ACP_SCRATCH_REG_51 0x12500CC 181 #define ACP_SCRATCH_REG_52 0x12500D0 182 #define ACP_SCRATCH_REG_53 0x12500D4 183 #define ACP_SCRATCH_REG_54 0x12500D8 184 #define ACP_SCRATCH_REG_55 0x12500DC 185 #define ACP_SCRATCH_REG_56 0x12500E0 186 #define ACP_SCRATCH_REG_57 0x12500E4 187 #define ACP_SCRATCH_REG_58 0x12500E8 188 #define ACP_SCRATCH_REG_59 0x12500EC 189 #define ACP_SCRATCH_REG_60 0x12500F0 190 #define ACP_SCRATCH_REG_61 0x12500F4 191 #define ACP_SCRATCH_REG_62 0x12500F8 192 #define ACP_SCRATCH_REG_63 0x12500FC 193 #define ACP_SCRATCH_REG_64 0x1250100 194 #define ACP_SCRATCH_REG_65 0x1250104 195 #define ACP_SCRATCH_REG_66 0x1250108 196 #define ACP_SCRATCH_REG_67 0x125010C 197 #define ACP_SCRATCH_REG_68 0x1250110 198 #define ACP_SCRATCH_REG_69 0x1250114 199 #define ACP_SCRATCH_REG_70 0x1250118 200 #define ACP_SCRATCH_REG_71 0x125011C 201 #define ACP_SCRATCH_REG_72 0x1250120 202 #define ACP_SCRATCH_REG_73 0x1250124 203 #define ACP_SCRATCH_REG_74 0x1250128 204 #define ACP_SCRATCH_REG_75 0x125012C 205 #define ACP_SCRATCH_REG_76 0x1250130 206 #define ACP_SCRATCH_REG_77 0x1250134 207 #define ACP_SCRATCH_REG_78 0x1250138 208 #define ACP_SCRATCH_REG_79 0x125013C 209 #define ACP_SCRATCH_REG_80 0x1250140 210 #define ACP_SCRATCH_REG_81 0x1250144 211 #define ACP_SCRATCH_REG_82 0x1250148 212 #define ACP_SCRATCH_REG_83 0x125014C 213 #define ACP_SCRATCH_REG_84 0x1250150 214 #define ACP_SCRATCH_REG_85 0x1250154 215 #define ACP_SCRATCH_REG_86 0x1250158 216 #define ACP_SCRATCH_REG_87 0x125015C 217 #define ACP_SCRATCH_REG_88 0x1250160 218 #define ACP_SCRATCH_REG_89 0x1250164 219 #define ACP_SCRATCH_REG_90 0x1250168 220 #define ACP_SCRATCH_REG_91 0x125016C 221 #define ACP_SCRATCH_REG_92 0x1250170 222 #define ACP_SCRATCH_REG_93 0x1250174 223 #define ACP_SCRATCH_REG_94 0x1250178 224 #define ACP_SCRATCH_REG_95 0x125017C 225 #define ACP_SCRATCH_REG_96 0x1250180 226 #define ACP_SCRATCH_REG_97 0x1250184 227 #define ACP_SCRATCH_REG_98 0x1250188 228 #define ACP_SCRATCH_REG_99 0x125018C 229 #define ACP_SCRATCH_REG_100 0x1250190 230 #define ACP_SCRATCH_REG_101 0x1250194 231 #define ACP_SCRATCH_REG_102 0x1250198 232 #define ACP_SCRATCH_REG_103 0x125019C 233 #define ACP_SCRATCH_REG_104 0x12501A0 234 #define ACP_SCRATCH_REG_105 0x12501A4 235 #define ACP_SCRATCH_REG_106 0x12501A8 236 #define ACP_SCRATCH_REG_107 0x12501AC 237 #define ACP_SCRATCH_REG_108 0x12501B0 238 #define ACP_SCRATCH_REG_109 0x12501B4 239 #define ACP_SCRATCH_REG_110 0x12501B8 240 #define ACP_SCRATCH_REG_111 0x12501BC 241 #define ACP_SCRATCH_REG_112 0x12501C0 242 #define ACP_SCRATCH_REG_113 0x12501C4 243 #define ACP_SCRATCH_REG_114 0x12501C8 244 #define ACP_SCRATCH_REG_115 0x12501CC 245 #define ACP_SCRATCH_REG_116 0x12501D0 246 #define ACP_SCRATCH_REG_117 0x12501D4 247 #define ACP_SCRATCH_REG_118 0x12501D8 248 #define ACP_SCRATCH_REG_119 0x12501DC 249 #define ACP_SCRATCH_REG_120 0x12501E0 250 #define ACP_SCRATCH_REG_121 0x12501E4 251 #define ACP_SCRATCH_REG_122 0x12501E8 252 #define ACP_SCRATCH_REG_123 0x12501EC 253 #define ACP_SCRATCH_REG_124 0x12501F0 254 #define ACP_SCRATCH_REG_125 0x12501F4 255 #define ACP_SCRATCH_REG_126 0x12501F8 256 #define ACP_SCRATCH_REG_127 0x12501FC 257 #define ACP_SCRATCH_REG_128 0x1250200 258 259 /* Registers from ACP_AUDIO_BUFFERS block */ 260 #define ACP_I2S_RX_RINGBUFADDR 0x1242000 261 #define ACP_I2S_RX_RINGBUFSIZE 0x1242004 262 #define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008 263 #define ACP_I2S_RX_FIFOADDR 0x124200C 264 #define ACP_I2S_RX_FIFOSIZE 0x1242010 265 #define ACP_I2S_RX_DMA_SIZE 0x1242014 266 #define ACP_I2S_RX_LINEARPOSCNTR_HIGH 0x1242018 267 #define ACP_I2S_RX_LINEARPOSCNTR_LOW 0x124201C 268 #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020 269 #define ACP_I2S_TX_RINGBUFADDR 0x1242024 270 #define ACP_I2S_TX_RINGBUFSIZE 0x1242028 271 #define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C 272 #define ACP_I2S_TX_FIFOADDR 0x1242030 273 #define ACP_I2S_TX_FIFOSIZE 0x1242034 274 #define ACP_I2S_TX_DMA_SIZE 0x1242038 275 #define ACP_I2S_TX_LINEARPOSCNTR_HIGH 0x124203C 276 #define ACP_I2S_TX_LINEARPOSCNTR_LOW 0x1242040 277 #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044 278 #define ACP_BT_RX_RINGBUFADDR 0x1242048 279 #define ACP_BT_RX_RINGBUFSIZE 0x124204C 280 #define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050 281 #define ACP_BT_RX_FIFOADDR 0x1242054 282 #define ACP_BT_RX_FIFOSIZE 0x1242058 283 #define ACP_BT_RX_DMA_SIZE 0x124205C 284 #define ACP_BT_RX_LINEARPOSCNTR_HIGH 0x1242060 285 #define ACP_BT_RX_LINEARPOSCNTR_LOW 0x1242064 286 #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068 287 #define ACP_BT_TX_RINGBUFADDR 0x124206C 288 #define ACP_BT_TX_RINGBUFSIZE 0x1242070 289 #define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074 290 #define ACP_BT_TX_FIFOADDR 0x1242078 291 #define ACP_BT_TX_FIFOSIZE 0x124207C 292 #define ACP_BT_TX_DMA_SIZE 0x1242080 293 #define ACP_BT_TX_LINEARPOSCNTR_HIGH 0x1242084 294 #define ACP_BT_TX_LINEARPOSCNTR_LOW 0x1242088 295 #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C 296 #define ACP_HS_RX_RINGBUFADDR 0x1242090 297 #define ACP_HS_RX_RINGBUFSIZE 0x1242094 298 #define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098 299 #define ACP_HS_RX_FIFOADDR 0x124209C 300 #define ACP_HS_RX_FIFOSIZE 0x12420A0 301 #define ACP_HS_RX_DMA_SIZE 0x12420A4 302 #define ACP_HS_RX_LINEARPOSCNTR_HIGH 0x12420A8 303 #define ACP_HS_RX_LINEARPOSCNTR_LOW 0x12420AC 304 #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0 305 #define ACP_HS_TX_RINGBUFADDR 0x12420B4 306 #define ACP_HS_TX_RINGBUFSIZE 0x12420B8 307 #define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC 308 #define ACP_HS_TX_FIFOADDR 0x12420C0 309 #define ACP_HS_TX_FIFOSIZE 0x12420C4 310 #define ACP_HS_TX_DMA_SIZE 0x12420C8 311 #define ACP_HS_TX_LINEARPOSCNTR_HIGH 0x12420CC 312 #define ACP_HS_TX_LINEARPOSCNTR_LOW 0x12420D0 313 #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4 314 315 /* Registers from ACP_I2S_TDM block */ 316 #define ACP_I2STDM_IER 0x1242400 317 #define ACP_I2STDM_IRER 0x1242404 318 #define ACP_I2STDM_RXFRMT 0x1242408 319 #define ACP_I2STDM_ITER 0x124240C 320 #define ACP_I2STDM_TXFRMT 0x1242410 321 #define ACP_I2STDM0_MSTRCLKGEN 0x1242414 322 #define ACP_I2STDM1_MSTRCLKGEN 0x1242418 323 #define ACP_I2STDM2_MSTRCLKGEN 0x124241C 324 #define ACP_I2STDM_REFCLKGEN 0x1242420 325 326 /* Registers from ACP_BT_TDM block */ 327 #define ACP_BTTDM_IER 0x1242800 328 #define ACP_BTTDM_IRER 0x1242804 329 #define ACP_BTTDM_RXFRMT 0x1242808 330 #define ACP_BTTDM_ITER 0x124280C 331 #define ACP_BTTDM_TXFRMT 0x1242810 332 #define ACP_HSTDM_IER 0x1242814 333 #define ACP_HSTDM_IRER 0x1242818 334 #define ACP_HSTDM_RXFRMT 0x124281C 335 #define ACP_HSTDM_ITER 0x1242820 336 #define ACP_HSTDM_TXFRMT 0x1242824 337 #endif 338
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