1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // aw88261.h -- AW88261 ALSA SoC Audio driver
4 //
5 // Copyright (c) 2023 awinic Technology CO., LTD
6 //
7 // Author: Jimmy Zhang <zhangjianming@awinic.com>
8 // Author: Weidong Wang <wangweidong.a@awinic.com>
9 //
10
11 #ifndef __AW88261_H__
12 #define __AW88261_H__
13
14 #define AW88261_ID_REG (0x00)
15 #define AW88261_SYSST_REG (0x01)
16 #define AW88261_SYSINT_REG (0x02)
17 #define AW88261_SYSINTM_REG (0x03)
18 #define AW88261_SYSCTRL_REG (0x04)
19 #define AW88261_SYSCTRL2_REG (0x05)
20 #define AW88261_I2SCTRL1_REG (0x06)
21 #define AW88261_I2SCTRL2_REG (0x07)
22 #define AW88261_I2SCTRL3_REG (0x08)
23 #define AW88261_DACCFG1_REG (0x09)
24 #define AW88261_DACCFG2_REG (0x0A)
25 #define AW88261_DACCFG3_REG (0x0B)
26 #define AW88261_DACCFG4_REG (0x0C)
27 #define AW88261_DACCFG5_REG (0x0D)
28 #define AW88261_DACCFG6_REG (0x0E)
29 #define AW88261_DACCFG7_REG (0x0F)
30 #define AW88261_DACCFG8_REG (0x10)
31 #define AW88261_PWMCTRL1_REG (0x11)
32 #define AW88261_PWMCTRL2_REG (0x12)
33 #define AW88261_I2SCFG1_REG (0x13)
34 #define AW88261_DBGCTRL_REG (0x14)
35 #define AW88261_DACCFG9_REG (0x15)
36 #define AW88261_DACCFG10_REG (0x16)
37 #define AW88261_DACST_REG (0x20)
38 #define AW88261_VBAT_REG (0x21)
39 #define AW88261_TEMP_REG (0x22)
40 #define AW88261_PVDD_REG (0x23)
41 #define AW88261_ISNDAT_REG (0x24)
42 #define AW88261_VSNDAT_REG (0x25)
43 #define AW88261_I2SINT_REG (0x26)
44 #define AW88261_I2SCAPCNT_REG (0x27)
45 #define AW88261_ANASTA1_REG (0x28)
46 #define AW88261_ANASTA2_REG (0x29)
47 #define AW88261_ANASTA3_REG (0x2A)
48 #define AW88261_TESTDET_REG (0x2B)
49 #define AW88261_DSMCFG1_REG (0x30)
50 #define AW88261_DSMCFG2_REG (0x31)
51 #define AW88261_DSMCFG3_REG (0x32)
52 #define AW88261_DSMCFG4_REG (0x33)
53 #define AW88261_DSMCFG5_REG (0x34)
54 #define AW88261_DSMCFG6_REG (0x35)
55 #define AW88261_DSMCFG7_REG (0x36)
56 #define AW88261_DSMCFG8_REG (0x37)
57 #define AW88261_TESTIN_REG (0x38)
58 #define AW88261_TESTOUT_REG (0x39)
59 #define AW88261_SADCCTRL1_REG (0x3A)
60 #define AW88261_SADCCTRL2_REG (0x3B)
61 #define AW88261_SADCCTRL3_REG (0x3C)
62 #define AW88261_SADCCTRL4_REG (0x3D)
63 #define AW88261_SADCCTRL5_REG (0x3E)
64 #define AW88261_SADCCTRL6_REG (0x3F)
65 #define AW88261_SADCCTRL7_REG (0x40)
66 #define AW88261_VSNTM1_REG (0x50)
67 #define AW88261_VSNTM2_REG (0x51)
68 #define AW88261_ISNCTRL1_REG (0x52)
69 #define AW88261_ISNCTRL2_REG (0x53)
70 #define AW88261_PLLCTRL1_REG (0x54)
71 #define AW88261_PLLCTRL2_REG (0x55)
72 #define AW88261_PLLCTRL3_REG (0x56)
73 #define AW88261_CDACTRL1_REG (0x57)
74 #define AW88261_CDACTRL2_REG (0x58)
75 #define AW88261_DITHERCFG1_REG (0x59)
76 #define AW88261_DITHERCFG2_REG (0x5A)
77 #define AW88261_DITHERCFG3_REG (0x5B)
78 #define AW88261_CPCTRL_REG (0x5C)
79 #define AW88261_BSTCTRL1_REG (0x60)
80 #define AW88261_BSTCTRL2_REG (0x61)
81 #define AW88261_BSTCTRL3_REG (0x62)
82 #define AW88261_BSTCTRL4_REG (0x63)
83 #define AW88261_BSTCTRL5_REG (0x64)
84 #define AW88261_BSTCTRL6_REG (0x65)
85 #define AW88261_BSTCTRL7_REG (0x66)
86 #define AW88261_BSTCTRL8_REG (0x67)
87 #define AW88261_BSTCTRL9_REG (0x68)
88 #define AW88261_TM_REG (0x6F)
89 #define AW88261_TESTCTRL1_REG (0x70)
90 #define AW88261_TESTCTRL2_REG (0x71)
91 #define AW88261_EFCTRL1_REG (0x72)
92 #define AW88261_EFCTRL2_REG (0x73)
93 #define AW88261_EFWH_REG (0x74)
94 #define AW88261_EFWM2_REG (0x75)
95 #define AW88261_EFWM1_REG (0x76)
96 #define AW88261_EFWL_REG (0x77)
97 #define AW88261_EFRH4_REG (0x78)
98 #define AW88261_EFRH3_REG (0x79)
99 #define AW88261_EFRH2_REG (0x7A)
100 #define AW88261_EFRH1_REG (0x7B)
101 #define AW88261_EFRL4_REG (0x7C)
102 #define AW88261_EFRL3_REG (0x7D)
103 #define AW88261_EFRL2_REG (0x7E)
104 #define AW88261_EFRL1_REG (0x7F)
105
106 #define AW88261_REG_MAX (0x80)
107 #define AW88261_EF_DBMD_MASK (0xfff7)
108 #define AW88261_OR_VALUE (0x0008)
109
110 #define AW88261_TEMH_MASK (0x83ff)
111 #define AW88261_TEML_MASK (0x83ff)
112 #define AW88261_DEFAULT_CFG (0x0000)
113
114 #define AW88261_ICALK_SHIFT (0)
115 #define AW88261_ICALKL_SHIFT (0)
116 #define AW88261_VCALK_SHIFT (0)
117 #define AW88261_VCALKL_SHIFT (0)
118
119 #define AW88261_AMPPD_START_BIT (1)
120 #define AW88261_AMPPD_BITS_LEN (1)
121 #define AW88261_AMPPD_MASK \
122 (~(((1<<AW88261_AMPPD_BITS_LEN)-1) << AW88261_AMPPD_START_BIT))
123
124 #define AW88261_UVLS_START_BIT (14)
125 #define AW88261_UVLS_NORMAL (0)
126 #define AW88261_UVLS_NORMAL_VALUE \
127 (AW88261_UVLS_NORMAL << AW88261_UVLS_START_BIT)
128
129 #define AW88261_BSTOCS_START_BIT (11)
130 #define AW88261_BSTOCS_OVER_CURRENT (1)
131 #define AW88261_BSTOCS_OVER_CURRENT_VALUE \
132 (AW88261_BSTOCS_OVER_CURRENT << AW88261_BSTOCS_START_BIT)
133
134 #define AW88261_BSTS_START_BIT (9)
135 #define AW88261_BSTS_FINISHED (1)
136 #define AW88261_BSTS_FINISHED_VALUE \
137 (AW88261_BSTS_FINISHED << AW88261_BSTS_START_BIT)
138
139 #define AW88261_SWS_START_BIT (8)
140 #define AW88261_SWS_SWITCHING (1)
141 #define AW88261_SWS_SWITCHING_VALUE \
142 (AW88261_SWS_SWITCHING << AW88261_SWS_START_BIT)
143
144 #define AW88261_NOCLKS_START_BIT (5)
145 #define AW88261_NOCLKS_NO_CLOCK (1)
146 #define AW88261_NOCLKS_NO_CLOCK_VALUE \
147 (AW88261_NOCLKS_NO_CLOCK << AW88261_NOCLKS_START_BIT)
148
149 #define AW88261_CLKS_START_BIT (4)
150 #define AW88261_CLKS_STABLE (1)
151 #define AW88261_CLKS_STABLE_VALUE \
152 (AW88261_CLKS_STABLE << AW88261_CLKS_START_BIT)
153
154 #define AW88261_OCDS_START_BIT (3)
155 #define AW88261_OCDS_OC (1)
156 #define AW88261_OCDS_OC_VALUE \
157 (AW88261_OCDS_OC << AW88261_OCDS_START_BIT)
158
159 #define AW88261_OTHS_START_BIT (1)
160 #define AW88261_OTHS_OT (1)
161 #define AW88261_OTHS_OT_VALUE \
162 (AW88261_OTHS_OT << AW88261_OTHS_START_BIT)
163
164 #define AW88261_PLLS_START_BIT (0)
165 #define AW88261_PLLS_LOCKED (1)
166 #define AW88261_PLLS_LOCKED_VALUE \
167 (AW88261_PLLS_LOCKED << AW88261_PLLS_START_BIT)
168
169 #define AW88261_BIT_PLL_CHECK \
170 (AW88261_CLKS_STABLE_VALUE | \
171 AW88261_PLLS_LOCKED_VALUE)
172
173 #define AW88261_BIT_SYSST_CHECK_MASK \
174 (~(AW88261_UVLS_NORMAL_VALUE | \
175 AW88261_BSTOCS_OVER_CURRENT_VALUE | \
176 AW88261_BSTS_FINISHED_VALUE | \
177 AW88261_SWS_SWITCHING_VALUE | \
178 AW88261_NOCLKS_NO_CLOCK_VALUE | \
179 AW88261_CLKS_STABLE_VALUE | \
180 AW88261_OCDS_OC_VALUE | \
181 AW88261_OTHS_OT_VALUE | \
182 AW88261_PLLS_LOCKED_VALUE))
183
184 #define AW88261_BIT_SYSST_CHECK \
185 (AW88261_BSTS_FINISHED_VALUE | \
186 AW88261_SWS_SWITCHING_VALUE | \
187 AW88261_CLKS_STABLE_VALUE | \
188 AW88261_PLLS_LOCKED_VALUE)
189
190 #define AW88261_ULS_HMUTE_START_BIT (14)
191 #define AW88261_ULS_HMUTE_BITS_LEN (1)
192 #define AW88261_ULS_HMUTE_MASK \
193 (~(((1<<AW88261_ULS_HMUTE_BITS_LEN)-1) << AW88261_ULS_HMUTE_START_BIT))
194
195 #define AW88261_ULS_HMUTE_DISABLE (0)
196 #define AW88261_ULS_HMUTE_DISABLE_VALUE \
197 (AW88261_ULS_HMUTE_DISABLE << AW88261_ULS_HMUTE_START_BIT)
198
199 #define AW88261_ULS_HMUTE_ENABLE (1)
200 #define AW88261_ULS_HMUTE_ENABLE_VALUE \
201 (AW88261_ULS_HMUTE_ENABLE << AW88261_ULS_HMUTE_START_BIT)
202
203 #define AW88261_HMUTE_START_BIT (8)
204 #define AW88261_HMUTE_BITS_LEN (1)
205 #define AW88261_HMUTE_MASK \
206 (~(((1<<AW88261_HMUTE_BITS_LEN)-1) << AW88261_HMUTE_START_BIT))
207
208 #define AW88261_HMUTE_DISABLE (0)
209 #define AW88261_HMUTE_DISABLE_VALUE \
210 (AW88261_HMUTE_DISABLE << AW88261_HMUTE_START_BIT)
211
212 #define AW88261_HMUTE_ENABLE (1)
213 #define AW88261_HMUTE_ENABLE_VALUE \
214 (AW88261_HMUTE_ENABLE << AW88261_HMUTE_START_BIT)
215
216 #define AW88261_AMPPD_START_BIT (1)
217 #define AW88261_AMPPD_BITS_LEN (1)
218 #define AW88261_AMPPD_MASK \
219 (~(((1<<AW88261_AMPPD_BITS_LEN)-1) << AW88261_AMPPD_START_BIT))
220
221 #define AW88261_AMPPD_WORKING (0)
222 #define AW88261_AMPPD_WORKING_VALUE \
223 (AW88261_AMPPD_WORKING << AW88261_AMPPD_START_BIT)
224
225 #define AW88261_AMPPD_POWER_DOWN (1)
226 #define AW88261_AMPPD_POWER_DOWN_VALUE \
227 (AW88261_AMPPD_POWER_DOWN << AW88261_AMPPD_START_BIT)
228
229 #define AW88261_PWDN_START_BIT (0)
230 #define AW88261_PWDN_BITS_LEN (1)
231 #define AW88261_PWDN_MASK \
232 (~(((1<<AW88261_PWDN_BITS_LEN)-1) << AW88261_PWDN_START_BIT))
233
234 #define AW88261_PWDN_WORKING (0)
235 #define AW88261_PWDN_WORKING_VALUE \
236 (AW88261_PWDN_WORKING << AW88261_PWDN_START_BIT)
237
238 #define AW88261_PWDN_POWER_DOWN (1)
239 #define AW88261_PWDN_POWER_DOWN_VALUE \
240 (AW88261_PWDN_POWER_DOWN << AW88261_PWDN_START_BIT)
241
242 #define AW88261_MUTE_VOL (90 * 8)
243 #define AW88261_VOLUME_STEP_DB (6 * 8)
244
245 #define AW88261_VOL_6DB_START (6)
246
247 #define AW88261_VOL_START_BIT (0)
248 #define AW88261_VOL_BITS_LEN (10)
249 #define AW88261_VOL_MASK \
250 (~(((1<<AW88261_VOL_BITS_LEN)-1) << AW88261_VOL_START_BIT))
251
252 #define AW88261_VOL_DEFAULT_VALUE (0)
253
254 #define AW88261_I2STXEN_START_BIT (6)
255 #define AW88261_I2STXEN_BITS_LEN (1)
256 #define AW88261_I2STXEN_MASK \
257 (~(((1<<AW88261_I2STXEN_BITS_LEN)-1) << AW88261_I2STXEN_START_BIT))
258
259 #define AW88261_I2STXEN_DISABLE (0)
260 #define AW88261_I2STXEN_DISABLE_VALUE \
261 (AW88261_I2STXEN_DISABLE << AW88261_I2STXEN_START_BIT)
262
263 #define AW88261_I2STXEN_ENABLE (1)
264 #define AW88261_I2STXEN_ENABLE_VALUE \
265 (AW88261_I2STXEN_ENABLE << AW88261_I2STXEN_START_BIT)
266
267 #define AW88261_CCO_MUX_START_BIT (14)
268 #define AW88261_CCO_MUX_BITS_LEN (1)
269 #define AW88261_CCO_MUX_MASK \
270 (~(((1<<AW88261_CCO_MUX_BITS_LEN)-1) << AW88261_CCO_MUX_START_BIT))
271
272 #define AW88261_CCO_MUX_DIVIDED (0)
273 #define AW88261_CCO_MUX_DIVIDED_VALUE \
274 (AW88261_CCO_MUX_DIVIDED << AW88261_CCO_MUX_START_BIT)
275
276 #define AW88261_CCO_MUX_BYPASS (1)
277 #define AW88261_CCO_MUX_BYPASS_VALUE \
278 (AW88261_CCO_MUX_BYPASS << AW88261_CCO_MUX_START_BIT)
279
280 #define AW88261_EF_VSN_GESLP_H_START_BIT (0)
281 #define AW88261_EF_VSN_GESLP_H_BITS_LEN (10)
282 #define AW88261_EF_VSN_GESLP_H_MASK \
283 (~(((1<<AW88261_EF_VSN_GESLP_H_BITS_LEN)-1) << AW88261_EF_VSN_GESLP_H_START_BIT))
284
285 #define AW88261_EF_VSN_GESLP_L_START_BIT (0)
286 #define AW88261_EF_VSN_GESLP_L_BITS_LEN (10)
287 #define AW88261_EF_VSN_GESLP_L_MASK \
288 (~(((1<<AW88261_EF_VSN_GESLP_L_BITS_LEN)-1) << AW88261_EF_VSN_GESLP_L_START_BIT))
289
290 #define AW88261_FORCE_PWM_START_BIT (12)
291 #define AW88261_FORCE_PWM_BITS_LEN (1)
292 #define AW88261_FORCE_PWM_MASK \
293 (~(((1<<AW88261_FORCE_PWM_BITS_LEN)-1) << AW88261_FORCE_PWM_START_BIT))
294
295 #define AW88261_FORCE_PWM_FORCEMINUS_PWM (1)
296 #define AW88261_FORCE_PWM_FORCEMINUS_PWM_VALUE \
297 (AW88261_FORCE_PWM_FORCEMINUS_PWM << AW88261_FORCE_PWM_START_BIT)
298
299 #define AW88261_BST_OS_WIDTH_START_BIT (0)
300 #define AW88261_BST_OS_WIDTH_BITS_LEN (3)
301 #define AW88261_BST_OS_WIDTH_MASK \
302 (~(((1<<AW88261_BST_OS_WIDTH_BITS_LEN)-1) << AW88261_BST_OS_WIDTH_START_BIT))
303
304 #define AW88261_BST_OS_WIDTH_50NS (4)
305 #define AW88261_BST_OS_WIDTH_50NS_VALUE \
306 (AW88261_BST_OS_WIDTH_50NS << AW88261_BST_OS_WIDTH_START_BIT)
307
308 /* BST_LOOPR bit 1:0 (BSTCTRL6 0x65) */
309 #define AW88261_BST_LOOPR_START_BIT (0)
310 #define AW88261_BST_LOOPR_BITS_LEN (2)
311 #define AW88261_BST_LOOPR_MASK \
312 (~(((1<<AW88261_BST_LOOPR_BITS_LEN)-1) << AW88261_BST_LOOPR_START_BIT))
313
314 #define AW88261_BST_LOOPR_340K (2)
315 #define AW88261_BST_LOOPR_340K_VALUE \
316 (AW88261_BST_LOOPR_340K << AW88261_BST_LOOPR_START_BIT)
317
318 /* RSQN_DLY bit 15:14 (BSTCTRL7 0x66) */
319 #define AW88261_RSQN_DLY_START_BIT (14)
320 #define AW88261_RSQN_DLY_BITS_LEN (2)
321 #define AW88261_RSQN_DLY_MASK \
322 (~(((1<<AW88261_RSQN_DLY_BITS_LEN)-1) << AW88261_RSQN_DLY_START_BIT))
323
324 #define AW88261_RSQN_DLY_35NS (2)
325 #define AW88261_RSQN_DLY_35NS_VALUE \
326 (AW88261_RSQN_DLY_35NS << AW88261_RSQN_DLY_START_BIT)
327
328 /* BURST_SSMODE bit 3 (BSTCTRL8 0x67) */
329 #define AW88261_BURST_SSMODE_START_BIT (3)
330 #define AW88261_BURST_SSMODE_BITS_LEN (1)
331 #define AW88261_BURST_SSMODE_MASK \
332 (~(((1<<AW88261_BURST_SSMODE_BITS_LEN)-1) << AW88261_BURST_SSMODE_START_BIT))
333
334 #define AW88261_BURST_SSMODE_FAST (0)
335 #define AW88261_BURST_SSMODE_FAST_VALUE \
336 (AW88261_BURST_SSMODE_FAST << AW88261_BURST_SSMODE_START_BIT)
337
338 /* BST_BURST bit 9:7 (BSTCTRL9 0x68) */
339 #define AW88261_BST_BURST_START_BIT (7)
340 #define AW88261_BST_BURST_BITS_LEN (3)
341 #define AW88261_BST_BURST_MASK \
342 (~(((1<<AW88261_BST_BURST_BITS_LEN)-1) << AW88261_BST_BURST_START_BIT))
343
344 #define AW88261_BST_BURST_30MA (2)
345 #define AW88261_BST_BURST_30MA_VALUE \
346 (AW88261_BST_BURST_30MA << AW88261_BST_BURST_START_BIT)
347
348 #define AW88261_EF_VSN_GESLP_SIGN_MASK (~0x0200)
349 #define AW88261_EF_VSN_GESLP_NEG (~0xfc00)
350
351 #define AW88261_EF_ISN_GESLP_SIGN_MASK (~0x0200)
352 #define AW88261_EF_ISN_GESLP_NEG (~0xfc00)
353
354 #define AW88261_EF_ISN_GESLP_H_START_BIT (0)
355 #define AW88261_EF_ISN_GESLP_H_BITS_LEN (10)
356 #define AW88261_EF_ISN_GESLP_H_MASK \
357 (~(((1<<AW88261_EF_ISN_GESLP_H_BITS_LEN)-1) << AW88261_EF_ISN_GESLP_H_START_BIT))
358
359 #define AW88261_EF_ISN_GESLP_L_START_BIT (0)
360 #define AW88261_EF_ISN_GESLP_L_BITS_LEN (10)
361 #define AW88261_EF_ISN_GESLP_L_MASK \
362 (~(((1<<AW88261_EF_ISN_GESLP_L_BITS_LEN)-1) << AW88261_EF_ISN_GESLP_L_START_BIT))
363
364 #define AW88261_CABL_BASE_VALUE (1000)
365 #define AW88261_ICABLK_FACTOR (1)
366 #define AW88261_VCABLK_FACTOR (1)
367
368 #define AW88261_VCAL_FACTOR (1<<13)
369
370 #define AW88261_START_RETRIES (5)
371 #define AW88261_START_WORK_DELAY_MS (0)
372
373 #define AW88261_I2C_NAME "aw88261"
374
375 #define AW88261_RATES (SNDRV_PCM_RATE_8000_48000 | \
376 SNDRV_PCM_RATE_96000)
377 #define AW88261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
378 SNDRV_PCM_FMTBIT_S24_LE | \
379 SNDRV_PCM_FMTBIT_S32_LE)
380
381 #define FADE_TIME_MAX 100000
382 #define FADE_TIME_MIN 0
383
384 #define AW88261_DEV_DEFAULT_CH (0)
385 #define AW88261_ACF_FILE "aw88261_acf.bin"
386 #define AW88261_DEV_SYSST_CHECK_MAX (10)
387 #define AW88261_SOFT_RESET_VALUE (0x55aa)
388 #define AW88261_REG_TO_DB (0x3f)
389 #define AW88261_VOL_START_MASK (0xfc00)
390 #define AW88261_INIT_PROFILE (0)
391
392 #define REG_VAL_TO_DB(value) ((((value) >> AW88261_VOL_6DB_START) * \
393 AW88261_VOLUME_STEP_DB) + \
394 ((value) & AW88261_REG_TO_DB))
395 #define DB_TO_REG_VAL(value) ((((value) / AW88261_VOLUME_STEP_DB) << \
396 AW88261_VOL_6DB_START) + \
397 ((value) % AW88261_VOLUME_STEP_DB))
398
399 #define AW88261_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
400 { \
401 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
402 .name = xname, \
403 .info = profile_info, \
404 .get = profile_get, \
405 .put = profile_set, \
406 }
407
408 enum {
409 AW88261_SYNC_START = 0,
410 AW88261_ASYNC_START,
411 };
412
413 enum aw88261_id {
414 AW88261_CHIP_ID = 0x2113,
415 };
416
417 enum {
418 AW88261_500_US = 500,
419 AW88261_1000_US = 1000,
420 AW88261_2000_US = 2000,
421 };
422
423 enum {
424 AW88261_DEV_PW_OFF = 0,
425 AW88261_DEV_PW_ON,
426 };
427
428 enum {
429 AW88261_DEV_FW_FAILED = 0,
430 AW88261_DEV_FW_OK,
431 };
432
433 enum {
434 AW88261_EF_AND_CHECK = 0,
435 AW88261_EF_OR_CHECK,
436 };
437
438 enum {
439 AW88261_FRCSET_DISABLE = 0,
440 AW88261_FRCSET_ENABLE,
441 };
442
443 struct aw88261 {
444 struct aw_device *aw_pa;
445 struct mutex lock;
446 struct gpio_desc *reset_gpio;
447 struct delayed_work start_work;
448 struct regmap *regmap;
449 struct aw_container *aw_cfg;
450
451 int efuse_check;
452 int frcset_en;
453 unsigned int mute_st;
454 unsigned int amppd_st;
455
456 bool phase_sync;
457 };
458
459 #endif
460
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