1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // aw88399.h -- ALSA SoC AW88399 codec support
4 //
5 // Copyright (c) 2023 AWINIC Technology CO., LTD
6 //
7 // Author: Weidong Wang <wangweidong.a@awinic.com>
8 //
9
10 #ifndef __AW88399_H__
11 #define __AW88399_H__
12
13 /* registers list */
14 #define AW88399_ID_REG (0x00)
15 #define AW88399_SYSST_REG (0x01)
16 #define AW88399_SYSINT_REG (0x02)
17 #define AW88399_SYSINTM_REG (0x03)
18 #define AW88399_SYSCTRL_REG (0x04)
19 #define AW88399_SYSCTRL2_REG (0x05)
20 #define AW88399_I2SCTRL1_REG (0x06)
21 #define AW88399_I2SCTRL2_REG (0x07)
22 #define AW88399_I2SCTRL3_REG (0x08)
23 #define AW88399_DACCFG1_REG (0x09)
24 #define AW88399_DACCFG2_REG (0x0A)
25 #define AW88399_DACCFG3_REG (0x0B)
26 #define AW88399_DACCFG4_REG (0x0C)
27 #define AW88399_DACCFG5_REG (0x0D)
28 #define AW88399_DACCFG6_REG (0x0E)
29 #define AW88399_DACCFG7_REG (0x0F)
30 #define AW88399_MPDCFG1_REG (0x10)
31 #define AW88399_MPDCFG2_REG (0x11)
32 #define AW88399_MPDCFG3_REG (0x12)
33 #define AW88399_MPDCFG4_REG (0x13)
34 #define AW88399_PWMCTRL1_REG (0x14)
35 #define AW88399_PWMCTRL2_REG (0x15)
36 #define AW88399_PWMCTRL3_REG (0x16)
37 #define AW88399_I2SCFG1_REG (0x17)
38 #define AW88399_DBGCTRL_REG (0x18)
39 #define AW88399_HAGCST_REG (0x20)
40 #define AW88399_VBAT_REG (0x21)
41 #define AW88399_TEMP_REG (0x22)
42 #define AW88399_PVDD_REG (0x23)
43 #define AW88399_ISNDAT_REG (0x24)
44 #define AW88399_VSNDAT_REG (0x25)
45 #define AW88399_I2SINT_REG (0x26)
46 #define AW88399_I2SCAPCNT_REG (0x27)
47 #define AW88399_ANASTA1_REG (0x28)
48 #define AW88399_ANASTA2_REG (0x29)
49 #define AW88399_ANASTA3_REG (0x2A)
50 #define AW88399_TESTDET_REG (0x2B)
51 #define AW88399_DSMCFG1_REG (0x30)
52 #define AW88399_DSMCFG2_REG (0x31)
53 #define AW88399_DSMCFG3_REG (0x32)
54 #define AW88399_DSMCFG4_REG (0x33)
55 #define AW88399_DSMCFG5_REG (0x34)
56 #define AW88399_DSMCFG6_REG (0x35)
57 #define AW88399_DSMCFG7_REG (0x36)
58 #define AW88399_DSMCFG8_REG (0x37)
59 #define AW88399_TESTIN_REG (0x38)
60 #define AW88399_TESTOUT_REG (0x39)
61 #define AW88399_MEMTEST_REG (0x3A)
62 #define AW88399_VSNCTRL1_REG (0x3B)
63 #define AW88399_ISNCTRL1_REG (0x3C)
64 #define AW88399_ISNCTRL2_REG (0x3D)
65 #define AW88399_DSPMADD_REG (0x40)
66 #define AW88399_DSPMDAT_REG (0x41)
67 #define AW88399_WDT_REG (0x42)
68 #define AW88399_ACR1_REG (0x43)
69 #define AW88399_ACR2_REG (0x44)
70 #define AW88399_ASR1_REG (0x45)
71 #define AW88399_ASR2_REG (0x46)
72 #define AW88399_DSPCFG_REG (0x47)
73 #define AW88399_ASR3_REG (0x48)
74 #define AW88399_ASR4_REG (0x49)
75 #define AW88399_DSPVCALB_REG (0x4A)
76 #define AW88399_CRCCTRL_REG (0x4B)
77 #define AW88399_DSPDBG1_REG (0x4C)
78 #define AW88399_DSPDBG2_REG (0x4D)
79 #define AW88399_DSPDBG3_REG (0x4E)
80 #define AW88399_PLLCTRL1_REG (0x50)
81 #define AW88399_PLLCTRL2_REG (0x51)
82 #define AW88399_PLLCTRL3_REG (0x52)
83 #define AW88399_CDACTRL1_REG (0x53)
84 #define AW88399_CDACTRL2_REG (0x54)
85 #define AW88399_CDACTRL3_REG (0x55)
86 #define AW88399_SADCCTRL1_REG (0x56)
87 #define AW88399_SADCCTRL2_REG (0x57)
88 #define AW88399_BOPCTRL1_REG (0x58)
89 #define AW88399_BOPCTRL2_REG (0x5A)
90 #define AW88399_BOPCTRL3_REG (0x5B)
91 #define AW88399_BOPCTRL4_REG (0x5C)
92 #define AW88399_BOPCTRL5_REG (0x5D)
93 #define AW88399_BOPCTRL6_REG (0x5E)
94 #define AW88399_BOPCTRL7_REG (0x5F)
95 #define AW88399_BSTCTRL1_REG (0x60)
96 #define AW88399_BSTCTRL2_REG (0x61)
97 #define AW88399_BSTCTRL3_REG (0x62)
98 #define AW88399_BSTCTRL4_REG (0x63)
99 #define AW88399_BSTCTRL5_REG (0x64)
100 #define AW88399_BSTCTRL6_REG (0x65)
101 #define AW88399_BSTCTRL7_REG (0x66)
102 #define AW88399_BSTCTRL8_REG (0x67)
103 #define AW88399_BSTCTRL9_REG (0x68)
104 #define AW88399_BSTCTRL10_REG (0x69)
105 #define AW88399_CPCTRL_REG (0x6A)
106 #define AW88399_EFWH_REG (0x6C)
107 #define AW88399_EFWM2_REG (0x6D)
108 #define AW88399_EFWM1_REG (0x6E)
109 #define AW88399_EFWL_REG (0x6F)
110 #define AW88399_TESTCTRL1_REG (0x70)
111 #define AW88399_TESTCTRL2_REG (0x71)
112 #define AW88399_EFCTRL1_REG (0x72)
113 #define AW88399_EFCTRL2_REG (0x73)
114 #define AW88399_EFRH4_REG (0x74)
115 #define AW88399_EFRH3_REG (0x75)
116 #define AW88399_EFRH2_REG (0x76)
117 #define AW88399_EFRH1_REG (0x77)
118 #define AW88399_EFRL4_REG (0x78)
119 #define AW88399_EFRL3_REG (0x79)
120 #define AW88399_EFRL2_REG (0x7A)
121 #define AW88399_EFRL1_REG (0x7B)
122 #define AW88399_TM_REG (0x7C)
123 #define AW88399_TM2_REG (0x7D)
124
125 #define AW88399_REG_MAX (0x7E)
126 #define AW88399_MUTE_VOL (1023)
127
128 #define AW88399_DSP_CFG_ADDR (0x9B00)
129 #define AW88399_DSP_REG_CFG_ADPZ_RA (0x9B68)
130 #define AW88399_DSP_FW_ADDR (0x8980)
131 #define AW88399_DSP_ROM_CHECK_ADDR (0x1F40)
132 #define AW88399_DSP_ROM_CHECK_DATA (0x4638)
133
134 #define AW88399_CALI_RE_HBITS_MASK (~(0xFFFF0000))
135 #define AW88399_CALI_RE_HBITS_SHIFT (16)
136
137 #define AW88399_CALI_RE_LBITS_MASK (~(0xFFFF))
138 #define AW88399_CALI_RE_LBITS_SHIFT (0)
139
140 #define AW88399_I2STXEN_START_BIT (9)
141 #define AW88399_I2STXEN_BITS_LEN (1)
142 #define AW88399_I2STXEN_MASK \
143 (~(((1<<AW88399_I2STXEN_BITS_LEN)-1) << AW88399_I2STXEN_START_BIT))
144
145 #define AW88399_I2STXEN_DISABLE (0)
146 #define AW88399_I2STXEN_DISABLE_VALUE \
147 (AW88399_I2STXEN_DISABLE << AW88399_I2STXEN_START_BIT)
148
149 #define AW88399_I2STXEN_ENABLE (1)
150 #define AW88399_I2STXEN_ENABLE_VALUE \
151 (AW88399_I2STXEN_ENABLE << AW88399_I2STXEN_START_BIT)
152
153 #define AW88399_VOL_START_BIT (0)
154 #define AW88399_VOL_BITS_LEN (10)
155 #define AW88399_VOL_MASK \
156 (~(((1<<AW88399_VOL_BITS_LEN)-1) << AW88399_VOL_START_BIT))
157
158 #define AW88399_PWDN_START_BIT (0)
159 #define AW88399_PWDN_BITS_LEN (1)
160 #define AW88399_PWDN_MASK \
161 (~(((1<<AW88399_PWDN_BITS_LEN)-1) << AW88399_PWDN_START_BIT))
162
163 #define AW88399_PWDN_POWER_DOWN (1)
164 #define AW88399_PWDN_POWER_DOWN_VALUE \
165 (AW88399_PWDN_POWER_DOWN << AW88399_PWDN_START_BIT)
166
167 #define AW88399_PWDN_WORKING (0)
168 #define AW88399_PWDN_WORKING_VALUE \
169 (AW88399_PWDN_WORKING << AW88399_PWDN_START_BIT)
170
171 #define AW88399_DSPBY_START_BIT (2)
172 #define AW88399_DSPBY_BITS_LEN (1)
173 #define AW88399_DSPBY_MASK \
174 (~(((1<<AW88399_DSPBY_BITS_LEN)-1) << AW88399_DSPBY_START_BIT))
175
176 #define AW88399_DSPBY_WORKING (0)
177 #define AW88399_DSPBY_WORKING_VALUE \
178 (AW88399_DSPBY_WORKING << AW88399_DSPBY_START_BIT)
179
180 #define AW88399_DSPBY_BYPASS (1)
181 #define AW88399_DSPBY_BYPASS_VALUE \
182 (AW88399_DSPBY_BYPASS << AW88399_DSPBY_START_BIT)
183
184 #define AW88399_MEM_CLKSEL_START_BIT (3)
185 #define AW88399_MEM_CLKSEL_BITS_LEN (1)
186 #define AW88399_MEM_CLKSEL_MASK \
187 (~(((1<<AW88399_MEM_CLKSEL_BITS_LEN)-1) << AW88399_MEM_CLKSEL_START_BIT))
188
189 #define AW88399_MEM_CLKSEL_OSCCLK (0)
190 #define AW88399_MEM_CLKSEL_OSCCLK_VALUE \
191 (AW88399_MEM_CLKSEL_OSCCLK << AW88399_MEM_CLKSEL_START_BIT)
192
193 #define AW88399_MEM_CLKSEL_DAPHCLK (1)
194 #define AW88399_MEM_CLKSEL_DAPHCLK_VALUE \
195 (AW88399_MEM_CLKSEL_DAPHCLK << AW88399_MEM_CLKSEL_START_BIT)
196
197 #define AW88399_DITHER_EN_START_BIT (15)
198 #define AW88399_DITHER_EN_BITS_LEN (1)
199 #define AW88399_DITHER_EN_MASK \
200 (~(((1<<AW88399_DITHER_EN_BITS_LEN)-1) << AW88399_DITHER_EN_START_BIT))
201
202 #define AW88399_DITHER_EN_DISABLE (0)
203 #define AW88399_DITHER_EN_DISABLE_VALUE \
204 (AW88399_DITHER_EN_DISABLE << AW88399_DITHER_EN_START_BIT)
205
206 #define AW88399_DITHER_EN_ENABLE (1)
207 #define AW88399_DITHER_EN_ENABLE_VALUE \
208 (AW88399_DITHER_EN_ENABLE << AW88399_DITHER_EN_START_BIT)
209
210 #define AW88399_HMUTE_START_BIT (8)
211 #define AW88399_HMUTE_BITS_LEN (1)
212 #define AW88399_HMUTE_MASK \
213 (~(((1<<AW88399_HMUTE_BITS_LEN)-1) << AW88399_HMUTE_START_BIT))
214
215 #define AW88399_HMUTE_DISABLE (0)
216 #define AW88399_HMUTE_DISABLE_VALUE \
217 (AW88399_HMUTE_DISABLE << AW88399_HMUTE_START_BIT)
218
219 #define AW88399_HMUTE_ENABLE (1)
220 #define AW88399_HMUTE_ENABLE_VALUE \
221 (AW88399_HMUTE_ENABLE << AW88399_HMUTE_START_BIT)
222
223 #define AW88399_EF_DBMD_START_BIT (2)
224 #define AW88399_EF_DBMD_BITS_LEN (1)
225 #define AW88399_EF_DBMD_MASK \
226 (~(((1<<AW88399_EF_DBMD_BITS_LEN)-1) << AW88399_EF_DBMD_START_BIT))
227
228 #define AW88399_EF_DBMD_OR (1)
229 #define AW88399_EF_DBMD_OR_VALUE \
230 (AW88399_EF_DBMD_OR << AW88399_EF_DBMD_START_BIT)
231
232 #define AW88399_VDSEL_START_BIT (5)
233 #define AW88399_VDSEL_BITS_LEN (1)
234 #define AW88399_VDSEL_MASK \
235 (~(((1<<AW88399_VDSEL_BITS_LEN)-1) << AW88399_VDSEL_START_BIT))
236
237 #define AW88399_EF_ISN_GESLP_H_START_BIT (0)
238 #define AW88399_EF_ISN_GESLP_H_BITS_LEN (10)
239 #define AW88399_EF_ISN_GESLP_H_MASK \
240 (~(((1<<AW88399_EF_ISN_GESLP_H_BITS_LEN)-1) << AW88399_EF_ISN_GESLP_H_START_BIT))
241
242 /* EF_VSN_GESLP_H bit 9:0 (EFRH3 0x75) */
243 #define AW88399_EF_VSN_GESLP_H_START_BIT (0)
244 #define AW88399_EF_VSN_GESLP_H_BITS_LEN (10)
245 #define AW88399_EF_VSN_GESLP_H_MASK \
246 (~(((1<<AW88399_EF_VSN_GESLP_H_BITS_LEN)-1) << AW88399_EF_VSN_GESLP_H_START_BIT))
247
248 #define AW88399_EF_ISN_GESLP_L_START_BIT (0)
249 #define AW88399_EF_ISN_GESLP_L_BITS_LEN (10)
250 #define AW88399_EF_ISN_GESLP_L_MASK \
251 (~(((1<<AW88399_EF_ISN_GESLP_L_BITS_LEN)-1) << AW88399_EF_ISN_GESLP_L_START_BIT))
252
253 /* EF_VSN_GESLP_L bit 9:0 (EFRL3 0x79) */
254 #define AW88399_EF_VSN_GESLP_L_START_BIT (0)
255 #define AW88399_EF_VSN_GESLP_L_BITS_LEN (10)
256 #define AW88399_EF_VSN_GESLP_L_MASK \
257 (~(((1<<AW88399_EF_VSN_GESLP_L_BITS_LEN)-1) << AW88399_EF_VSN_GESLP_L_START_BIT))
258
259 #define AW88399_INTERNAL_VSN_TRIM_H_START_BIT (9)
260 #define AW88399_INTERNAL_VSN_TRIM_H_BITS_LEN (6)
261 #define AW88399_INTERNAL_VSN_TRIM_H_MASK \
262 (~(((1<<AW88399_INTERNAL_VSN_TRIM_H_BITS_LEN)-1) << AW88399_INTERNAL_VSN_TRIM_H_START_BIT))
263
264 #define AW88399_INTERNAL_VSN_TRIM_L_START_BIT (9)
265 #define AW88399_INTERNAL_VSN_TRIM_L_BITS_LEN (6)
266 #define AW88399_INTERNAL_VSN_TRIM_L_MASK \
267 (~(((1<<AW88399_INTERNAL_VSN_TRIM_L_BITS_LEN)-1) << AW88399_INTERNAL_VSN_TRIM_L_START_BIT))
268
269 #define AW88399_RCV_MODE_START_BIT (7)
270 #define AW88399_RCV_MODE_BITS_LEN (1)
271 #define AW88399_RCV_MODE_MASK \
272 (~(((1<<AW88399_RCV_MODE_BITS_LEN)-1) << AW88399_RCV_MODE_START_BIT))
273
274 #define AW88399_CLKI_START_BIT (4)
275 #define AW88399_NOCLKI_START_BIT (5)
276 #define AW88399_PLLI_START_BIT (0)
277 #define AW88399_PLLI_INT_VALUE (1)
278 #define AW88399_PLLI_INT_INTERRUPT \
279 (AW88399_PLLI_INT_VALUE << AW88399_PLLI_START_BIT)
280
281 #define AW88399_CLKI_INT_VALUE (1)
282 #define AW88399_CLKI_INT_INTERRUPT \
283 (AW88399_CLKI_INT_VALUE << AW88399_CLKI_START_BIT)
284
285 #define AW88399_NOCLKI_INT_VALUE (1)
286 #define AW88399_NOCLKI_INT_INTERRUPT \
287 (AW88399_NOCLKI_INT_VALUE << AW88399_NOCLKI_START_BIT)
288
289 #define AW88399_BIT_SYSINT_CHECK \
290 (AW88399_PLLI_INT_INTERRUPT | \
291 AW88399_CLKI_INT_INTERRUPT | \
292 AW88399_NOCLKI_INT_INTERRUPT)
293
294 #define AW88399_CRC_CHECK_START_BIT (12)
295 #define AW88399_CRC_CHECK_BITS_LEN (3)
296 #define AW88399_CRC_CHECK_BITS_MASK \
297 (~(((1<<AW88399_CRC_CHECK_BITS_LEN)-1) << AW88399_CRC_CHECK_START_BIT))
298
299 #define AW88399_RCV_MODE_RECEIVER (1)
300 #define AW88399_RCV_MODE_RECEIVER_VALUE \
301 (AW88399_RCV_MODE_RECEIVER << AW88399_RCV_MODE_START_BIT)
302
303 #define AW88399_AMPPD_START_BIT (1)
304 #define AW88399_AMPPD_BITS_LEN (1)
305 #define AW88399_AMPPD_MASK \
306 (~(((1<<AW88399_AMPPD_BITS_LEN)-1) << AW88399_AMPPD_START_BIT))
307
308 #define AW88399_AMPPD_WORKING (0)
309 #define AW88399_AMPPD_WORKING_VALUE \
310 (AW88399_AMPPD_WORKING << AW88399_AMPPD_START_BIT)
311
312 #define AW88399_AMPPD_POWER_DOWN (1)
313 #define AW88399_AMPPD_POWER_DOWN_VALUE \
314 (AW88399_AMPPD_POWER_DOWN << AW88399_AMPPD_START_BIT)
315
316 #define AW88399_RAM_CG_BYP_START_BIT (0)
317 #define AW88399_RAM_CG_BYP_BITS_LEN (1)
318 #define AW88399_RAM_CG_BYP_MASK \
319 (~(((1<<AW88399_RAM_CG_BYP_BITS_LEN)-1) << AW88399_RAM_CG_BYP_START_BIT))
320
321 #define AW88399_RAM_CG_BYP_WORK (0)
322 #define AW88399_RAM_CG_BYP_WORK_VALUE \
323 (AW88399_RAM_CG_BYP_WORK << AW88399_RAM_CG_BYP_START_BIT)
324
325 #define AW88399_RAM_CG_BYP_BYPASS (1)
326 #define AW88399_RAM_CG_BYP_BYPASS_VALUE \
327 (AW88399_RAM_CG_BYP_BYPASS << AW88399_RAM_CG_BYP_START_BIT)
328
329 #define AW88399_CRC_END_ADDR_START_BIT (0)
330 #define AW88399_CRC_END_ADDR_BITS_LEN (12)
331 #define AW88399_CRC_END_ADDR_MASK \
332 (~(((1<<AW88399_CRC_END_ADDR_BITS_LEN)-1) << AW88399_CRC_END_ADDR_START_BIT))
333
334 #define AW88399_CRC_CODE_EN_START_BIT (13)
335 #define AW88399_CRC_CODE_EN_BITS_LEN (1)
336 #define AW88399_CRC_CODE_EN_MASK \
337 (~(((1<<AW88399_CRC_CODE_EN_BITS_LEN)-1) << AW88399_CRC_CODE_EN_START_BIT))
338
339 #define AW88399_CRC_CODE_EN_DISABLE (0)
340 #define AW88399_CRC_CODE_EN_DISABLE_VALUE \
341 (AW88399_CRC_CODE_EN_DISABLE << AW88399_CRC_CODE_EN_START_BIT)
342
343 #define AW88399_CRC_CODE_EN_ENABLE (1)
344 #define AW88399_CRC_CODE_EN_ENABLE_VALUE \
345 (AW88399_CRC_CODE_EN_ENABLE << AW88399_CRC_CODE_EN_START_BIT)
346
347 #define AW88399_CRC_CFG_EN_START_BIT (12)
348 #define AW88399_CRC_CFG_EN_BITS_LEN (1)
349 #define AW88399_CRC_CFG_EN_MASK \
350 (~(((1<<AW88399_CRC_CFG_EN_BITS_LEN)-1) << AW88399_CRC_CFG_EN_START_BIT))
351
352 #define AW88399_CRC_CFG_EN_DISABLE (0)
353 #define AW88399_CRC_CFG_EN_DISABLE_VALUE \
354 (AW88399_CRC_CFG_EN_DISABLE << AW88399_CRC_CFG_EN_START_BIT)
355
356 #define AW88399_CRC_CFG_EN_ENABLE (1)
357 #define AW88399_CRC_CFG_EN_ENABLE_VALUE \
358 (AW88399_CRC_CFG_EN_ENABLE << AW88399_CRC_CFG_EN_START_BIT)
359
360 #define AW88399_OCDS_START_BIT (3)
361 #define AW88399_OCDS_OC (1)
362 #define AW88399_OCDS_OC_VALUE \
363 (AW88399_OCDS_OC << AW88399_OCDS_START_BIT)
364
365 #define AW88399_NOCLKS_START_BIT (5)
366 #define AW88399_NOCLKS_NO_CLOCK (1)
367 #define AW88399_NOCLKS_NO_CLOCK_VALUE \
368 (AW88399_NOCLKS_NO_CLOCK << AW88399_NOCLKS_START_BIT)
369
370 #define AW88399_SWS_START_BIT (8)
371 #define AW88399_SWS_SWITCHING (1)
372 #define AW88399_SWS_SWITCHING_VALUE \
373 (AW88399_SWS_SWITCHING << AW88399_SWS_START_BIT)
374
375 #define AW88399_BSTS_START_BIT (9)
376 #define AW88399_BSTS_FINISHED (1)
377 #define AW88399_BSTS_FINISHED_VALUE \
378 (AW88399_BSTS_FINISHED << AW88399_BSTS_START_BIT)
379
380 #define AW88399_UVLS_START_BIT (14)
381 #define AW88399_UVLS_NORMAL (0)
382 #define AW88399_UVLS_NORMAL_VALUE \
383 (AW88399_UVLS_NORMAL << AW88399_UVLS_START_BIT)
384
385 #define AW88399_BSTOCS_START_BIT (11)
386 #define AW88399_BSTOCS_OVER_CURRENT (1)
387 #define AW88399_BSTOCS_OVER_CURRENT_VALUE \
388 (AW88399_BSTOCS_OVER_CURRENT << AW88399_BSTOCS_START_BIT)
389
390 #define AW88399_OTHS_START_BIT (1)
391 #define AW88399_OTHS_OT (1)
392 #define AW88399_OTHS_OT_VALUE \
393 (AW88399_OTHS_OT << AW88399_OTHS_START_BIT)
394
395 #define AW88399_PLLS_START_BIT (0)
396 #define AW88399_PLLS_LOCKED (1)
397 #define AW88399_PLLS_LOCKED_VALUE \
398 (AW88399_PLLS_LOCKED << AW88399_PLLS_START_BIT)
399
400 #define AW88399_CLKS_START_BIT (4)
401 #define AW88399_CLKS_STABLE (1)
402 #define AW88399_CLKS_STABLE_VALUE \
403 (AW88399_CLKS_STABLE << AW88399_CLKS_START_BIT)
404
405 #define AW88399_BIT_PLL_CHECK \
406 (AW88399_CLKS_STABLE_VALUE | \
407 AW88399_PLLS_LOCKED_VALUE)
408
409 #define AW88399_BIT_SYSST_CHECK_MASK \
410 (~(AW88399_UVLS_NORMAL_VALUE | \
411 AW88399_BSTOCS_OVER_CURRENT_VALUE | \
412 AW88399_BSTS_FINISHED_VALUE | \
413 AW88399_SWS_SWITCHING_VALUE | \
414 AW88399_NOCLKS_NO_CLOCK_VALUE | \
415 AW88399_CLKS_STABLE_VALUE | \
416 AW88399_OCDS_OC_VALUE | \
417 AW88399_OTHS_OT_VALUE | \
418 AW88399_PLLS_LOCKED_VALUE))
419
420 #define AW88399_BIT_SYSST_NOSWS_CHECK \
421 (AW88399_BSTS_FINISHED_VALUE | \
422 AW88399_CLKS_STABLE_VALUE | \
423 AW88399_PLLS_LOCKED_VALUE)
424
425 #define AW88399_BIT_SYSST_SWS_CHECK \
426 (AW88399_BSTS_FINISHED_VALUE | \
427 AW88399_CLKS_STABLE_VALUE | \
428 AW88399_PLLS_LOCKED_VALUE | \
429 AW88399_SWS_SWITCHING_VALUE)
430
431 #define AW88399_CCO_MUX_START_BIT (14)
432 #define AW88399_CCO_MUX_BITS_LEN (1)
433 #define AW88399_CCO_MUX_MASK \
434 (~(((1<<AW88399_CCO_MUX_BITS_LEN)-1) << AW88399_CCO_MUX_START_BIT))
435
436 #define AW88399_CCO_MUX_DIVIDED (0)
437 #define AW88399_CCO_MUX_DIVIDED_VALUE \
438 (AW88399_CCO_MUX_DIVIDED << AW88399_CCO_MUX_START_BIT)
439
440 #define AW88399_CCO_MUX_BYPASS (1)
441 #define AW88399_CCO_MUX_BYPASS_VALUE \
442 (AW88399_CCO_MUX_BYPASS << AW88399_CCO_MUX_START_BIT)
443
444 #define AW88399_NOISE_GATE_EN_START_BIT (13)
445 #define AW88399_NOISE_GATE_EN_BITS_LEN (1)
446 #define AW88399_NOISE_GATE_EN_MASK \
447 (~(((1<<AW88399_NOISE_GATE_EN_BITS_LEN)-1) << AW88399_NOISE_GATE_EN_START_BIT))
448
449 #define AW88399_WDT_CNT_START_BIT (0)
450 #define AW88399_WDT_CNT_BITS_LEN (8)
451 #define AW88399_WDT_CNT_MASK \
452 (~(((1<<AW88399_WDT_CNT_BITS_LEN)-1) << AW88399_WDT_CNT_START_BIT))
453
454 #define AW88399_VOLUME_STEP_DB (64)
455 #define AW88399_VOL_DEFAULT_VALUE (0)
456 #define AW88399_DSP_ODD_NUM_BIT_TEST (0x5555)
457 #define AW88399_EF_ISN_GESLP_SIGN_MASK (~(1 << 9))
458 #define AW88399_EF_ISN_GESLP_SIGN_NEG (0xfe00)
459
460 #define AW88399_EF_VSN_GESLP_SIGN_MASK (~(1 << 9))
461 #define AW88399_EF_VSN_GESLP_SIGN_NEG (0xfe00)
462
463 #define AW88399_TEM4_SIGN_MASK (~(1 << 5))
464 #define AW88399_TEM4_SIGN_NEG (0xffc0)
465
466 #define AW88399_ICABLK_FACTOR (1)
467 #define AW88399_VCABLK_FACTOR (1)
468 #define AW88399_VCABLK_DAC_FACTOR (2)
469
470 #define AW88399_VCALB_ADJ_FACTOR (12)
471 #define AW88399_VCALB_ACCURACY (1 << 12)
472
473 #define AW88399_ISCAL_FACTOR (3125)
474 #define AW88399_VSCAL_FACTOR (18875)
475 #define AW88399_ISCAL_DAC_FACTOR (3125)
476 #define AW88399_VSCAL_DAC_FACTOR (12600)
477 #define AW88399_CABL_BASE_VALUE (1000)
478
479 #define AW88399_DEV_DEFAULT_CH (0)
480 #define AW88399_DEV_DSP_CHECK_MAX (5)
481 #define AW88399_MAX_RAM_WRITE_BYTE_SIZE (128)
482 #define AW88399_DSP_RE_SHIFT (12)
483 #define AW88399_CALI_RE_MAX (15000)
484 #define AW88399_CALI_RE_MIN (4000)
485 #define AW_FW_ADDR_LEN (4)
486 #define AW88399_DSP_RE_TO_SHOW_RE(re, shift) (((re) * (1000)) >> (shift))
487 #define AW88399_SHOW_RE_TO_DSP_RE(re, shift) (((re) << shift) / (1000))
488 #define AW88399_CRC_CHECK_PASS_VAL (0x4)
489
490 #define AW88399_CRC_CFG_BASE_ADDR (0xD80)
491 #define AW88399_CRC_FW_BASE_ADDR (0x4C0)
492 #define AW88399_ACF_FILE "aw88399_acf.bin"
493 #define AW88399_DEV_SYSST_CHECK_MAX (10)
494 #define AW88399_CHIP_ID 0x2183
495
496 #define AW88399_I2C_NAME "aw88399"
497
498 #define AW88399_START_RETRIES (5)
499 #define AW88399_START_WORK_DELAY_MS (0)
500
501 #define AW88399_RATES (SNDRV_PCM_RATE_8000_48000 | \
502 SNDRV_PCM_RATE_96000)
503 #define AW88399_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
504 SNDRV_PCM_FMTBIT_S24_LE | \
505 SNDRV_PCM_FMTBIT_S32_LE)
506
507 #define FADE_TIME_MAX 100000
508 #define FADE_TIME_MIN 0
509
510 #define AW88399_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
511 { \
512 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
513 .name = xname, \
514 .info = profile_info, \
515 .get = profile_get, \
516 .put = profile_set, \
517 }
518
519 enum {
520 AW_EF_AND_CHECK = 0,
521 AW_EF_OR_CHECK,
522 };
523
524 enum {
525 AW88399_DEV_VDSEL_DAC = 0,
526 AW88399_DEV_VDSEL_VSENSE = 32,
527 };
528
529 enum {
530 AW88399_DSP_CRC_NA = 0,
531 AW88399_DSP_CRC_OK = 1,
532 };
533
534 enum {
535 AW88399_DSP_FW_UPDATE_OFF = 0,
536 AW88399_DSP_FW_UPDATE_ON = 1,
537 };
538
539 enum {
540 AW88399_FORCE_UPDATE_OFF = 0,
541 AW88399_FORCE_UPDATE_ON = 1,
542 };
543
544 enum {
545 AW88399_1000_US = 1000,
546 AW88399_2000_US = 2000,
547 AW88399_3000_US = 3000,
548 AW88399_4000_US = 4000,
549 };
550
551 enum AW88399_DEV_STATUS {
552 AW88399_DEV_PW_OFF = 0,
553 AW88399_DEV_PW_ON,
554 };
555
556 enum AW88399_DEV_FW_STATUS {
557 AW88399_DEV_FW_FAILED = 0,
558 AW88399_DEV_FW_OK,
559 };
560
561 enum AW88399_DEV_MEMCLK {
562 AW88399_DEV_MEMCLK_OSC = 0,
563 AW88399_DEV_MEMCLK_PLL = 1,
564 };
565
566 enum AW88399_DEV_DSP_CFG {
567 AW88399_DEV_DSP_WORK = 0,
568 AW88399_DEV_DSP_BYPASS = 1,
569 };
570
571 enum {
572 AW88399_DSP_16_DATA = 0,
573 AW88399_DSP_32_DATA = 1,
574 };
575
576 enum {
577 AW88399_NOT_RCV_MODE = 0,
578 AW88399_RCV_MODE = 1,
579 };
580
581 enum {
582 AW88399_SYNC_START = 0,
583 AW88399_ASYNC_START,
584 };
585
586 struct aw88399 {
587 struct aw_device *aw_pa;
588 struct mutex lock;
589 struct gpio_desc *reset_gpio;
590 struct delayed_work start_work;
591 struct regmap *regmap;
592 struct aw_container *aw_cfg;
593
594 unsigned int check_val;
595 unsigned int crc_init_val;
596 unsigned int vcalb_init_val;
597 unsigned int dither_st;
598 };
599
600 #endif
601
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