1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Components shared between ASoC and HDA CS35L56 drivers
4 //
5 // Copyright (C) 2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/array_size.h>
9 #include <linux/firmware/cirrus/wmfw.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/regmap.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/types.h>
14 #include <sound/cs-amp-lib.h>
15
16 #include "cs35l56.h"
17
18 static const struct reg_sequence cs35l56_patch[] = {
19 /*
20 * Firmware can change these to non-defaults to satisfy SDCA.
21 * Ensure that they are at known defaults.
22 */
23 { CS35L56_ASP1_ENABLES1, 0x00000000 },
24 { CS35L56_ASP1_CONTROL1, 0x00000028 },
25 { CS35L56_ASP1_CONTROL2, 0x18180200 },
26 { CS35L56_ASP1_CONTROL3, 0x00000002 },
27 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
28 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
29 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
30 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
31 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
32 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
33 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
34 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
35 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
36 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
37 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
38 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
39 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
40
41 /* These are not reset by a soft-reset, so patch to defaults. */
42 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
43 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
44 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
45 };
46
47 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
48 {
49 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
50 ARRAY_SIZE(cs35l56_patch));
51 }
52 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED);
53
54 static const struct reg_default cs35l56_reg_defaults[] = {
55 /* no defaults for OTP_MEM - first read populates cache */
56
57 { CS35L56_ASP1_ENABLES1, 0x00000000 },
58 { CS35L56_ASP1_CONTROL1, 0x00000028 },
59 { CS35L56_ASP1_CONTROL2, 0x18180200 },
60 { CS35L56_ASP1_CONTROL3, 0x00000002 },
61 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
62 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
63 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
64 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
65 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
66 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
67 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
68 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
69 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
70 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
71 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
72 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
73 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
74 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
75 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
76 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
77 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
78 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
79 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
80 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
81 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
82 };
83
84 static bool cs35l56_is_dsp_memory(unsigned int reg)
85 {
86 switch (reg) {
87 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
88 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
89 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
90 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
91 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
92 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
93 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
94 return true;
95 default:
96 return false;
97 }
98 }
99
100 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
101 {
102 switch (reg) {
103 case CS35L56_DEVID:
104 case CS35L56_REVID:
105 case CS35L56_RELID:
106 case CS35L56_OTPID:
107 case CS35L56_SFT_RESET:
108 case CS35L56_GLOBAL_ENABLES:
109 case CS35L56_BLOCK_ENABLES:
110 case CS35L56_BLOCK_ENABLES2:
111 case CS35L56_REFCLK_INPUT:
112 case CS35L56_GLOBAL_SAMPLE_RATE:
113 case CS35L56_OTP_MEM_53:
114 case CS35L56_OTP_MEM_54:
115 case CS35L56_OTP_MEM_55:
116 case CS35L56_ASP1_ENABLES1:
117 case CS35L56_ASP1_CONTROL1:
118 case CS35L56_ASP1_CONTROL2:
119 case CS35L56_ASP1_CONTROL3:
120 case CS35L56_ASP1_FRAME_CONTROL1:
121 case CS35L56_ASP1_FRAME_CONTROL5:
122 case CS35L56_ASP1_DATA_CONTROL1:
123 case CS35L56_ASP1_DATA_CONTROL5:
124 case CS35L56_DACPCM1_INPUT:
125 case CS35L56_DACPCM2_INPUT:
126 case CS35L56_ASP1TX1_INPUT:
127 case CS35L56_ASP1TX2_INPUT:
128 case CS35L56_ASP1TX3_INPUT:
129 case CS35L56_ASP1TX4_INPUT:
130 case CS35L56_DSP1RX1_INPUT:
131 case CS35L56_DSP1RX2_INPUT:
132 case CS35L56_SWIRE_DP3_CH1_INPUT:
133 case CS35L56_SWIRE_DP3_CH2_INPUT:
134 case CS35L56_SWIRE_DP3_CH3_INPUT:
135 case CS35L56_SWIRE_DP3_CH4_INPUT:
136 case CS35L56_IRQ1_CFG:
137 case CS35L56_IRQ1_STATUS:
138 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
139 case CS35L56_IRQ1_EINT_18:
140 case CS35L56_IRQ1_EINT_20:
141 case CS35L56_IRQ1_MASK_1:
142 case CS35L56_IRQ1_MASK_2:
143 case CS35L56_IRQ1_MASK_4:
144 case CS35L56_IRQ1_MASK_8:
145 case CS35L56_IRQ1_MASK_18:
146 case CS35L56_IRQ1_MASK_20:
147 case CS35L56_DSP_VIRTUAL1_MBOX_1:
148 case CS35L56_DSP_VIRTUAL1_MBOX_2:
149 case CS35L56_DSP_VIRTUAL1_MBOX_3:
150 case CS35L56_DSP_VIRTUAL1_MBOX_4:
151 case CS35L56_DSP_VIRTUAL1_MBOX_5:
152 case CS35L56_DSP_VIRTUAL1_MBOX_6:
153 case CS35L56_DSP_VIRTUAL1_MBOX_7:
154 case CS35L56_DSP_VIRTUAL1_MBOX_8:
155 case CS35L56_DSP_RESTRICT_STS1:
156 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
157 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
158 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
159 case CS35L56_DSP1_SCRATCH1:
160 case CS35L56_DSP1_SCRATCH2:
161 case CS35L56_DSP1_SCRATCH3:
162 case CS35L56_DSP1_SCRATCH4:
163 return true;
164 default:
165 return cs35l56_is_dsp_memory(reg);
166 }
167 }
168
169 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
170 {
171 switch (reg) {
172 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
173 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
174 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
175 return true;
176 default:
177 return false;
178 }
179 }
180
181 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
182 {
183 switch (reg) {
184 case CS35L56_DEVID:
185 case CS35L56_REVID:
186 case CS35L56_RELID:
187 case CS35L56_OTPID:
188 case CS35L56_SFT_RESET:
189 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
190 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
191 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
192 case CS35L56_REFCLK_INPUT: /* owned by firmware */
193 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
194 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
195 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
196 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
197 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
198 case CS35L56_IRQ1_STATUS:
199 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
200 case CS35L56_IRQ1_EINT_18:
201 case CS35L56_IRQ1_EINT_20:
202 case CS35L56_DSP_VIRTUAL1_MBOX_1:
203 case CS35L56_DSP_VIRTUAL1_MBOX_2:
204 case CS35L56_DSP_VIRTUAL1_MBOX_3:
205 case CS35L56_DSP_VIRTUAL1_MBOX_4:
206 case CS35L56_DSP_VIRTUAL1_MBOX_5:
207 case CS35L56_DSP_VIRTUAL1_MBOX_6:
208 case CS35L56_DSP_VIRTUAL1_MBOX_7:
209 case CS35L56_DSP_VIRTUAL1_MBOX_8:
210 case CS35L56_DSP_RESTRICT_STS1:
211 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
212 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
213 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
214 case CS35L56_DSP1_SCRATCH1:
215 case CS35L56_DSP1_SCRATCH2:
216 case CS35L56_DSP1_SCRATCH3:
217 case CS35L56_DSP1_SCRATCH4:
218 return true;
219 case CS35L56_MAIN_RENDER_USER_MUTE:
220 case CS35L56_MAIN_RENDER_USER_VOLUME:
221 case CS35L56_MAIN_POSTURE_NUMBER:
222 return false;
223 default:
224 return cs35l56_is_dsp_memory(reg);
225 }
226 }
227
228 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
229 {
230 unsigned int val;
231 int ret;
232
233 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
234 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
235 val, (val == 0),
236 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
237 if (ret) {
238 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
239 return ret;
240 }
241
242 return 0;
243 }
244 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED);
245
246 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
247 {
248 int ret;
249 unsigned int val;
250
251 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
252 if (ret)
253 return ret;
254
255 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP1_PM_CUR_STATE,
256 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
257 CS35L56_HALO_STATE_POLL_US,
258 CS35L56_HALO_STATE_TIMEOUT_US);
259 if (ret < 0)
260 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
261 val, ret);
262 return ret;
263 }
264 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED);
265
266 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
267 {
268 unsigned int val = 0;
269 int read_ret, poll_ret;
270
271 /*
272 * The regmap must remain in cache-only until the chip has
273 * booted, so use a bypassed read of the status register.
274 */
275 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret,
276 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
277 CS35L56_HALO_STATE_POLL_US,
278 CS35L56_HALO_STATE_TIMEOUT_US,
279 false,
280 cs35l56_base->regmap, CS35L56_DSP1_HALO_STATE, &val);
281
282 if (poll_ret) {
283 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
284 read_ret, val);
285 return -EIO;
286 }
287
288 return 0;
289 }
290 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED);
291
292 void cs35l56_wait_control_port_ready(void)
293 {
294 /* Wait for control port to be ready (datasheet tIRS). */
295 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
296 }
297 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED);
298
299 void cs35l56_wait_min_reset_pulse(void)
300 {
301 /* Satisfy minimum reset pulse width spec */
302 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
303 }
304 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED);
305
306 static const struct reg_sequence cs35l56_system_reset_seq[] = {
307 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
308 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
309 };
310
311 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
312 {
313 /*
314 * Must enter cache-only first so there can't be any more register
315 * accesses other than the controlled system reset sequence below.
316 */
317 regcache_cache_only(cs35l56_base->regmap, true);
318 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
319 cs35l56_system_reset_seq,
320 ARRAY_SIZE(cs35l56_system_reset_seq));
321
322 /* On SoundWire the registers won't be accessible until it re-enumerates. */
323 if (is_soundwire)
324 return;
325
326 cs35l56_wait_control_port_ready();
327
328 /* Leave in cache-only. This will be revoked when the chip has rebooted. */
329 }
330 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED);
331
332 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
333 {
334 int ret;
335
336 if (irq < 1)
337 return 0;
338
339 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
340 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
341 "cs35l56", cs35l56_base);
342 if (!ret)
343 cs35l56_base->irq = irq;
344 else
345 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
346
347 return ret;
348 }
349 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED);
350
351 irqreturn_t cs35l56_irq(int irq, void *data)
352 {
353 struct cs35l56_base *cs35l56_base = data;
354 unsigned int status1 = 0, status8 = 0, status20 = 0;
355 unsigned int mask1, mask8, mask20;
356 unsigned int val;
357 int rv;
358
359 irqreturn_t ret = IRQ_NONE;
360
361 if (!cs35l56_base->init_done)
362 return IRQ_NONE;
363
364 mutex_lock(&cs35l56_base->irq_lock);
365
366 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
367 if (rv < 0) {
368 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
369 goto err_unlock;
370 }
371
372 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
373 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
374 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
375 goto err;
376 }
377
378 /* Ack interrupts */
379 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
380 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
381 status1 &= ~mask1;
382 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
383
384 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
385 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
386 status8 &= ~mask8;
387 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
388
389 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
390 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
391 status20 &= ~mask20;
392 /* We don't want EINT20 but they default to unmasked: force mask */
393 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
394
395 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
396
397 /* Check to see if unmasked bits are active */
398 if (!status1 && !status8 && !status20)
399 goto err;
400
401 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
402 dev_crit(cs35l56_base->dev, "Amp short error\n");
403
404 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
405 dev_crit(cs35l56_base->dev, "Overtemp error\n");
406
407 ret = IRQ_HANDLED;
408
409 err:
410 pm_runtime_put(cs35l56_base->dev);
411 err_unlock:
412 mutex_unlock(&cs35l56_base->irq_lock);
413
414 return ret;
415 }
416 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED);
417
418 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
419 {
420 unsigned int val;
421 int ret;
422
423 /*
424 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
425 * can't be used here to test for memory retention.
426 * Assume that tuning must be re-loaded.
427 */
428 if (cs35l56_base->secured)
429 return true;
430
431 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
432 if (ret) {
433 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
434 return ret;
435 }
436
437 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val);
438 if (ret)
439 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
440 else
441 ret = !!(val & CS35L56_FIRMWARE_MISSING);
442
443 pm_runtime_put_autosuspend(cs35l56_base->dev);
444
445 return ret;
446 }
447 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED);
448
449 static const struct reg_sequence cs35l56_hibernate_seq[] = {
450 /* This must be the last register access */
451 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
452 };
453
454 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = {
455 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP),
456 };
457
458 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
459 {
460 /*
461 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
462 * transactions to meet the minimum required time from the rising edge
463 * to the last falling edge of wake.
464 *
465 * It uses bypassed write because we must wake the chip before
466 * disabling regmap cache-only.
467 *
468 * This can NAK on I2C which will terminate the write sequence so the
469 * single-write sequence is issued twice.
470 */
471 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
472 cs35l56_hibernate_wake_seq,
473 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
474
475 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
476
477 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
478 cs35l56_hibernate_wake_seq,
479 ARRAY_SIZE(cs35l56_hibernate_wake_seq));
480
481 cs35l56_wait_control_port_ready();
482 }
483
484 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
485 {
486 unsigned int val;
487 int ret;
488
489 if (!cs35l56_base->init_done)
490 return 0;
491
492 /* Firmware must have entered a power-save state */
493 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
494 CS35L56_TRANSDUCER_ACTUAL_PS,
495 val, (val >= CS35L56_PS3),
496 CS35L56_PS3_POLL_US,
497 CS35L56_PS3_TIMEOUT_US);
498 if (ret)
499 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
500
501 /* Clear BOOT_DONE so it can be used to detect a reboot */
502 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
503
504 if (!cs35l56_base->can_hibernate) {
505 regcache_cache_only(cs35l56_base->regmap, true);
506 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
507
508 return 0;
509 }
510
511 /*
512 * Must enter cache-only first so there can't be any more register
513 * accesses other than the controlled hibernate sequence below.
514 */
515 regcache_cache_only(cs35l56_base->regmap, true);
516
517 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
518 cs35l56_hibernate_seq,
519 ARRAY_SIZE(cs35l56_hibernate_seq));
520
521 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
522
523 return 0;
524 }
525 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED);
526
527 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
528 {
529 unsigned int val;
530 int ret;
531
532 if (!cs35l56_base->init_done)
533 return 0;
534
535 if (!cs35l56_base->can_hibernate)
536 goto out_sync;
537
538 /* Must be done before releasing cache-only */
539 if (!is_soundwire)
540 cs35l56_issue_wake_event(cs35l56_base);
541
542 out_sync:
543 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
544 if (ret) {
545 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
546 goto err;
547 }
548
549 regcache_cache_only(cs35l56_base->regmap, false);
550
551 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
552 if (ret)
553 goto err;
554
555 /* BOOT_DONE will be 1 if the amp reset */
556 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
557 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
558 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
559 regcache_mark_dirty(cs35l56_base->regmap);
560 }
561
562 regcache_sync(cs35l56_base->regmap);
563
564 dev_dbg(cs35l56_base->dev, "Resumed");
565
566 return 0;
567
568 err:
569 regcache_cache_only(cs35l56_base->regmap, true);
570
571 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
572 cs35l56_hibernate_seq,
573 ARRAY_SIZE(cs35l56_hibernate_seq));
574
575 return ret;
576 }
577 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED);
578
579 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
580 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
581 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
582 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
583 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
584 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
585 };
586
587 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
588 {
589 cs_dsp->num = 1;
590 cs_dsp->type = WMFW_HALO;
591 cs_dsp->rev = 0;
592 cs_dsp->dev = cs35l56_base->dev;
593 cs_dsp->regmap = cs35l56_base->regmap;
594 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
595 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
596 cs_dsp->mem = cs35l56_dsp1_regions;
597 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
598 cs_dsp->no_core_startstop = true;
599 }
600 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED);
601
602 struct cs35l56_pte {
603 u8 x;
604 u8 wafer_id;
605 u8 pte[2];
606 u8 lot[3];
607 u8 y;
608 u8 unused[3];
609 u8 dvs;
610 } __packed;
611 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0);
612
613 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid)
614 {
615 struct cs35l56_pte pte;
616 u64 unique_id;
617 int ret;
618
619 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte));
620 if (ret) {
621 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret);
622 return ret;
623 }
624
625 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16);
626 unique_id <<= 32;
627 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) |
628 ((u32)pte.dvs << 24);
629
630 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id);
631
632 *uid = unique_id;
633
634 return 0;
635 }
636
637 /* Firmware calibration controls */
638 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = {
639 .alg_id = 0x9f210,
640 .mem_region = WMFW_ADSP2_YM,
641 .ambient = "CAL_AMBIENT",
642 .calr = "CAL_R",
643 .status = "CAL_STATUS",
644 .checksum = "CAL_CHECKSUM",
645 };
646 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED);
647
648 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base)
649 {
650 u64 silicon_uid = 0;
651 int ret;
652
653 /* Driver can't apply calibration to a secured part, so skip */
654 if (cs35l56_base->secured)
655 return 0;
656
657 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid);
658 if (ret < 0)
659 return ret;
660
661 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid,
662 cs35l56_base->cal_index,
663 &cs35l56_base->cal_data);
664
665 /* Only return an error status if probe should be aborted */
666 if ((ret == -ENOENT) || (ret == -EOVERFLOW))
667 return 0;
668
669 if (ret < 0)
670 return ret;
671
672 cs35l56_base->cal_data_valid = true;
673
674 return 0;
675 }
676 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED);
677
678 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
679 bool *fw_missing, unsigned int *fw_version)
680 {
681 unsigned int prot_status;
682 int ret;
683
684 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status);
685 if (ret) {
686 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret);
687 return ret;
688 }
689
690 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING);
691
692 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version);
693 if (ret) {
694 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret);
695 return ret;
696 }
697
698 return 0;
699 }
700 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED);
701
702 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
703 {
704 int ret;
705 unsigned int devid, revid, otpid, secured, fw_ver;
706 bool fw_missing;
707
708 /*
709 * When the system is not using a reset_gpio ensure the device is
710 * awake, otherwise the device has just been released from reset and
711 * the driver must wait for the control port to become usable.
712 */
713 if (!cs35l56_base->reset_gpio)
714 cs35l56_issue_wake_event(cs35l56_base);
715 else
716 cs35l56_wait_control_port_ready();
717
718 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid);
719 if (ret < 0) {
720 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
721 return ret;
722 }
723 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
724
725 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
726 if (ret)
727 return ret;
728
729 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid);
730 if (ret < 0) {
731 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
732 return ret;
733 }
734 devid &= CS35L56_DEVID_MASK;
735
736 switch (devid) {
737 case 0x35A54:
738 case 0x35A56:
739 case 0x35A57:
740 break;
741 default:
742 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
743 return ret;
744 }
745
746 cs35l56_base->type = devid & 0xFF;
747
748 /* Silicon is now identified and booted so exit cache-only */
749 regcache_cache_only(cs35l56_base->regmap, false);
750
751 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
752 if (ret) {
753 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
754 return ret;
755 }
756
757 /* When any bus is restricted treat the device as secured */
758 if (secured & CS35L56_RESTRICTED_MASK)
759 cs35l56_base->secured = true;
760
761 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
762 if (ret < 0) {
763 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
764 return ret;
765 }
766
767 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver);
768 if (ret)
769 return ret;
770
771 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n",
772 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid,
773 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing);
774
775 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
776 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
777 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
778 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
779 0);
780 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
781 CS35L56_TEMP_ERR_EINT1_MASK,
782 0);
783
784 return 0;
785 }
786 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED);
787
788 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
789 {
790 struct gpio_descs *descs;
791 u32 speaker_id;
792 int i, ret;
793
794 /* Attempt to read the speaker type from a device property first */
795 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id);
796 if (!ret) {
797 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
798 return speaker_id;
799 }
800
801 /* Read the speaker type qualifier from the motherboard GPIOs */
802 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
803 if (!descs) {
804 return -ENOENT;
805 } else if (IS_ERR(descs)) {
806 ret = PTR_ERR(descs);
807 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
808 }
809
810 speaker_id = 0;
811 for (i = 0; i < descs->ndescs; i++) {
812 ret = gpiod_get_value_cansleep(descs->desc[i]);
813 if (ret < 0) {
814 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
815 goto err;
816 }
817
818 speaker_id |= (ret << i);
819 }
820
821 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
822 ret = speaker_id;
823 err:
824 gpiod_put_array(descs);
825
826 return ret;
827 }
828 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED);
829
830 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
831 [0x0C] = 128000,
832 [0x0F] = 256000,
833 [0x11] = 384000,
834 [0x12] = 512000,
835 [0x15] = 768000,
836 [0x17] = 1024000,
837 [0x1A] = 1500000,
838 [0x1B] = 1536000,
839 [0x1C] = 2000000,
840 [0x1D] = 2048000,
841 [0x1E] = 2400000,
842 [0x20] = 3000000,
843 [0x21] = 3072000,
844 [0x23] = 4000000,
845 [0x24] = 4096000,
846 [0x25] = 4800000,
847 [0x27] = 6000000,
848 [0x28] = 6144000,
849 [0x29] = 6250000,
850 [0x2A] = 6400000,
851 [0x2E] = 8000000,
852 [0x2F] = 8192000,
853 [0x30] = 9600000,
854 [0x32] = 12000000,
855 [0x33] = 12288000,
856 [0x37] = 13500000,
857 [0x38] = 19200000,
858 [0x39] = 22579200,
859 [0x3B] = 24576000,
860 };
861
862 int cs35l56_get_bclk_freq_id(unsigned int freq)
863 {
864 int i;
865
866 if (freq == 0)
867 return -EINVAL;
868
869 /* The BCLK frequency must be a valid PLL REFCLK */
870 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
871 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
872 return i;
873 }
874
875 return -EINVAL;
876 }
877 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED);
878
879 static const char * const cs35l56_supplies[/* auto-sized */] = {
880 "VDD_P",
881 "VDD_IO",
882 "VDD_A",
883 };
884
885 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
886 {
887 int i;
888
889 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
890 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
891 data[i].supply = cs35l56_supplies[i];
892 }
893 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED);
894
895 const char * const cs35l56_tx_input_texts[] = {
896 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
897 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
898 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
899 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
900 };
901 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED);
902
903 const unsigned int cs35l56_tx_input_values[] = {
904 CS35L56_INPUT_SRC_NONE,
905 CS35L56_INPUT_SRC_ASP1RX1,
906 CS35L56_INPUT_SRC_ASP1RX2,
907 CS35L56_INPUT_SRC_VMON,
908 CS35L56_INPUT_SRC_IMON,
909 CS35L56_INPUT_SRC_ERR_VOL,
910 CS35L56_INPUT_SRC_CLASSH,
911 CS35L56_INPUT_SRC_VDDBMON,
912 CS35L56_INPUT_SRC_VBSTMON,
913 CS35L56_INPUT_SRC_DSP1TX1,
914 CS35L56_INPUT_SRC_DSP1TX2,
915 CS35L56_INPUT_SRC_DSP1TX3,
916 CS35L56_INPUT_SRC_DSP1TX4,
917 CS35L56_INPUT_SRC_DSP1TX5,
918 CS35L56_INPUT_SRC_DSP1TX6,
919 CS35L56_INPUT_SRC_DSP1TX7,
920 CS35L56_INPUT_SRC_DSP1TX8,
921 CS35L56_INPUT_SRC_TEMPMON,
922 CS35L56_INPUT_SRC_INTERPOLATOR,
923 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
924 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
925 };
926 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED);
927
928 struct regmap_config cs35l56_regmap_i2c = {
929 .reg_bits = 32,
930 .val_bits = 32,
931 .reg_stride = 4,
932 .reg_format_endian = REGMAP_ENDIAN_BIG,
933 .val_format_endian = REGMAP_ENDIAN_BIG,
934 .max_register = CS35L56_DSP1_PMEM_5114,
935 .reg_defaults = cs35l56_reg_defaults,
936 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
937 .volatile_reg = cs35l56_volatile_reg,
938 .readable_reg = cs35l56_readable_reg,
939 .precious_reg = cs35l56_precious_reg,
940 .cache_type = REGCACHE_MAPLE,
941 };
942 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED);
943
944 struct regmap_config cs35l56_regmap_spi = {
945 .reg_bits = 32,
946 .val_bits = 32,
947 .pad_bits = 16,
948 .reg_stride = 4,
949 .reg_format_endian = REGMAP_ENDIAN_BIG,
950 .val_format_endian = REGMAP_ENDIAN_BIG,
951 .max_register = CS35L56_DSP1_PMEM_5114,
952 .reg_defaults = cs35l56_reg_defaults,
953 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
954 .volatile_reg = cs35l56_volatile_reg,
955 .readable_reg = cs35l56_readable_reg,
956 .precious_reg = cs35l56_precious_reg,
957 .cache_type = REGCACHE_MAPLE,
958 };
959 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED);
960
961 struct regmap_config cs35l56_regmap_sdw = {
962 .reg_bits = 32,
963 .val_bits = 32,
964 .reg_stride = 4,
965 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
966 .val_format_endian = REGMAP_ENDIAN_BIG,
967 .max_register = CS35L56_DSP1_PMEM_5114,
968 .reg_defaults = cs35l56_reg_defaults,
969 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
970 .volatile_reg = cs35l56_volatile_reg,
971 .readable_reg = cs35l56_readable_reg,
972 .precious_reg = cs35l56_precious_reg,
973 .cache_type = REGCACHE_MAPLE,
974 };
975 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED);
976
977 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
978 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
979 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
980 MODULE_LICENSE("GPL");
981 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB);
982
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