1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs42l52.c -- CS42L52 ALSA SoC audio driver
4 *
5 * Copyright 2012 CirrusLogic, Inc.
6 *
7 * Author: Georgi Vlaev <joe@nucleusys.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/input.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/workqueue.h>
23 #include <linux/platform_device.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <sound/cs42l52.h>
32 #include "cs42l52.h"
33
34 struct sp_config {
35 u8 spc, format, spfs;
36 u32 srate;
37 };
38
39 struct cs42l52_private {
40 struct regmap *regmap;
41 struct snd_soc_component *component;
42 struct device *dev;
43 struct sp_config config;
44 struct cs42l52_platform_data pdata;
45 u32 sysclk;
46 u8 mclksel;
47 u32 mclk;
48 u8 flags;
49 struct input_dev *beep;
50 struct work_struct beep_work;
51 int beep_rate;
52 };
53
54 static const struct reg_default cs42l52_reg_defaults[] = {
55 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
56 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
57 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
58 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
59 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
60 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
61 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
62 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
63 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
64 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
65 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
66 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
67 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
68 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
69 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
70 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
71 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
72 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
73 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
74 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
75 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
76 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
77 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
78 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
79 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
80 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
81 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
82 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
83 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
84 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
85 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
86 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
87 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
88 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
89 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
90 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
91 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
92 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
93 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
94 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
95 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
96 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
97 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
98 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
99 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
100 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
101 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
102 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
103 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
104 };
105
106 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
107 {
108 switch (reg) {
109 case CS42L52_CHIP ... CS42L52_CHARGE_PUMP:
110 return true;
111 default:
112 return false;
113 }
114 }
115
116 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
117 {
118 switch (reg) {
119 case CS42L52_IFACE_CTL2:
120 case CS42L52_CLK_STATUS:
121 case CS42L52_BATT_LEVEL:
122 case CS42L52_SPK_STATUS:
123 case CS42L52_CHARGE_PUMP:
124 return true;
125 default:
126 return false;
127 }
128 }
129
130 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
131
132 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
133
134 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
135
136 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
137
138 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
139
140 static DECLARE_TLV_DB_SCALE(pass_tlv, -6000, 50, 0);
141
142 static DECLARE_TLV_DB_SCALE(mix_tlv, -5150, 50, 0);
143
144 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
145
146 static const DECLARE_TLV_DB_RANGE(limiter_tlv,
147 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
148 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
149 );
150
151 static const char * const cs42l52_adca_text[] = {
152 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
153
154 static const char * const cs42l52_adcb_text[] = {
155 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
156
157 static SOC_ENUM_SINGLE_DECL(adca_enum,
158 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
159
160 static SOC_ENUM_SINGLE_DECL(adcb_enum,
161 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
162
163 static const struct snd_kcontrol_new adca_mux =
164 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
165
166 static const struct snd_kcontrol_new adcb_mux =
167 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
168
169 static const char * const mic_bias_level_text[] = {
170 "0.5 +VA", "0.6 +VA", "0.7 +VA",
171 "0.8 +VA", "0.83 +VA", "0.91 +VA"
172 };
173
174 static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
175 CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
176
177 static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
178
179 static SOC_ENUM_SINGLE_DECL(mica_enum,
180 CS42L52_MICA_CTL, 5, cs42l52_mic_text);
181
182 static SOC_ENUM_SINGLE_DECL(micb_enum,
183 CS42L52_MICB_CTL, 5, cs42l52_mic_text);
184
185 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
186
187 static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
188 CS42L52_ADC_MISC_CTL, 6,
189 digital_output_mux_text);
190
191 static const struct snd_kcontrol_new digital_output_mux =
192 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
193
194 static const char * const hp_gain_num_text[] = {
195 "0.3959", "0.4571", "0.5111", "0.6047",
196 "0.7099", "0.8399", "1.000", "1.1430"
197 };
198
199 static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
200 CS42L52_PB_CTL1, 5,
201 hp_gain_num_text);
202
203 static const char * const beep_pitch_text[] = {
204 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
205 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
206 };
207
208 static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
209 CS42L52_BEEP_FREQ, 4,
210 beep_pitch_text);
211
212 static const char * const beep_ontime_text[] = {
213 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
214 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
215 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
216 };
217
218 static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
219 CS42L52_BEEP_FREQ, 0,
220 beep_ontime_text);
221
222 static const char * const beep_offtime_text[] = {
223 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
224 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
225 };
226
227 static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
228 CS42L52_BEEP_VOL, 5,
229 beep_offtime_text);
230
231 static const char * const beep_config_text[] = {
232 "Off", "Single", "Multiple", "Continuous"
233 };
234
235 static SOC_ENUM_SINGLE_DECL(beep_config_enum,
236 CS42L52_BEEP_TONE_CTL, 6,
237 beep_config_text);
238
239 static const char * const beep_bass_text[] = {
240 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
241 };
242
243 static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
244 CS42L52_BEEP_TONE_CTL, 1,
245 beep_bass_text);
246
247 static const char * const beep_treble_text[] = {
248 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
249 };
250
251 static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
252 CS42L52_BEEP_TONE_CTL, 3,
253 beep_treble_text);
254
255 static const char * const ng_threshold_text[] = {
256 "-34dB", "-37dB", "-40dB", "-43dB",
257 "-46dB", "-52dB", "-58dB", "-64dB"
258 };
259
260 static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
261 CS42L52_NOISE_GATE_CTL, 2,
262 ng_threshold_text);
263
264 static const char * const cs42l52_ng_delay_text[] = {
265 "50ms", "100ms", "150ms", "200ms"};
266
267 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
268 CS42L52_NOISE_GATE_CTL, 0,
269 cs42l52_ng_delay_text);
270
271 static const char * const cs42l52_ng_type_text[] = {
272 "Apply Specific", "Apply All"
273 };
274
275 static SOC_ENUM_SINGLE_DECL(ng_type_enum,
276 CS42L52_NOISE_GATE_CTL, 6,
277 cs42l52_ng_type_text);
278
279 static const char * const left_swap_text[] = {
280 "Left", "LR 2", "Right"};
281
282 static const char * const right_swap_text[] = {
283 "Right", "LR 2", "Left"};
284
285 static const unsigned int swap_values[] = { 0, 1, 3 };
286
287 static const struct soc_enum adca_swap_enum =
288 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
289 ARRAY_SIZE(left_swap_text),
290 left_swap_text,
291 swap_values);
292
293 static const struct snd_kcontrol_new adca_mixer =
294 SOC_DAPM_ENUM("Route", adca_swap_enum);
295
296 static const struct soc_enum pcma_swap_enum =
297 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
298 ARRAY_SIZE(left_swap_text),
299 left_swap_text,
300 swap_values);
301
302 static const struct snd_kcontrol_new pcma_mixer =
303 SOC_DAPM_ENUM("Route", pcma_swap_enum);
304
305 static const struct soc_enum adcb_swap_enum =
306 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
307 ARRAY_SIZE(right_swap_text),
308 right_swap_text,
309 swap_values);
310
311 static const struct snd_kcontrol_new adcb_mixer =
312 SOC_DAPM_ENUM("Route", adcb_swap_enum);
313
314 static const struct soc_enum pcmb_swap_enum =
315 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
316 ARRAY_SIZE(right_swap_text),
317 right_swap_text,
318 swap_values);
319
320 static const struct snd_kcontrol_new pcmb_mixer =
321 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
322
323
324 static const struct snd_kcontrol_new passthrul_ctl =
325 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
326
327 static const struct snd_kcontrol_new passthrur_ctl =
328 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
329
330 static const struct snd_kcontrol_new spkl_ctl =
331 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
332
333 static const struct snd_kcontrol_new spkr_ctl =
334 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
335
336 static const struct snd_kcontrol_new hpl_ctl =
337 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
338
339 static const struct snd_kcontrol_new hpr_ctl =
340 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
341
342 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
343
344 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
345 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
346
347 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
348 CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv),
349
350 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
351
352 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
353 CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv),
354
355 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
356 CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pass_tlv),
357
358 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
359
360 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
361 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
362
363 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
364
365 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
366 CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv),
367 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
368 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
369 0, 0x19, 0x7F, mix_tlv),
370
371 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
372
373 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
374 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
375
376 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
377 CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv),
378
379 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
380 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
381 0, 0x19, 0x7f, mix_tlv),
382 SOC_DOUBLE_R("PCM Mixer Switch",
383 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
384
385 SOC_ENUM("Beep Config", beep_config_enum),
386 SOC_ENUM("Beep Pitch", beep_pitch_enum),
387 SOC_ENUM("Beep on Time", beep_ontime_enum),
388 SOC_ENUM("Beep off Time", beep_offtime_enum),
389 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
390 0, 0x07, 0x1f, beep_tlv),
391 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
392 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
393 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
394
395 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
396 SOC_SINGLE_TLV("Treble Gain Volume",
397 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
398 SOC_SINGLE_TLV("Bass Gain Volume",
399 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
400
401 /* Limiter */
402 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
403 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
404 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
405 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
406 SOC_SINGLE_TLV("Limiter Release Rate Volume",
407 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
408 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
409 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
410
411 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
412 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
413 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
414
415 /* ALC */
416 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
417 0, 63, 0, limiter_tlv),
418 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
419 0, 63, 0, limiter_tlv),
420 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
421 5, 7, 0, limiter_tlv),
422 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
423 2, 7, 0, limiter_tlv),
424
425 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
426 CS42L52_PGAB_CTL, 7, 1, 1),
427 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
428 CS42L52_PGAB_CTL, 6, 1, 1),
429 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
430
431 /* Noise gate */
432 SOC_ENUM("NG Type Switch", ng_type_enum),
433 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
434 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
435 SOC_ENUM("NG Threshold", ng_threshold_enum),
436 SOC_ENUM("NG Delay", ng_delay_enum),
437
438 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
439
440 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
441 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
442 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
443 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
444 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
445
446 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
447 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
448 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
449
450 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
451 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
452 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
453 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
454
455 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
456 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
457
458 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
459 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
460
461 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
462 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
463
464 };
465
466 static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
467 SOC_ENUM("MICA Select", mica_enum),
468 };
469
470 static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
471 SOC_ENUM("MICB Select", micb_enum),
472 };
473
474 static int cs42l52_add_mic_controls(struct snd_soc_component *component)
475 {
476 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
477 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
478
479 if (!pdata->mica_diff_cfg)
480 snd_soc_add_component_controls(component, cs42l52_mica_controls,
481 ARRAY_SIZE(cs42l52_mica_controls));
482
483 if (!pdata->micb_diff_cfg)
484 snd_soc_add_component_controls(component, cs42l52_micb_controls,
485 ARRAY_SIZE(cs42l52_micb_controls));
486
487 return 0;
488 }
489
490 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
491
492 SND_SOC_DAPM_INPUT("AIN1L"),
493 SND_SOC_DAPM_INPUT("AIN1R"),
494 SND_SOC_DAPM_INPUT("AIN2L"),
495 SND_SOC_DAPM_INPUT("AIN2R"),
496 SND_SOC_DAPM_INPUT("AIN3L"),
497 SND_SOC_DAPM_INPUT("AIN3R"),
498 SND_SOC_DAPM_INPUT("AIN4L"),
499 SND_SOC_DAPM_INPUT("AIN4R"),
500 SND_SOC_DAPM_INPUT("MICA"),
501 SND_SOC_DAPM_INPUT("MICB"),
502 SND_SOC_DAPM_SIGGEN("Beep"),
503
504 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
505 SND_SOC_NOPM, 0, 0),
506 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
507 SND_SOC_NOPM, 0, 0),
508
509 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
510 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
511 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
512 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
513
514 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
515 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
516
517 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
518 0, 0, &adca_mixer),
519 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
520 0, 0, &adcb_mixer),
521
522 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
523 0, 0, &digital_output_mux),
524
525 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
526 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
527
528 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
529 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
530
531 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
532 SND_SOC_NOPM, 0, 0),
533 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
534 SND_SOC_NOPM, 0, 0),
535
536 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
537 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
538
539 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
540 6, 0, &passthrul_ctl),
541 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
542 7, 0, &passthrur_ctl),
543
544 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
545 0, 0, &pcma_mixer),
546 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
547 0, 0, &pcmb_mixer),
548
549 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
550 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
551
552 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
553 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
554
555 SND_SOC_DAPM_OUTPUT("HPOUTA"),
556 SND_SOC_DAPM_OUTPUT("HPOUTB"),
557 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
558 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
559
560 };
561
562 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
563
564 {"Capture", NULL, "AIFOUTL"},
565 {"Capture", NULL, "AIFOUTL"},
566
567 {"AIFOUTL", NULL, "Output Mux"},
568 {"AIFOUTR", NULL, "Output Mux"},
569
570 {"Output Mux", "ADC", "ADC Left"},
571 {"Output Mux", "ADC", "ADC Right"},
572
573 {"ADC Left", NULL, "Charge Pump"},
574 {"ADC Right", NULL, "Charge Pump"},
575
576 {"Charge Pump", NULL, "ADC Left Mux"},
577 {"Charge Pump", NULL, "ADC Right Mux"},
578
579 {"ADC Left Mux", "Input1A", "AIN1L"},
580 {"ADC Right Mux", "Input1B", "AIN1R"},
581 {"ADC Left Mux", "Input2A", "AIN2L"},
582 {"ADC Right Mux", "Input2B", "AIN2R"},
583 {"ADC Left Mux", "Input3A", "AIN3L"},
584 {"ADC Right Mux", "Input3B", "AIN3R"},
585 {"ADC Left Mux", "Input4A", "AIN4L"},
586 {"ADC Right Mux", "Input4B", "AIN4R"},
587 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
588 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
589
590 {"PGA Left", "Switch", "AIN1L"},
591 {"PGA Right", "Switch", "AIN1R"},
592 {"PGA Left", "Switch", "AIN2L"},
593 {"PGA Right", "Switch", "AIN2R"},
594 {"PGA Left", "Switch", "AIN3L"},
595 {"PGA Right", "Switch", "AIN3R"},
596 {"PGA Left", "Switch", "AIN4L"},
597 {"PGA Right", "Switch", "AIN4R"},
598
599 {"PGA Left", "Switch", "PGA MICA"},
600 {"PGA MICA", NULL, "MICA"},
601
602 {"PGA Right", "Switch", "PGA MICB"},
603 {"PGA MICB", NULL, "MICB"},
604
605 {"HPOUTA", NULL, "HP Left Amp"},
606 {"HPOUTB", NULL, "HP Right Amp"},
607 {"HP Left Amp", NULL, "Bypass Left"},
608 {"HP Right Amp", NULL, "Bypass Right"},
609 {"Bypass Left", "Switch", "PGA Left"},
610 {"Bypass Right", "Switch", "PGA Right"},
611 {"HP Left Amp", "Switch", "DAC Left"},
612 {"HP Right Amp", "Switch", "DAC Right"},
613
614 {"SPKOUTA", NULL, "SPK Left Amp"},
615 {"SPKOUTB", NULL, "SPK Right Amp"},
616
617 {"SPK Left Amp", NULL, "Beep"},
618 {"SPK Right Amp", NULL, "Beep"},
619 {"SPK Left Amp", "Switch", "Playback"},
620 {"SPK Right Amp", "Switch", "Playback"},
621
622 {"DAC Left", NULL, "Beep"},
623 {"DAC Right", NULL, "Beep"},
624 {"DAC Left", NULL, "Playback"},
625 {"DAC Right", NULL, "Playback"},
626
627 {"Output Mux", "DSP", "Playback"},
628 {"Output Mux", "DSP", "Playback"},
629
630 {"AIFINL", NULL, "Playback"},
631 {"AIFINR", NULL, "Playback"},
632
633 };
634
635 struct cs42l52_clk_para {
636 u32 mclk;
637 u32 rate;
638 u8 speed;
639 u8 group;
640 u8 videoclk;
641 u8 ratio;
642 u8 mclkdiv2;
643 };
644
645 static const struct cs42l52_clk_para clk_map_table[] = {
646 /*8k*/
647 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
648 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
649 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
650 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
651 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
652
653 /*11.025k*/
654 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
655 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
656
657 /*16k*/
658 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
659 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
660 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
661 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
662 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
663
664 /*22.05k*/
665 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
666 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
667
668 /* 32k */
669 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
670 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
671 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
672 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
673 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
674
675 /* 44.1k */
676 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
677 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
678
679 /* 48k */
680 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
681 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
682 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
683 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
684 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
685
686 /* 88.2k */
687 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
688 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
689
690 /* 96k */
691 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
692 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
693 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
694 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
695 };
696
697 static int cs42l52_get_clk(int mclk, int rate)
698 {
699 int i, ret = -EINVAL;
700 u_int mclk1, mclk2 = 0;
701
702 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
703 if (clk_map_table[i].rate == rate) {
704 mclk1 = clk_map_table[i].mclk;
705 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
706 mclk2 = mclk1;
707 ret = i;
708 }
709 }
710 }
711 return ret;
712 }
713
714 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
715 int clk_id, unsigned int freq, int dir)
716 {
717 struct snd_soc_component *component = codec_dai->component;
718 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
719
720 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
721 cs42l52->sysclk = freq;
722 } else {
723 dev_err(component->dev, "Invalid freq parameter\n");
724 return -EINVAL;
725 }
726 return 0;
727 }
728
729 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
730 {
731 struct snd_soc_component *component = codec_dai->component;
732 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
733 u8 iface = 0;
734
735 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
736 case SND_SOC_DAIFMT_CBM_CFM:
737 iface = CS42L52_IFACE_CTL1_MASTER;
738 break;
739 case SND_SOC_DAIFMT_CBS_CFS:
740 iface = CS42L52_IFACE_CTL1_SLAVE;
741 break;
742 default:
743 return -EINVAL;
744 }
745
746 /* interface format */
747 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
748 case SND_SOC_DAIFMT_I2S:
749 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
750 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
751 break;
752 case SND_SOC_DAIFMT_RIGHT_J:
753 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
754 break;
755 case SND_SOC_DAIFMT_LEFT_J:
756 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
757 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
758 break;
759 case SND_SOC_DAIFMT_DSP_A:
760 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
761 break;
762 case SND_SOC_DAIFMT_DSP_B:
763 break;
764 default:
765 return -EINVAL;
766 }
767
768 /* clock inversion */
769 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
770 case SND_SOC_DAIFMT_NB_NF:
771 break;
772 case SND_SOC_DAIFMT_IB_IF:
773 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
774 break;
775 case SND_SOC_DAIFMT_IB_NF:
776 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
777 break;
778 case SND_SOC_DAIFMT_NB_IF:
779 break;
780 default:
781 return -EINVAL;
782 }
783 cs42l52->config.format = iface;
784 snd_soc_component_write(component, CS42L52_IFACE_CTL1, cs42l52->config.format);
785
786 return 0;
787 }
788
789 static int cs42l52_mute(struct snd_soc_dai *dai, int mute, int direction)
790 {
791 struct snd_soc_component *component = dai->component;
792
793 if (mute)
794 snd_soc_component_update_bits(component, CS42L52_PB_CTL1,
795 CS42L52_PB_CTL1_MUTE_MASK,
796 CS42L52_PB_CTL1_MUTE);
797 else
798 snd_soc_component_update_bits(component, CS42L52_PB_CTL1,
799 CS42L52_PB_CTL1_MUTE_MASK,
800 CS42L52_PB_CTL1_UNMUTE);
801
802 return 0;
803 }
804
805 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
806 struct snd_pcm_hw_params *params,
807 struct snd_soc_dai *dai)
808 {
809 struct snd_soc_component *component = dai->component;
810 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
811 u32 clk = 0;
812 int index;
813
814 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
815 if (index >= 0) {
816 cs42l52->sysclk = clk_map_table[index].mclk;
817
818 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
819 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
820 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
821 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
822 clk_map_table[index].mclkdiv2;
823
824 snd_soc_component_write(component, CS42L52_CLK_CTL, clk);
825 } else {
826 dev_err(component->dev, "can't get correct mclk\n");
827 return -EINVAL;
828 }
829
830 return 0;
831 }
832
833 static int cs42l52_set_bias_level(struct snd_soc_component *component,
834 enum snd_soc_bias_level level)
835 {
836 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
837
838 switch (level) {
839 case SND_SOC_BIAS_ON:
840 break;
841 case SND_SOC_BIAS_PREPARE:
842 snd_soc_component_update_bits(component, CS42L52_PWRCTL1,
843 CS42L52_PWRCTL1_PDN_CODEC, 0);
844 break;
845 case SND_SOC_BIAS_STANDBY:
846 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
847 regcache_cache_only(cs42l52->regmap, false);
848 regcache_sync(cs42l52->regmap);
849 }
850 snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
851 break;
852 case SND_SOC_BIAS_OFF:
853 snd_soc_component_write(component, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
854 regcache_cache_only(cs42l52->regmap, true);
855 break;
856 }
857
858 return 0;
859 }
860
861 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
862
863 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
864 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
865 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
866 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
867
868 static const struct snd_soc_dai_ops cs42l52_ops = {
869 .hw_params = cs42l52_pcm_hw_params,
870 .mute_stream = cs42l52_mute,
871 .set_fmt = cs42l52_set_fmt,
872 .set_sysclk = cs42l52_set_sysclk,
873 .no_capture_mute = 1,
874 };
875
876 static struct snd_soc_dai_driver cs42l52_dai = {
877 .name = "cs42l52",
878 .playback = {
879 .stream_name = "Playback",
880 .channels_min = 1,
881 .channels_max = 2,
882 .rates = CS42L52_RATES,
883 .formats = CS42L52_FORMATS,
884 },
885 .capture = {
886 .stream_name = "Capture",
887 .channels_min = 1,
888 .channels_max = 2,
889 .rates = CS42L52_RATES,
890 .formats = CS42L52_FORMATS,
891 },
892 .ops = &cs42l52_ops,
893 };
894
895 static int beep_rates[] = {
896 261, 522, 585, 667, 706, 774, 889, 1000,
897 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
898 };
899
900 static void cs42l52_beep_work(struct work_struct *work)
901 {
902 struct cs42l52_private *cs42l52 =
903 container_of(work, struct cs42l52_private, beep_work);
904 struct snd_soc_component *component = cs42l52->component;
905 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
906 int i;
907 int val = 0;
908 int best = 0;
909
910 if (cs42l52->beep_rate) {
911 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
912 if (abs(cs42l52->beep_rate - beep_rates[i]) <
913 abs(cs42l52->beep_rate - beep_rates[best]))
914 best = i;
915 }
916
917 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
918 beep_rates[best], cs42l52->beep_rate);
919
920 val = (best << CS42L52_BEEP_RATE_SHIFT);
921
922 snd_soc_dapm_enable_pin(dapm, "Beep");
923 } else {
924 dev_dbg(component->dev, "Disabling beep\n");
925 snd_soc_dapm_disable_pin(dapm, "Beep");
926 }
927
928 snd_soc_component_update_bits(component, CS42L52_BEEP_FREQ,
929 CS42L52_BEEP_RATE_MASK, val);
930
931 snd_soc_dapm_sync(dapm);
932 }
933
934 /* For usability define a way of injecting beep events for the device -
935 * many systems will not have a keyboard.
936 */
937 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
938 unsigned int code, int hz)
939 {
940 struct snd_soc_component *component = input_get_drvdata(dev);
941 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
942
943 dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
944
945 switch (code) {
946 case SND_BELL:
947 if (hz)
948 hz = 261;
949 break;
950 case SND_TONE:
951 break;
952 default:
953 return -1;
954 }
955
956 /* Kick the beep from a workqueue */
957 cs42l52->beep_rate = hz;
958 schedule_work(&cs42l52->beep_work);
959 return 0;
960 }
961
962 static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
963 const char *buf, size_t count)
964 {
965 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
966 long int time;
967 int ret;
968
969 ret = kstrtol(buf, 10, &time);
970 if (ret != 0)
971 return ret;
972
973 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
974
975 return count;
976 }
977
978 static DEVICE_ATTR_WO(beep);
979
980 static void cs42l52_init_beep(struct snd_soc_component *component)
981 {
982 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
983 int ret;
984
985 cs42l52->beep = devm_input_allocate_device(component->dev);
986 if (!cs42l52->beep) {
987 dev_err(component->dev, "Failed to allocate beep device\n");
988 return;
989 }
990
991 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
992 cs42l52->beep_rate = 0;
993
994 cs42l52->beep->name = "CS42L52 Beep Generator";
995 cs42l52->beep->phys = dev_name(component->dev);
996 cs42l52->beep->id.bustype = BUS_I2C;
997
998 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
999 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1000 cs42l52->beep->event = cs42l52_beep_event;
1001 cs42l52->beep->dev.parent = component->dev;
1002 input_set_drvdata(cs42l52->beep, component);
1003
1004 ret = input_register_device(cs42l52->beep);
1005 if (ret != 0) {
1006 cs42l52->beep = NULL;
1007 dev_err(component->dev, "Failed to register beep device\n");
1008 }
1009
1010 ret = device_create_file(component->dev, &dev_attr_beep);
1011 if (ret != 0) {
1012 dev_err(component->dev, "Failed to create keyclick file: %d\n",
1013 ret);
1014 }
1015 }
1016
1017 static void cs42l52_free_beep(struct snd_soc_component *component)
1018 {
1019 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
1020
1021 device_remove_file(component->dev, &dev_attr_beep);
1022 cancel_work_sync(&cs42l52->beep_work);
1023 cs42l52->beep = NULL;
1024
1025 snd_soc_component_update_bits(component, CS42L52_BEEP_TONE_CTL,
1026 CS42L52_BEEP_EN_MASK, 0);
1027 }
1028
1029 static int cs42l52_probe(struct snd_soc_component *component)
1030 {
1031 struct cs42l52_private *cs42l52 = snd_soc_component_get_drvdata(component);
1032
1033 regcache_cache_only(cs42l52->regmap, true);
1034
1035 cs42l52_add_mic_controls(component);
1036
1037 cs42l52_init_beep(component);
1038
1039 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1040 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1041
1042 return 0;
1043 }
1044
1045 static void cs42l52_remove(struct snd_soc_component *component)
1046 {
1047 cs42l52_free_beep(component);
1048 }
1049
1050 static const struct snd_soc_component_driver soc_component_dev_cs42l52 = {
1051 .probe = cs42l52_probe,
1052 .remove = cs42l52_remove,
1053 .set_bias_level = cs42l52_set_bias_level,
1054 .controls = cs42l52_snd_controls,
1055 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1056 .dapm_widgets = cs42l52_dapm_widgets,
1057 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1058 .dapm_routes = cs42l52_audio_map,
1059 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1060 .suspend_bias_off = 1,
1061 .idle_bias_on = 1,
1062 .use_pmdown_time = 1,
1063 .endianness = 1,
1064 };
1065
1066 /* Current and threshold powerup sequence Pg37 */
1067 static const struct reg_sequence cs42l52_threshold_patch[] = {
1068
1069 { 0x00, 0x99 },
1070 { 0x3E, 0xBA },
1071 { 0x47, 0x80 },
1072 { 0x32, 0xBB },
1073 { 0x32, 0x3B },
1074 { 0x00, 0x00 },
1075
1076 };
1077
1078 static const struct regmap_config cs42l52_regmap = {
1079 .reg_bits = 8,
1080 .val_bits = 8,
1081
1082 .max_register = CS42L52_MAX_REGISTER,
1083 .reg_defaults = cs42l52_reg_defaults,
1084 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1085 .readable_reg = cs42l52_readable_register,
1086 .volatile_reg = cs42l52_volatile_register,
1087 .cache_type = REGCACHE_MAPLE,
1088 };
1089
1090 static int cs42l52_i2c_probe(struct i2c_client *i2c_client)
1091 {
1092 struct cs42l52_private *cs42l52;
1093 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1094 int ret;
1095 unsigned int devid;
1096 unsigned int reg;
1097 u32 val32;
1098
1099 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l52), GFP_KERNEL);
1100 if (cs42l52 == NULL)
1101 return -ENOMEM;
1102 cs42l52->dev = &i2c_client->dev;
1103
1104 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1105 if (IS_ERR(cs42l52->regmap)) {
1106 ret = PTR_ERR(cs42l52->regmap);
1107 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1108 return ret;
1109 }
1110 if (pdata) {
1111 cs42l52->pdata = *pdata;
1112 } else {
1113 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata),
1114 GFP_KERNEL);
1115 if (!pdata)
1116 return -ENOMEM;
1117
1118 if (i2c_client->dev.of_node) {
1119 if (of_property_read_bool(i2c_client->dev.of_node,
1120 "cirrus,mica-differential-cfg"))
1121 pdata->mica_diff_cfg = true;
1122
1123 if (of_property_read_bool(i2c_client->dev.of_node,
1124 "cirrus,micb-differential-cfg"))
1125 pdata->micb_diff_cfg = true;
1126
1127 if (of_property_read_u32(i2c_client->dev.of_node,
1128 "cirrus,micbias-lvl", &val32) >= 0)
1129 pdata->micbias_lvl = val32;
1130
1131 if (of_property_read_u32(i2c_client->dev.of_node,
1132 "cirrus,chgfreq-divisor", &val32) >= 0)
1133 pdata->chgfreq = val32;
1134
1135 pdata->reset_gpio =
1136 of_get_named_gpio(i2c_client->dev.of_node,
1137 "cirrus,reset-gpio", 0);
1138 }
1139 cs42l52->pdata = *pdata;
1140 }
1141
1142 if (cs42l52->pdata.reset_gpio) {
1143 ret = devm_gpio_request_one(&i2c_client->dev,
1144 cs42l52->pdata.reset_gpio,
1145 GPIOF_OUT_INIT_HIGH,
1146 "CS42L52 /RST");
1147 if (ret < 0) {
1148 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1149 cs42l52->pdata.reset_gpio, ret);
1150 return ret;
1151 }
1152 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1153 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1154 }
1155
1156 i2c_set_clientdata(i2c_client, cs42l52);
1157
1158 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1159 ARRAY_SIZE(cs42l52_threshold_patch));
1160 if (ret != 0)
1161 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1162 ret);
1163
1164 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®);
1165 if (ret) {
1166 dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
1167 return ret;
1168 }
1169
1170 devid = reg & CS42L52_CHIP_ID_MASK;
1171 if (devid != CS42L52_CHIP_ID) {
1172 ret = -ENODEV;
1173 dev_err(&i2c_client->dev,
1174 "CS42L52 Device ID (%X). Expected %X\n",
1175 devid, CS42L52_CHIP_ID);
1176 return ret;
1177 }
1178
1179 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1180 reg & CS42L52_CHIP_REV_MASK);
1181
1182 /* Set Platform Data */
1183 if (cs42l52->pdata.mica_diff_cfg)
1184 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1185 CS42L52_MIC_CTL_TYPE_MASK,
1186 cs42l52->pdata.mica_diff_cfg <<
1187 CS42L52_MIC_CTL_TYPE_SHIFT);
1188
1189 if (cs42l52->pdata.micb_diff_cfg)
1190 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1191 CS42L52_MIC_CTL_TYPE_MASK,
1192 cs42l52->pdata.micb_diff_cfg <<
1193 CS42L52_MIC_CTL_TYPE_SHIFT);
1194
1195 if (cs42l52->pdata.chgfreq)
1196 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1197 CS42L52_CHARGE_PUMP_MASK,
1198 cs42l52->pdata.chgfreq <<
1199 CS42L52_CHARGE_PUMP_SHIFT);
1200
1201 if (cs42l52->pdata.micbias_lvl)
1202 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1203 CS42L52_IFACE_CTL2_BIAS_LVL,
1204 cs42l52->pdata.micbias_lvl);
1205
1206 return devm_snd_soc_register_component(&i2c_client->dev,
1207 &soc_component_dev_cs42l52, &cs42l52_dai, 1);
1208 }
1209
1210 static const struct of_device_id cs42l52_of_match[] = {
1211 { .compatible = "cirrus,cs42l52", },
1212 {},
1213 };
1214 MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1215
1216
1217 static const struct i2c_device_id cs42l52_id[] = {
1218 { "cs42l52" },
1219 { }
1220 };
1221 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1222
1223 static struct i2c_driver cs42l52_i2c_driver = {
1224 .driver = {
1225 .name = "cs42l52",
1226 .of_match_table = cs42l52_of_match,
1227 },
1228 .id_table = cs42l52_id,
1229 .probe = cs42l52_i2c_probe,
1230 };
1231
1232 module_i2c_driver(cs42l52_i2c_driver);
1233
1234 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1235 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1236 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1237 MODULE_LICENSE("GPL");
1238
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