1 /*
2 * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 *
6 * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #ifndef _CS42XX8_H
14 #define _CS42XX8_H
15
16 struct cs42xx8_driver_data {
17 char name[32];
18 int num_adcs;
19 };
20
21 extern const struct dev_pm_ops cs42xx8_pm;
22 extern const struct cs42xx8_driver_data cs42448_data;
23 extern const struct cs42xx8_driver_data cs42888_data;
24 extern const struct regmap_config cs42xx8_regmap_config;
25 int cs42xx8_probe(struct device *dev, struct regmap *regmap, struct cs42xx8_driver_data *drvdata);
26
27 /* CS42888 register map */
28 #define CS42XX8_CHIPID 0x01 /* Chip ID */
29 #define CS42XX8_PWRCTL 0x02 /* Power Control */
30 #define CS42XX8_FUNCMOD 0x03 /* Functional Mode */
31 #define CS42XX8_INTF 0x04 /* Interface Formats */
32 #define CS42XX8_ADCCTL 0x05 /* ADC Control */
33 #define CS42XX8_TXCTL 0x06 /* Transition Control */
34 #define CS42XX8_DACMUTE 0x07 /* DAC Mute Control */
35 #define CS42XX8_VOLAOUT1 0x08 /* Volume Control AOUT1 */
36 #define CS42XX8_VOLAOUT2 0x09 /* Volume Control AOUT2 */
37 #define CS42XX8_VOLAOUT3 0x0A /* Volume Control AOUT3 */
38 #define CS42XX8_VOLAOUT4 0x0B /* Volume Control AOUT4 */
39 #define CS42XX8_VOLAOUT5 0x0C /* Volume Control AOUT5 */
40 #define CS42XX8_VOLAOUT6 0x0D /* Volume Control AOUT6 */
41 #define CS42XX8_VOLAOUT7 0x0E /* Volume Control AOUT7 */
42 #define CS42XX8_VOLAOUT8 0x0F /* Volume Control AOUT8 */
43 #define CS42XX8_DACINV 0x10 /* DAC Channel Invert */
44 #define CS42XX8_VOLAIN1 0x11 /* Volume Control AIN1 */
45 #define CS42XX8_VOLAIN2 0x12 /* Volume Control AIN2 */
46 #define CS42XX8_VOLAIN3 0x13 /* Volume Control AIN3 */
47 #define CS42XX8_VOLAIN4 0x14 /* Volume Control AIN4 */
48 #define CS42XX8_VOLAIN5 0x15 /* Volume Control AIN5 */
49 #define CS42XX8_VOLAIN6 0x16 /* Volume Control AIN6 */
50 #define CS42XX8_ADCINV 0x17 /* ADC Channel Invert */
51 #define CS42XX8_STATUSCTL 0x18 /* Status Control */
52 #define CS42XX8_STATUS 0x19 /* Status */
53 #define CS42XX8_STATUSM 0x1A /* Status Mask */
54 #define CS42XX8_MUTEC 0x1B /* MUTEC Pin Control */
55
56 #define CS42XX8_FIRSTREG CS42XX8_CHIPID
57 #define CS42XX8_LASTREG CS42XX8_MUTEC
58 #define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1)
59 #define CS42XX8_I2C_INCR 0x80
60
61 /* Chip I.D. and Revision Register (Address 01h) */
62 #define CS42XX8_CHIPID_CHIP_ID_MASK 0xF0
63 #define CS42XX8_CHIPID_REV_ID_MASK 0x0F
64
65 /* Power Control (Address 02h) */
66 #define CS42XX8_PWRCTL_PDN_ADC3_SHIFT 7
67 #define CS42XX8_PWRCTL_PDN_ADC3_MASK (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
68 #define CS42XX8_PWRCTL_PDN_ADC3 (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
69 #define CS42XX8_PWRCTL_PDN_ADC2_SHIFT 6
70 #define CS42XX8_PWRCTL_PDN_ADC2_MASK (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
71 #define CS42XX8_PWRCTL_PDN_ADC2 (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
72 #define CS42XX8_PWRCTL_PDN_ADC1_SHIFT 5
73 #define CS42XX8_PWRCTL_PDN_ADC1_MASK (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
74 #define CS42XX8_PWRCTL_PDN_ADC1 (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
75 #define CS42XX8_PWRCTL_PDN_DAC4_SHIFT 4
76 #define CS42XX8_PWRCTL_PDN_DAC4_MASK (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
77 #define CS42XX8_PWRCTL_PDN_DAC4 (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
78 #define CS42XX8_PWRCTL_PDN_DAC3_SHIFT 3
79 #define CS42XX8_PWRCTL_PDN_DAC3_MASK (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
80 #define CS42XX8_PWRCTL_PDN_DAC3 (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
81 #define CS42XX8_PWRCTL_PDN_DAC2_SHIFT 2
82 #define CS42XX8_PWRCTL_PDN_DAC2_MASK (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
83 #define CS42XX8_PWRCTL_PDN_DAC2 (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
84 #define CS42XX8_PWRCTL_PDN_DAC1_SHIFT 1
85 #define CS42XX8_PWRCTL_PDN_DAC1_MASK (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
86 #define CS42XX8_PWRCTL_PDN_DAC1 (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
87 #define CS42XX8_PWRCTL_PDN_SHIFT 0
88 #define CS42XX8_PWRCTL_PDN_MASK (1 << CS42XX8_PWRCTL_PDN_SHIFT)
89 #define CS42XX8_PWRCTL_PDN (1 << CS42XX8_PWRCTL_PDN_SHIFT)
90
91 /* Functional Mode (Address 03h) */
92 #define CS42XX8_FUNCMOD_DAC_FM_SHIFT 6
93 #define CS42XX8_FUNCMOD_DAC_FM_WIDTH 2
94 #define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
95 #define CS42XX8_FUNCMOD_DAC_FM(v) ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
96 #define CS42XX8_FUNCMOD_ADC_FM_SHIFT 4
97 #define CS42XX8_FUNCMOD_ADC_FM_WIDTH 2
98 #define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
99 #define CS42XX8_FUNCMOD_ADC_FM(v) ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
100 #define CS42XX8_FUNCMOD_xC_FM_MASK(x) ((x) ? CS42XX8_FUNCMOD_DAC_FM_MASK : CS42XX8_FUNCMOD_ADC_FM_MASK)
101 #define CS42XX8_FUNCMOD_xC_FM(x, v) ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v))
102 #define CS42XX8_FUNCMOD_MFREQ_SHIFT 1
103 #define CS42XX8_FUNCMOD_MFREQ_WIDTH 3
104 #define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MFREQ_SHIFT)
105 #define CS42XX8_FUNCMOD_MFREQ_256(s) ((0 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
106 #define CS42XX8_FUNCMOD_MFREQ_384(s) ((1 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
107 #define CS42XX8_FUNCMOD_MFREQ_512(s) ((2 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
108 #define CS42XX8_FUNCMOD_MFREQ_768(s) ((3 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
109 #define CS42XX8_FUNCMOD_MFREQ_1024(s) ((4 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
110
111 #define CS42XX8_FM_SINGLE 0
112 #define CS42XX8_FM_DOUBLE 1
113 #define CS42XX8_FM_QUAD 2
114 #define CS42XX8_FM_AUTO 3
115
116 /* Interface Formats (Address 04h) */
117 #define CS42XX8_INTF_FREEZE_SHIFT 7
118 #define CS42XX8_INTF_FREEZE_MASK (1 << CS42XX8_INTF_FREEZE_SHIFT)
119 #define CS42XX8_INTF_FREEZE (1 << CS42XX8_INTF_FREEZE_SHIFT)
120 #define CS42XX8_INTF_AUX_DIF_SHIFT 6
121 #define CS42XX8_INTF_AUX_DIF_MASK (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
122 #define CS42XX8_INTF_AUX_DIF (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
123 #define CS42XX8_INTF_DAC_DIF_SHIFT 3
124 #define CS42XX8_INTF_DAC_DIF_WIDTH 3
125 #define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF_SHIFT)
126 #define CS42XX8_INTF_DAC_DIF_LEFTJ (0 << CS42XX8_INTF_DAC_DIF_SHIFT)
127 #define CS42XX8_INTF_DAC_DIF_I2S (1 << CS42XX8_INTF_DAC_DIF_SHIFT)
128 #define CS42XX8_INTF_DAC_DIF_RIGHTJ (2 << CS42XX8_INTF_DAC_DIF_SHIFT)
129 #define CS42XX8_INTF_DAC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_DAC_DIF_SHIFT)
130 #define CS42XX8_INTF_DAC_DIF_ONELINE_20 (4 << CS42XX8_INTF_DAC_DIF_SHIFT)
131 #define CS42XX8_INTF_DAC_DIF_ONELINE_24 (5 << CS42XX8_INTF_DAC_DIF_SHIFT)
132 #define CS42XX8_INTF_DAC_DIF_TDM (6 << CS42XX8_INTF_DAC_DIF_SHIFT)
133 #define CS42XX8_INTF_ADC_DIF_SHIFT 0
134 #define CS42XX8_INTF_ADC_DIF_WIDTH 3
135 #define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF_SHIFT)
136 #define CS42XX8_INTF_ADC_DIF_LEFTJ (0 << CS42XX8_INTF_ADC_DIF_SHIFT)
137 #define CS42XX8_INTF_ADC_DIF_I2S (1 << CS42XX8_INTF_ADC_DIF_SHIFT)
138 #define CS42XX8_INTF_ADC_DIF_RIGHTJ (2 << CS42XX8_INTF_ADC_DIF_SHIFT)
139 #define CS42XX8_INTF_ADC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_ADC_DIF_SHIFT)
140 #define CS42XX8_INTF_ADC_DIF_ONELINE_20 (4 << CS42XX8_INTF_ADC_DIF_SHIFT)
141 #define CS42XX8_INTF_ADC_DIF_ONELINE_24 (5 << CS42XX8_INTF_ADC_DIF_SHIFT)
142 #define CS42XX8_INTF_ADC_DIF_TDM (6 << CS42XX8_INTF_ADC_DIF_SHIFT)
143
144 /* ADC Control & DAC De-Emphasis (Address 05h) */
145 #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT 7
146 #define CS42XX8_ADCCTL_ADC_HPF_FREEZE_MASK (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
147 #define CS42XX8_ADCCTL_ADC_HPF_FREEZE (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
148 #define CS42XX8_ADCCTL_DAC_DEM_SHIFT 5
149 #define CS42XX8_ADCCTL_DAC_DEM_MASK (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
150 #define CS42XX8_ADCCTL_DAC_DEM (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
151 #define CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT 4
152 #define CS42XX8_ADCCTL_ADC1_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
153 #define CS42XX8_ADCCTL_ADC1_SINGLE (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
154 #define CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT 3
155 #define CS42XX8_ADCCTL_ADC2_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
156 #define CS42XX8_ADCCTL_ADC2_SINGLE (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
157 #define CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT 2
158 #define CS42XX8_ADCCTL_ADC3_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
159 #define CS42XX8_ADCCTL_ADC3_SINGLE (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
160 #define CS42XX8_ADCCTL_AIN5_MUX_SHIFT 1
161 #define CS42XX8_ADCCTL_AIN5_MUX_MASK (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
162 #define CS42XX8_ADCCTL_AIN5_MUX (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
163 #define CS42XX8_ADCCTL_AIN6_MUX_SHIFT 0
164 #define CS42XX8_ADCCTL_AIN6_MUX_MASK (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
165 #define CS42XX8_ADCCTL_AIN6_MUX (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
166
167 /* Transition Control (Address 06h) */
168 #define CS42XX8_TXCTL_DAC_SNGVOL_SHIFT 7
169 #define CS42XX8_TXCTL_DAC_SNGVOL_MASK (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
170 #define CS42XX8_TXCTL_DAC_SNGVOL (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
171 #define CS42XX8_TXCTL_DAC_SZC_SHIFT 5
172 #define CS42XX8_TXCTL_DAC_SZC_WIDTH 2
173 #define CS42XX8_TXCTL_DAC_SZC_MASK (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_SZC_SHIFT)
174 #define CS42XX8_TXCTL_DAC_SZC_IC (0 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
175 #define CS42XX8_TXCTL_DAC_SZC_ZC (1 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
176 #define CS42XX8_TXCTL_DAC_SZC_SR (2 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
177 #define CS42XX8_TXCTL_DAC_SZC_SRZC (3 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
178 #define CS42XX8_TXCTL_AMUTE_SHIFT 4
179 #define CS42XX8_TXCTL_AMUTE_MASK (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
180 #define CS42XX8_TXCTL_AMUTE (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
181 #define CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT 3
182 #define CS42XX8_TXCTL_MUTE_ADC_SP_MASK (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
183 #define CS42XX8_TXCTL_MUTE_ADC_SP (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
184 #define CS42XX8_TXCTL_ADC_SNGVOL_SHIFT 2
185 #define CS42XX8_TXCTL_ADC_SNGVOL_MASK (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
186 #define CS42XX8_TXCTL_ADC_SNGVOL (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
187 #define CS42XX8_TXCTL_ADC_SZC_SHIFT 0
188 #define CS42XX8_TXCTL_ADC_SZC_MASK (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_SZC_SHIFT)
189 #define CS42XX8_TXCTL_ADC_SZC_IC (0 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
190 #define CS42XX8_TXCTL_ADC_SZC_ZC (1 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
191 #define CS42XX8_TXCTL_ADC_SZC_SR (2 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
192 #define CS42XX8_TXCTL_ADC_SZC_SRZC (3 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
193
194 /* DAC Channel Mute (Address 07h) */
195 #define CS42XX8_DACMUTE_AOUT(n) (0x1 << n)
196 #define CS42XX8_DACMUTE_ALL 0xff
197
198 /* Status Control (Address 18h)*/
199 #define CS42XX8_STATUSCTL_INI_SHIFT 2
200 #define CS42XX8_STATUSCTL_INI_WIDTH 2
201 #define CS42XX8_STATUSCTL_INI_MASK (((1 << CS42XX8_STATUSCTL_INI_WIDTH) - 1) << CS42XX8_STATUSCTL_INI_SHIFT)
202 #define CS42XX8_STATUSCTL_INT_ACTIVE_HIGH (0 << CS42XX8_STATUSCTL_INI_SHIFT)
203 #define CS42XX8_STATUSCTL_INT_ACTIVE_LOW (1 << CS42XX8_STATUSCTL_INI_SHIFT)
204 #define CS42XX8_STATUSCTL_INT_OPEN_DRAIN (2 << CS42XX8_STATUSCTL_INI_SHIFT)
205
206 /* Status (Address 19h)*/
207 #define CS42XX8_STATUS_DAC_CLK_ERR_SHIFT 4
208 #define CS42XX8_STATUS_DAC_CLK_ERR_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_SHIFT)
209 #define CS42XX8_STATUS_ADC_CLK_ERR_SHIFT 3
210 #define CS42XX8_STATUS_ADC_CLK_ERR_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_SHIFT)
211 #define CS42XX8_STATUS_ADC3_OVFL_SHIFT 2
212 #define CS42XX8_STATUS_ADC3_OVFL_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_SHIFT)
213 #define CS42XX8_STATUS_ADC2_OVFL_SHIFT 1
214 #define CS42XX8_STATUS_ADC2_OVFL_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_SHIFT)
215 #define CS42XX8_STATUS_ADC1_OVFL_SHIFT 0
216 #define CS42XX8_STATUS_ADC1_OVFL_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_SHIFT)
217
218 /* Status Mask (Address 1Ah) */
219 #define CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT 4
220 #define CS42XX8_STATUS_DAC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT)
221 #define CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT 3
222 #define CS42XX8_STATUS_ADC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT)
223 #define CS42XX8_STATUS_ADC3_OVFL_M_SHIFT 2
224 #define CS42XX8_STATUS_ADC3_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_M_SHIFT)
225 #define CS42XX8_STATUS_ADC2_OVFL_M_SHIFT 1
226 #define CS42XX8_STATUS_ADC2_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_M_SHIFT)
227 #define CS42XX8_STATUS_ADC1_OVFL_M_SHIFT 0
228 #define CS42XX8_STATUS_ADC1_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_M_SHIFT)
229
230 /* MUTEC Pin Control (Address 1Bh) */
231 #define CS42XX8_MUTEC_MCPOLARITY_SHIFT 1
232 #define CS42XX8_MUTEC_MCPOLARITY_MASK (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
233 #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_LOW (0 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
234 #define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_HIGH (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
235 #define CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT 0
236 #define CS42XX8_MUTEC_MUTEC_ACTIVE_MASK (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
237 #define CS42XX8_MUTEC_MUTEC_ACTIVE (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
238 #endif /* _CS42XX8_H */
239
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