1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * max98396.h -- MAX98396 ALSA SoC audio driver header
4 *
5 * Copyright(c) 2022, Analog Devices Inc.
6 */
7
8 #ifndef _MAX98396_H
9 #define _MAX98396_H
10
11 #define MAX98396_R2000_SW_RESET 0x2000
12 #define MAX98396_R2001_INT_RAW1 0x2001
13 #define MAX98396_R2002_INT_RAW2 0x2002
14 #define MAX98396_R2003_INT_RAW3 0x2003
15 #define MAX98396_R2004_INT_RAW4 0x2004
16 #define MAX98396_R2006_INT_STATE1 0x2006
17 #define MAX98396_R2007_INT_STATE2 0x2007
18 #define MAX98396_R2008_INT_STATE3 0x2008
19 #define MAX98396_R2009_INT_STATE4 0x2009
20 #define MAX98396_R200B_INT_FLAG1 0x200B
21 #define MAX98396_R200C_INT_FLAG2 0x200C
22 #define MAX98396_R200D_INT_FLAG3 0x200D
23 #define MAX98396_R200E_INT_FLAG4 0x200E
24 #define MAX98396_R2010_INT_EN1 0x2010
25 #define MAX98396_R2011_INT_EN2 0x2011
26 #define MAX98396_R2012_INT_EN3 0x2012
27 #define MAX98396_R2013_INT_EN4 0x2013
28 #define MAX98396_R2015_INT_FLAG_CLR1 0x2015
29 #define MAX98396_R2016_INT_FLAG_CLR2 0x2016
30 #define MAX98396_R2017_INT_FLAG_CLR3 0x2017
31 #define MAX98396_R2018_INT_FLAG_CLR4 0x2018
32 #define MAX98396_R201F_IRQ_CTRL 0x201F
33 #define MAX98396_R2020_THERM_WARN_THRESH 0x2020
34 #define MAX98396_R2021_THERM_WARN_THRESH2 0x2021
35 #define MAX98396_R2022_THERM_SHDN_THRESH 0x2022
36 #define MAX98396_R2023_THERM_HYSTERESIS 0x2023
37 #define MAX98396_R2024_THERM_FOLDBACK_SET 0x2024
38 #define MAX98396_R2027_THERM_FOLDBACK_EN 0x2027
39 #define MAX98396_R2030_NOISEGATE_MODE_CTRL 0x2030
40 #define MAX98396_R2033_NOISEGATE_MODE_EN 0x2033
41 #define MAX98396_R2038_CLK_MON_CTRL 0x2038
42 #define MAX98396_R2039_DATA_MON_CTRL 0x2039
43 #define MAX98396_R203F_ENABLE_CTRLS 0x203F
44 #define MAX98396_R2040_PIN_CFG 0x2040
45 #define MAX98396_R2041_PCM_MODE_CFG 0x2041
46 #define MAX98396_R2042_PCM_CLK_SETUP 0x2042
47 #define MAX98396_R2043_PCM_SR_SETUP 0x2043
48 #define MAX98396_R2044_PCM_TX_CTRL_1 0x2044
49 #define MAX98396_R2045_PCM_TX_CTRL_2 0x2045
50 #define MAX98396_R2046_PCM_TX_CTRL_3 0x2046
51 #define MAX98396_R2047_PCM_TX_CTRL_4 0x2047
52 #define MAX98396_R2048_PCM_TX_CTRL_5 0x2048
53 #define MAX98396_R2049_PCM_TX_CTRL_6 0x2049
54 #define MAX98396_R204A_PCM_TX_CTRL_7 0x204A
55 #define MAX98396_R204B_PCM_TX_CTRL_8 0x204B
56 #define MAX98396_R204C_PCM_TX_HIZ_CTRL_1 0x204C
57 #define MAX98396_R204D_PCM_TX_HIZ_CTRL_2 0x204D
58 #define MAX98396_R204E_PCM_TX_HIZ_CTRL_3 0x204E
59 #define MAX98396_R204F_PCM_TX_HIZ_CTRL_4 0x204F
60 #define MAX98396_R2050_PCM_TX_HIZ_CTRL_5 0x2050
61 #define MAX98396_R2051_PCM_TX_HIZ_CTRL_6 0x2051
62 #define MAX98396_R2052_PCM_TX_HIZ_CTRL_7 0x2052
63 #define MAX98396_R2053_PCM_TX_HIZ_CTRL_8 0x2053
64 #define MAX98396_R2055_PCM_RX_SRC1 0x2055
65 #define MAX98396_R2056_PCM_RX_SRC2 0x2056
66 #define MAX98396_R2058_PCM_BYPASS_SRC 0x2058
67 #define MAX98396_R205D_PCM_TX_SRC_EN 0x205D
68 #define MAX98396_R205E_PCM_RX_EN 0x205E
69 #define MAX98396_R205F_PCM_TX_EN 0x205F
70 #define MAX98396_R2070_ICC_RX_EN_A 0x2070
71 #define MAX98396_R2071_ICC_RX_EN_B 0x2071
72 #define MAX98396_R2072_ICC_TX_CTRL 0x2072
73 #define MAX98396_R207F_ICC_EN 0x207F
74 #define MAX98396_R2083_TONE_GEN_DC_CFG 0x2083
75 #define MAX98396_R2084_TONE_GEN_DC_LVL1 0x2084
76 #define MAX98396_R2085_TONE_GEN_DC_LVL2 0x2085
77 #define MAX98396_R2086_TONE_GEN_DC_LVL3 0x2086
78 #define MAX98396_R208F_TONE_GEN_EN 0x208F
79 #define MAX98396_R2090_AMP_VOL_CTRL 0x2090
80 #define MAX98396_R2091_AMP_PATH_GAIN 0x2091
81 #define MAX98396_R2092_AMP_DSP_CFG 0x2092
82 #define MAX98396_R2093_SSM_CFG 0x2093
83 #define MAX98396_R2094_SPK_CLS_DG_THRESH 0x2094
84 #define MAX98396_R2095_SPK_CLS_DG_HDR 0x2095
85 #define MAX98396_R2096_SPK_CLS_DG_HOLD_TIME 0x2096
86 #define MAX98396_R2097_SPK_CLS_DG_DELAY 0x2097
87 #define MAX98396_R2098_SPK_CLS_DG_MODE 0x2098
88 #define MAX98396_R2099_SPK_CLS_DG_VBAT_LVL 0x2099
89 #define MAX98396_R209A_SPK_EDGE_CTRL 0x209A
90 #define MAX98396_R209C_SPK_EDGE_CTRL1 0x209C
91 #define MAX98396_R209D_SPK_EDGE_CTRL2 0x209D
92 #define MAX98396_R209E_AMP_CLIP_GAIN 0x209E
93 #define MAX98396_R209F_BYPASS_PATH_CFG 0x209F
94 #define MAX98396_R20A0_AMP_SUPPLY_CTL 0x20A0
95 #define MAX98396_R20AF_AMP_EN 0x20AF
96 #define MAX98396_R20B0_ADC_SR 0x20B0
97 #define MAX98396_R20B1_ADC_PVDD_CFG 0x20B1
98 #define MAX98396_R20B2_ADC_VBAT_CFG 0x20B2
99 #define MAX98396_R20B3_ADC_THERMAL_CFG 0x20B3
100 #define MAX98396_R20B4_ADC_READBACK_CTRL1 0x20B4
101 #define MAX98396_R20B5_ADC_READBACK_CTRL2 0x20B5
102 #define MAX98396_R20B6_ADC_PVDD_READBACK_MSB 0x20B6
103 #define MAX98396_R20B7_ADC_PVDD_READBACK_LSB 0x20B7
104 #define MAX98396_R20B8_ADC_VBAT_READBACK_MSB 0x20B8
105 #define MAX98396_R20B9_ADC_VBAT_READBACK_LSB 0x20B9
106 #define MAX98396_R20BA_ADC_TEMP_READBACK_MSB 0x20BA
107 #define MAX98396_R20BB_ADC_TEMP_READBACK_LSB 0x20BB
108 #define MAX98396_R20BC_ADC_LO_PVDD_READBACK_MSB 0x20BC
109 #define MAX98396_R20BD_ADC_LO_PVDD_READBACK_LSB 0x20BD
110 #define MAX98396_R20BE_ADC_LO_VBAT_READBACK_MSB 0x20BE
111 #define MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB 0x20BF
112 #define MAX98396_R20C7_ADC_CFG 0x20C7
113 #define MAX98396_R20D0_DHT_CFG1 0x20D0
114 #define MAX98396_R20D1_LIMITER_CFG1 0x20D1
115 #define MAX98396_R20D2_LIMITER_CFG2 0x20D2
116 #define MAX98396_R20D3_DHT_CFG2 0x20D3
117 #define MAX98396_R20D4_DHT_CFG3 0x20D4
118 #define MAX98396_R20D5_DHT_CFG4 0x20D5
119 #define MAX98396_R20D6_DHT_HYSTERESIS_CFG 0x20D6
120 #define MAX98396_R20DF_DHT_EN 0x20DF
121 #define MAX98396_R20E0_IV_SENSE_PATH_CFG 0x20E0
122 #define MAX98396_R20E4_IV_SENSE_PATH_EN 0x20E4
123 #define MAX98396_R20E5_BPE_STATE 0x20E5
124 #define MAX98396_R20E6_BPE_L3_THRESH_MSB 0x20E6
125 #define MAX98396_R20E7_BPE_L3_THRESH_LSB 0x20E7
126 #define MAX98396_R20E8_BPE_L2_THRESH_MSB 0x20E8
127 #define MAX98396_R20E9_BPE_L2_THRESH_LSB 0x20E9
128 #define MAX98396_R20EA_BPE_L1_THRESH_MSB 0x20EA
129 #define MAX98396_R20EB_BPE_L1_THRESH_LSB 0x20EB
130 #define MAX98396_R20EC_BPE_L0_THRESH_MSB 0x20EC
131 #define MAX98396_R20ED_BPE_L0_THRESH_LSB 0x20ED
132 #define MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME 0x20EE
133 #define MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME 0x20EF
134 #define MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME 0x20F0
135 #define MAX98396_R20F1_BPE_L0_HOLD_TIME 0x20F1
136 #define MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP 0x20F2
137 #define MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP 0x20F3
138 #define MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP 0x20F4
139 #define MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP 0x20F5
140 #define MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN 0x20F6
141 #define MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN 0x20F7
142 #define MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN 0x20F8
143 #define MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN 0x20F9
144 #define MAX98396_R20FA_BPE_L3_ATT_REL_RATE 0x20FA
145 #define MAX98396_R20FB_BPE_L2_ATT_REL_RATE 0x20FB
146 #define MAX98396_R20FC_BPE_L1_ATT_REL_RATE 0x20FC
147 #define MAX98396_R20FD_BPE_L0_ATT_REL_RATE 0x20FD
148 #define MAX98396_R20FE_BPE_L3_LIMITER_CFG 0x20FE
149 #define MAX98396_R20FF_BPE_L2_LIMITER_CFG 0x20FF
150 #define MAX98396_R2100_BPE_L1_LIMITER_CFG 0x2100
151 #define MAX98396_R2101_BPE_L0_LIMITER_CFG 0x2101
152 #define MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE 0x2102
153 #define MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE 0x2103
154 #define MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE 0x2104
155 #define MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE 0x2105
156 #define MAX98396_R2106_BPE_THRESH_HYSTERESIS 0x2106
157 #define MAX98396_R2107_BPE_INFINITE_HOLD_CLR 0x2107
158 #define MAX98396_R2108_BPE_SUPPLY_SRC 0x2108
159 #define MAX98396_R2109_BPE_LOW_STATE 0x2109
160 #define MAX98396_R210A_BPE_LOW_GAIN 0x210A
161 #define MAX98396_R210B_BPE_LOW_LIMITER 0x210B
162 #define MAX98396_R210D_BPE_EN 0x210D
163 #define MAX98396_R210E_AUTO_RESTART 0x210E
164 #define MAX98396_R210F_GLOBAL_EN 0x210F
165 #define MAX98396_R21FF_REVISION_ID 0x21FF
166
167 /* MAX98927 Registers */
168 #define MAX98397_R203A_SPK_MON_THRESH 0x203A
169 #define MAX98397_R204C_PCM_TX_CTRL_9 0x204C
170 #define MAX98397_R204D_PCM_TX_HIZ_CTRL_1 0x204D
171 #define MAX98397_R204E_PCM_TX_HIZ_CTRL_2 0x204E
172 #define MAX98397_R204F_PCM_TX_HIZ_CTRL_3 0x204F
173 #define MAX98397_R2050_PCM_TX_HIZ_CTRL_4 0x2050
174 #define MAX98397_R2051_PCM_TX_HIZ_CTRL_5 0x2051
175 #define MAX98397_R2052_PCM_TX_HIZ_CTRL_6 0x2052
176 #define MAX98397_R2053_PCM_TX_HIZ_CTRL_7 0x2053
177 #define MAX98397_R2054_PCM_TX_HIZ_CTRL_8 0x2054
178 #define MAX98397_R2056_PCM_RX_SRC1 0x2056
179 #define MAX98397_R2057_PCM_RX_SRC2 0x2057
180 #define MAX98397_R2060_PCM_TX_SUPPLY_SEL 0x2060
181 #define MAX98397_R209B_SPK_PATH_WB_ONLY 0x209B
182 #define MAX98397_R20B4_ADC_VDDH_CFG 0x20B4
183 #define MAX98397_R20B5_ADC_READBACK_CTRL1 0x20B5
184 #define MAX98397_R20B6_ADC_READBACK_CTRL2 0x20B6
185 #define MAX98397_R20B7_ADC_PVDD_READBACK_MSB 0x20B7
186 #define MAX98397_R20B8_ADC_PVDD_READBACK_LSB 0x20B8
187 #define MAX98397_R20B9_ADC_VBAT_READBACK_MSB 0x20B9
188 #define MAX98397_R20BA_ADC_VBAT_READBACK_LSB 0x20BA
189 #define MAX98397_R20BB_ADC_TEMP_READBACK_MSB 0x20BB
190 #define MAX98397_R20BC_ADC_TEMP_READBACK_LSB 0x20BC
191 #define MAX98397_R20BD_ADC_VDDH__READBACK_MSB 0x20BD
192 #define MAX98397_R20BE_ADC_VDDH_READBACK_LSB 0x20BE
193 #define MAX98397_R20BF_ADC_LO_PVDD_READBACK_MSB 0x20BF
194 #define MAX98397_R20C0_ADC_LO_PVDD_READBACK_LSB 0x20C0
195 #define MAX98397_R20C1_ADC_LO_VBAT_READBACK_MSB 0x20C1
196 #define MAX98397_R20C2_ADC_LO_VBAT_READBACK_LSB 0x20C2
197 #define MAX98397_R20C3_ADC_LO_VDDH_READBACK_MSB 0x20C3
198 #define MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB 0x20C4
199 #define MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE 0x20C5
200 #define MAX98397_R22FF_REVISION_ID 0x22FF
201
202 #define GET_REG_ADDR_REV_ID(x)\
203 ((x) > 0 ? MAX98397_R22FF_REVISION_ID : MAX98396_R21FF_REVISION_ID)
204
205 /* MAX98396_R2024_THERM_FOLDBACK_SET */
206 #define MAX98396_THERM_FB_SLOPE1_SHIFT (0)
207 #define MAX98396_THERM_FB_SLOPE2_SHIFT (2)
208 #define MAX98396_THERM_FB_REL_SHIFT (4)
209 #define MAX98396_THERM_FB_HOLD_SHIFT (6)
210
211 /* MAX98396_R2038_CLK_MON_CTRL */
212 #define MAX98396_CLK_MON_AUTO_RESTART_MASK (0x1 << 0)
213 #define MAX98396_CLK_MON_AUTO_RESTART_SHIFT (0)
214
215 /* MAX98396_R2039_DATA_MON_CTRL */
216 #define MAX98396_DMON_MAG_THRESH_SHIFT (4)
217 #define MAX98396_DMON_MAG_THRESH_MASK (0x3 << MAX98396_DMON_MAG_THRESH_SHIFT)
218 #define MAX98396_DMON_STUCK_THRESH_SHIFT (2)
219 #define MAX98396_DMON_STUCK_THRESH_MASK (0x3 << MAX98396_DMON_STUCK_THRESH_SHIFT)
220 #define MAX98396_DMON_DURATION_MASK (0x3)
221
222 /* MAX98396_R203F_ENABLE_CTRLS */
223 #define MAX98396_CTRL_CMON_EN_SHIFT (0)
224 #define MAX98396_CTRL_DMON_STUCK_EN_MASK (0x1 << 1)
225 #define MAX98396_CTRL_DMON_MAG_EN_MASK (0x1 << 2)
226
227 /* MAX98396_R2041_PCM_MODE_CFG */
228 #define MAX98396_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
229 #define MAX98396_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
230 #define MAX98396_PCM_FORMAT_I2S (0x0 << 3)
231 #define MAX98396_PCM_FORMAT_LJ (0x1 << 3)
232 #define MAX98396_PCM_FORMAT_TDM_MODE0 (0x3 << 3)
233 #define MAX98396_PCM_FORMAT_TDM_MODE1 (0x4 << 3)
234 #define MAX98396_PCM_FORMAT_TDM_MODE2 (0x5 << 3)
235 #define MAX98396_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
236 #define MAX98396_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
237 #define MAX98396_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
238 #define MAX98396_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
239 #define MAX98396_PCM_MODE_CFG_LRCLKEDGE (0x1 << 1)
240
241 /* MAX98396_R2042_PCM_CLK_SETUP */
242 #define MAX98396_PCM_MODE_CFG_BCLKEDGE (0x1 << 4)
243 #define MAX98396_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
244 #define MAX98396_PCM_BCLKEDGE_BSEL_MASK (0x1F)
245
246 /* MAX98396_R2043_PCM_SR_SETUP */
247 #define MAX98396_PCM_SR_SHIFT (0)
248 #define MAX98396_IVADC_SR_SHIFT (4)
249 #define MAX98396_PCM_SR_MASK (0xF << MAX98396_PCM_SR_SHIFT)
250 #define MAX98396_IVADC_SR_MASK (0xF << MAX98396_IVADC_SR_SHIFT)
251 #define MAX98396_PCM_SR_8000 (0)
252 #define MAX98396_PCM_SR_11025 (1)
253 #define MAX98396_PCM_SR_12000 (2)
254 #define MAX98396_PCM_SR_16000 (3)
255 #define MAX98396_PCM_SR_22050 (4)
256 #define MAX98396_PCM_SR_24000 (5)
257 #define MAX98396_PCM_SR_32000 (6)
258 #define MAX98396_PCM_SR_44100 (7)
259 #define MAX98396_PCM_SR_48000 (8)
260 #define MAX98396_PCM_SR_88200 (9)
261 #define MAX98396_PCM_SR_96000 (10)
262 #define MAX98396_PCM_SR_176400 (11)
263 #define MAX98396_PCM_SR_192000 (12)
264
265 /* MAX98396_R2055_PCM_RX_SRC1 */
266 #define MAX98396_PCM_RX_MASK (0x3 << 0)
267
268 /* MAX98396_R2056_PCM_RX_SRC2 */
269 #define MAX98396_PCM_DMIX_CH1_SHIFT (0xF << 0)
270 #define MAX98396_PCM_DMIX_CH0_SRC_MASK (0xF << 0)
271 #define MAX98396_PCM_DMIX_CH1_SRC_MASK (0xF << MAX98396_PCM_DMIX_CH1_SHIFT)
272
273 /* MAX98396_R205E_PCM_RX_EN */
274 #define MAX98396_PCM_RX_EN_MASK (0x1 << 0)
275 #define MAX98396_PCM_RX_BYP_EN_MASK (0x1 << 1)
276
277 /* MAX98396_R2092_AMP_DSP_CFG */
278 #define MAX98396_DSP_SPK_DCBLK_EN_SHIFT (0)
279 #define MAX98396_DSP_SPK_DITH_EN_SHIFT (1)
280 #define MAX98396_DSP_SPK_INVERT_SHIFT (2)
281 #define MAX98396_DSP_SPK_VOL_RMPUP_SHIFT (3)
282 #define MAX98396_DSP_SPK_VOL_RMPDN_SHIFT (4)
283 #define MAX98396_DSP_SPK_SAFE_EN_SHIFT (5)
284 #define MAX98396_DSP_SPK_WB_FLT_EN_SHIFT (6)
285
286 /* MAX98396_R20A0_AMP_SUPPLY_CTL */
287 #define MAX98396_AMP_SUPPLY_NOVBAT (0x1 << 0)
288
289 /* MAX98396_R20E0_IV_SENSE_PATH_CFG */
290 #define MAX98396_IV_SENSE_DCBLK_EN_MASK (0x3 << 0)
291 #define MAX98396_IV_SENSE_DCBLK_EN_SHIFT (0)
292 #define MAX98396_IV_SENSE_DITH_EN_SHIFT (2)
293 #define MAX98396_IV_SENSE_WB_FLT_EN_SHIFT (3)
294
295 /* MAX98396_R210E_AUTO_RESTART_BEHAVIOR */
296 #define MAX98396_PVDD_UVLO_RESTART_SHFT (0)
297 #define MAX98396_VBAT_UVLO_RESTART_SHFT (1)
298 #define MAX98396_THEM_SHDN_RESTART_SHFT (2)
299 #define MAX98396_OVC_RESTART_SHFT (3)
300
301 enum {
302 CODEC_TYPE_MAX98396,
303 CODEC_TYPE_MAX98397,
304 };
305
306 #define MAX98396_NUM_CORE_SUPPLIES 3
307
308 struct max98396_priv {
309 struct regmap *regmap;
310 struct gpio_desc *reset_gpio;
311 struct regulator_bulk_data core_supplies[MAX98396_NUM_CORE_SUPPLIES];
312 struct regulator *pvdd, *vbat;
313 unsigned int v_slot;
314 unsigned int i_slot;
315 unsigned int spkfb_slot;
316 unsigned int bypass_slot;
317 bool dmon_stuck_enable;
318 unsigned int dmon_stuck_threshold;
319 bool dmon_mag_enable;
320 unsigned int dmon_mag_threshold;
321 unsigned int dmon_duration;
322 bool interleave_mode;
323 bool tdm_mode;
324 int tdm_max_samplerate;
325 int device_id;
326 };
327 #endif
328
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