1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * max98926.h -- MAX98926 ALSA SoC Audio driver
4 * Copyright 2013-2015 Maxim Integrated Products
5 */
6
7 #ifndef _MAX98926_H
8 #define _MAX98926_H
9
10 #define MAX98926_CHIP_VERSION 0x40
11 #define MAX98926_CHIP_VERSION1 0x50
12
13 #define MAX98926_VBAT_DATA 0x00
14 #define MAX98926_VBST_DATA 0x01
15 #define MAX98926_LIVE_STATUS0 0x02
16 #define MAX98926_LIVE_STATUS1 0x03
17 #define MAX98926_LIVE_STATUS2 0x04
18 #define MAX98926_STATE0 0x05
19 #define MAX98926_STATE1 0x06
20 #define MAX98926_STATE2 0x07
21 #define MAX98926_FLAG0 0x08
22 #define MAX98926_FLAG1 0x09
23 #define MAX98926_FLAG2 0x0A
24 #define MAX98926_IRQ_ENABLE0 0x0B
25 #define MAX98926_IRQ_ENABLE1 0x0C
26 #define MAX98926_IRQ_ENABLE2 0x0D
27 #define MAX98926_IRQ_CLEAR0 0x0E
28 #define MAX98926_IRQ_CLEAR1 0x0F
29 #define MAX98926_IRQ_CLEAR2 0x10
30 #define MAX98926_MAP0 0x11
31 #define MAX98926_MAP1 0x12
32 #define MAX98926_MAP2 0x13
33 #define MAX98926_MAP3 0x14
34 #define MAX98926_MAP4 0x15
35 #define MAX98926_MAP5 0x16
36 #define MAX98926_MAP6 0x17
37 #define MAX98926_MAP7 0x18
38 #define MAX98926_MAP8 0x19
39 #define MAX98926_DAI_CLK_MODE1 0x1A
40 #define MAX98926_DAI_CLK_MODE2 0x1B
41 #define MAX98926_DAI_CLK_DIV_M_MSBS 0x1C
42 #define MAX98926_DAI_CLK_DIV_M_LSBS 0x1D
43 #define MAX98926_DAI_CLK_DIV_N_MSBS 0x1E
44 #define MAX98926_DAI_CLK_DIV_N_LSBS 0x1F
45 #define MAX98926_FORMAT 0x20
46 #define MAX98926_TDM_SLOT_SELECT 0x21
47 #define MAX98926_DOUT_CFG_VMON 0x22
48 #define MAX98926_DOUT_CFG_IMON 0x23
49 #define MAX98926_DOUT_CFG_VBAT 0x24
50 #define MAX98926_DOUT_CFG_VBST 0x25
51 #define MAX98926_DOUT_CFG_FLAG 0x26
52 #define MAX98926_DOUT_HIZ_CFG1 0x27
53 #define MAX98926_DOUT_HIZ_CFG2 0x28
54 #define MAX98926_DOUT_HIZ_CFG3 0x29
55 #define MAX98926_DOUT_HIZ_CFG4 0x2A
56 #define MAX98926_DOUT_DRV_STRENGTH 0x2B
57 #define MAX98926_FILTERS 0x2C
58 #define MAX98926_GAIN 0x2D
59 #define MAX98926_GAIN_RAMPING 0x2E
60 #define MAX98926_SPK_AMP 0x2F
61 #define MAX98926_THRESHOLD 0x30
62 #define MAX98926_ALC_ATTACK 0x31
63 #define MAX98926_ALC_ATTEN_RLS 0x32
64 #define MAX98926_ALC_HOLD_RLS 0x33
65 #define MAX98926_ALC_CONFIGURATION 0x34
66 #define MAX98926_BOOST_CONVERTER 0x35
67 #define MAX98926_BLOCK_ENABLE 0x36
68 #define MAX98926_CONFIGURATION 0x37
69 #define MAX98926_GLOBAL_ENABLE 0x38
70 #define MAX98926_BOOST_LIMITER 0x3A
71 #define MAX98926_VERSION 0xFF
72
73 #define MAX98926_REG_CNT (MAX98926_R03A_BOOST_LIMITER+1)
74
75 #define MAX98926_PDM_CURRENT_MASK (1<<7)
76 #define MAX98926_PDM_CURRENT_SHIFT 7
77 #define MAX98926_PDM_VOLTAGE_MASK (1<<3)
78 #define MAX98926_PDM_VOLTAGE_SHIFT 3
79 #define MAX98926_PDM_CHANNEL_0_MASK (1<<2)
80 #define MAX98926_PDM_CHANNEL_0_SHIFT 2
81 #define MAX98926_PDM_CHANNEL_1_MASK (1<<6)
82 #define MAX98926_PDM_CHANNEL_1_SHIFT 6
83 #define MAX98926_PDM_CHANNEL_1_HIZ 5
84 #define MAX98926_PDM_CHANNEL_0_HIZ 1
85 #define MAX98926_PDM_SOURCE_0_SHIFT 0
86 #define MAX98926_PDM_SOURCE_0_MASK (1<<0)
87 #define MAX98926_PDM_SOURCE_1_MASK (1<<4)
88 #define MAX98926_PDM_SOURCE_1_SHIFT 4
89
90 /* MAX98926 Register Bit Fields */
91
92 /* MAX98926_R002_LIVE_STATUS0 */
93 #define MAX98926_THERMWARN_STATUS_MASK (1<<3)
94 #define MAX98926_THERMWARN_STATUS_SHIFT 3
95 #define MAX98926_THERMWARN_STATUS_WIDTH 1
96 #define MAX98926_THERMSHDN_STATUS_MASK (1<<1)
97 #define MAX98926_THERMSHDN_STATUS_SHIFT 1
98 #define MAX98926_THERMSHDN_STATUS_WIDTH 1
99
100 /* MAX98926_R003_LIVE_STATUS1 */
101 #define MAX98926_SPKCURNT_STATUS_MASK (1<<5)
102 #define MAX98926_SPKCURNT_STATUS_SHIFT 5
103 #define MAX98926_SPKCURNT_STATUS_WIDTH 1
104 #define MAX98926_WATCHFAIL_STATUS_MASK (1<<4)
105 #define MAX98926_WATCHFAIL_STATUS_SHIFT 4
106 #define MAX98926_WATCHFAIL_STATUS_WIDTH 1
107 #define MAX98926_ALCINFH_STATUS_MASK (1<<3)
108 #define MAX98926_ALCINFH_STATUS_SHIFT 3
109 #define MAX98926_ALCINFH_STATUS_WIDTH 1
110 #define MAX98926_ALCACT_STATUS_MASK (1<<2)
111 #define MAX98926_ALCACT_STATUS_SHIFT 2
112 #define MAX98926_ALCACT_STATUS_WIDTH 1
113 #define MAX98926_ALCMUT_STATUS_MASK (1<<1)
114 #define MAX98926_ALCMUT_STATUS_SHIFT 1
115 #define MAX98926_ALCMUT_STATUS_WIDTH 1
116 #define MAX98926_ACLP_STATUS_MASK (1<<0)
117 #define MAX98926_ACLP_STATUS_SHIFT 0
118 #define MAX98926_ACLP_STATUS_WIDTH 1
119
120 /* MAX98926_R004_LIVE_STATUS2 */
121 #define MAX98926_SLOTOVRN_STATUS_MASK (1<<6)
122 #define MAX98926_SLOTOVRN_STATUS_SHIFT 6
123 #define MAX98926_SLOTOVRN_STATUS_WIDTH 1
124 #define MAX98926_INVALSLOT_STATUS_MASK (1<<5)
125 #define MAX98926_INVALSLOT_STATUS_SHIFT 5
126 #define MAX98926_INVALSLOT_STATUS_WIDTH 1
127 #define MAX98926_SLOTCNFLT_STATUS_MASK (1<<4)
128 #define MAX98926_SLOTCNFLT_STATUS_SHIFT 4
129 #define MAX98926_SLOTCNFLT_STATUS_WIDTH 1
130 #define MAX98926_VBSTOVFL_STATUS_MASK (1<<3)
131 #define MAX98926_VBSTOVFL_STATUS_SHIFT 3
132 #define MAX98926_VBSTOVFL_STATUS_WIDTH 1
133 #define MAX98926_VBATOVFL_STATUS_MASK (1<<2)
134 #define MAX98926_VBATOVFL_STATUS_SHIFT 2
135 #define MAX98926_VBATOVFL_STATUS_WIDTH 1
136 #define MAX98926_IMONOVFL_STATUS_MASK (1<<1)
137 #define MAX98926_IMONOVFL_STATUS_SHIFT 1
138 #define MAX98926_IMONOVFL_STATUS_WIDTH 1
139 #define MAX98926_VMONOVFL_STATUS_MASK (1<<0)
140 #define MAX98926_VMONOVFL_STATUS_SHIFT 0
141 #define MAX98926_VMONOVFL_STATUS_WIDTH 1
142
143 /* MAX98926_R005_STATE0 */
144 #define MAX98926_THERMWARN_END_STATE_MASK (1<<3)
145 #define MAX98926_THERMWARN_END_STATE_SHIFT 3
146 #define MAX98926_THERMWARN_END_STATE_WIDTH 1
147 #define MAX98926_THERMWARN_BGN_STATE_MASK (1<<2)
148 #define MAX98926_THERMWARN_BGN_STATE_SHIFT 1
149 #define MAX98926_THERMWARN_BGN_STATE_WIDTH 1
150 #define MAX98926_THERMSHDN_END_STATE_MASK (1<<1)
151 #define MAX98926_THERMSHDN_END_STATE_SHIFT 1
152 #define MAX98926_THERMSHDN_END_STATE_WIDTH 1
153 #define MAX98926_THERMSHDN_BGN_STATE_MASK (1<<0)
154 #define MAX98926_THERMSHDN_BGN_STATE_SHIFT 0
155 #define MAX98926_THERMSHDN_BGN_STATE_WIDTH 1
156
157 /* MAX98926_R006_STATE1 */
158 #define MAX98926_SPRCURNT_STATE_MASK (1<<5)
159 #define MAX98926_SPRCURNT_STATE_SHIFT 5
160 #define MAX98926_SPRCURNT_STATE_WIDTH 1
161 #define MAX98926_WATCHFAIL_STATE_MASK (1<<4)
162 #define MAX98926_WATCHFAIL_STATE_SHIFT 4
163 #define MAX98926_WATCHFAIL_STATE_WIDTH 1
164 #define MAX98926_ALCINFH_STATE_MASK (1<<3)
165 #define MAX98926_ALCINFH_STATE_SHIFT 3
166 #define MAX98926_ALCINFH_STATE_WIDTH 1
167 #define MAX98926_ALCACT_STATE_MASK (1<<2)
168 #define MAX98926_ALCACT_STATE_SHIFT 2
169 #define MAX98926_ALCACT_STATE_WIDTH 1
170 #define MAX98926_ALCMUT_STATE_MASK (1<<1)
171 #define MAX98926_ALCMUT_STATE_SHIFT 1
172 #define MAX98926_ALCMUT_STATE_WIDTH 1
173 #define MAX98926_ALCP_STATE_MASK (1<<0)
174 #define MAX98926_ALCP_STATE_SHIFT 0
175 #define MAX98926_ALCP_STATE_WIDTH 1
176
177 /* MAX98926_R007_STATE2 */
178 #define MAX98926_SLOTOVRN_STATE_MASK (1<<6)
179 #define MAX98926_SLOTOVRN_STATE_SHIFT 6
180 #define MAX98926_SLOTOVRN_STATE_WIDTH 1
181 #define MAX98926_INVALSLOT_STATE_MASK (1<<5)
182 #define MAX98926_INVALSLOT_STATE_SHIFT 5
183 #define MAX98926_INVALSLOT_STATE_WIDTH 1
184 #define MAX98926_SLOTCNFLT_STATE_MASK (1<<4)
185 #define MAX98926_SLOTCNFLT_STATE_SHIFT 4
186 #define MAX98926_SLOTCNFLT_STATE_WIDTH 1
187 #define MAX98926_VBSTOVFL_STATE_MASK (1<<3)
188 #define MAX98926_VBSTOVFL_STATE_SHIFT 3
189 #define MAX98926_VBSTOVFL_STATE_WIDTH 1
190 #define MAX98926_VBATOVFL_STATE_MASK (1<<2)
191 #define MAX98926_VBATOVFL_STATE_SHIFT 2
192 #define MAX98926_VBATOVFL_STATE_WIDTH 1
193 #define MAX98926_IMONOVFL_STATE_MASK (1<<1)
194 #define MAX98926_IMONOVFL_STATE_SHIFT 1
195 #define MAX98926_IMONOVFL_STATE_WIDTH 1
196 #define MAX98926_VMONOVFL_STATE_MASK (1<<0)
197 #define MAX98926_VMONOVFL_STATE_SHIFT 0
198 #define MAX98926_VMONOVFL_STATE_WIDTH 1
199
200 /* MAX98926_R008_FLAG0 */
201 #define MAX98926_THERMWARN_END_FLAG_MASK (1<<3)
202 #define MAX98926_THERMWARN_END_FLAG_SHIFT 3
203 #define MAX98926_THERMWARN_END_FLAG_WIDTH 1
204 #define MAX98926_THERMWARN_BGN_FLAG_MASK (1<<2)
205 #define MAX98926_THERMWARN_BGN_FLAG_SHIFT 2
206 #define MAX98926_THERMWARN_BGN_FLAG_WIDTH 1
207 #define MAX98926_THERMSHDN_END_FLAG_MASK (1<<1)
208 #define MAX98926_THERMSHDN_END_FLAG_SHIFT 1
209 #define MAX98926_THERMSHDN_END_FLAG_WIDTH 1
210 #define MAX98926_THERMSHDN_BGN_FLAG_MASK (1<<0)
211 #define MAX98926_THERMSHDN_BGN_FLAG_SHIFT 0
212 #define MAX98926_THERMSHDN_BGN_FLAG_WIDTH 1
213
214 /* MAX98926_R009_FLAG1 */
215 #define MAX98926_SPKCURNT_FLAG_MASK (1<<5)
216 #define MAX98926_SPKCURNT_FLAG_SHIFT 5
217 #define MAX98926_SPKCURNT_FLAG_WIDTH 1
218 #define MAX98926_WATCHFAIL_FLAG_MASK (1<<4)
219 #define MAX98926_WATCHFAIL_FLAG_SHIFT 4
220 #define MAX98926_WATCHFAIL_FLAG_WIDTH 1
221 #define MAX98926_ALCINFH_FLAG_MASK (1<<3)
222 #define MAX98926_ALCINFH_FLAG_SHIFT 3
223 #define MAX98926_ALCINFH_FLAG_WIDTH 1
224 #define MAX98926_ALCACT_FLAG_MASK (1<<2)
225 #define MAX98926_ALCACT_FLAG_SHIFT 2
226 #define MAX98926_ALCACT_FLAG_WIDTH 1
227 #define MAX98926_ALCMUT_FLAG_MASK (1<<1)
228 #define MAX98926_ALCMUT_FLAG_SHIFT 1
229 #define MAX98926_ALCMUT_FLAG_WIDTH 1
230 #define MAX98926_ALCP_FLAG_MASK (1<<0)
231 #define MAX98926_ALCP_FLAG_SHIFT 0
232 #define MAX98926_ALCP_FLAG_WIDTH 1
233
234 /* MAX98926_R00A_FLAG2 */
235 #define MAX98926_SLOTOVRN_FLAG_MASK (1<<6)
236 #define MAX98926_SLOTOVRN_FLAG_SHIFT 6
237 #define MAX98926_SLOTOVRN_FLAG_WIDTH 1
238 #define MAX98926_INVALSLOT_FLAG_MASK (1<<5)
239 #define MAX98926_INVALSLOT_FLAG_SHIFT 5
240 #define MAX98926_INVALSLOT_FLAG_WIDTH 1
241 #define MAX98926_SLOTCNFLT_FLAG_MASK (1<<4)
242 #define MAX98926_SLOTCNFLT_FLAG_SHIFT 4
243 #define MAX98926_SLOTCNFLT_FLAG_WIDTH 1
244 #define MAX98926_VBSTOVFL_FLAG_MASK (1<<3)
245 #define MAX98926_VBSTOVFL_FLAG_SHIFT 3
246 #define MAX98926_VBSTOVFL_FLAG_WIDTH 1
247 #define MAX98926_VBATOVFL_FLAG_MASK (1<<2)
248 #define MAX98926_VBATOVFL_FLAG_SHIFT 2
249 #define MAX98926_VBATOVFL_FLAG_WIDTH 1
250 #define MAX98926_IMONOVFL_FLAG_MASK (1<<1)
251 #define MAX98926_IMONOVFL_FLAG_SHIFT 1
252 #define MAX98926_IMONOVFL_FLAG_WIDTH 1
253 #define MAX98926_VMONOVFL_FLAG_MASK (1<<0)
254 #define MAX98926_VMONOVFL_FLAG_SHIFT 0
255 #define MAX98926_VMONOVFL_FLAG_WIDTH 1
256
257 /* MAX98926_R00B_IRQ_ENABLE0 */
258 #define MAX98926_THERMWARN_END_EN_MASK (1<<3)
259 #define MAX98926_THERMWARN_END_EN_SHIFT 3
260 #define MAX98926_THERMWARN_END_EN_WIDTH 1
261 #define MAX98926_THERMWARN_BGN_EN_MASK (1<<2)
262 #define MAX98926_THERMWARN_BGN_EN_SHIFT 2
263 #define MAX98926_THERMWARN_BGN_EN_WIDTH 1
264 #define MAX98926_THERMSHDN_END_EN_MASK (1<<1)
265 #define MAX98926_THERMSHDN_END_EN_SHIFT 1
266 #define MAX98926_THERMSHDN_END_EN_WIDTH 1
267 #define MAX98926_THERMSHDN_BGN_EN_MASK (1<<0)
268 #define MAX98926_THERMSHDN_BGN_EN_SHIFT 0
269 #define MAX98926_THERMSHDN_BGN_EN_WIDTH 1
270
271 /* MAX98926_R00C_IRQ_ENABLE1 */
272 #define MAX98926_SPKCURNT_EN_MASK (1<<5)
273 #define MAX98926_SPKCURNT_EN_SHIFT 5
274 #define MAX98926_SPKCURNT_EN_WIDTH 1
275 #define MAX98926_WATCHFAIL_EN_MASK (1<<4)
276 #define MAX98926_WATCHFAIL_EN_SHIFT 4
277 #define MAX98926_WATCHFAIL_EN_WIDTH 1
278 #define MAX98926_ALCINFH_EN_MASK (1<<3)
279 #define MAX98926_ALCINFH_EN_SHIFT 3
280 #define MAX98926_ALCINFH_EN_WIDTH 1
281 #define MAX98926_ALCACT_EN_MASK (1<<2)
282 #define MAX98926_ALCACT_EN_SHIFT 2
283 #define MAX98926_ALCACT_EN_WIDTH 1
284 #define MAX98926_ALCMUT_EN_MASK (1<<1)
285 #define MAX98926_ALCMUT_EN_SHIFT 1
286 #define MAX98926_ALCMUT_EN_WIDTH 1
287 #define MAX98926_ALCP_EN_MASK (1<<0)
288 #define MAX98926_ALCP_EN_SHIFT 0
289 #define MAX98926_ALCP_EN_WIDTH 1
290
291 /* MAX98926_R00D_IRQ_ENABLE2 */
292 #define MAX98926_SLOTOVRN_EN_MASK (1<<6)
293 #define MAX98926_SLOTOVRN_EN_SHIFT 6
294 #define MAX98926_SLOTOVRN_EN_WIDTH 1
295 #define MAX98926_INVALSLOT_EN_MASK (1<<5)
296 #define MAX98926_INVALSLOT_EN_SHIFT 5
297 #define MAX98926_INVALSLOT_EN_WIDTH 1
298 #define MAX98926_SLOTCNFLT_EN_MASK (1<<4)
299 #define MAX98926_SLOTCNFLT_EN_SHIFT 4
300 #define MAX98926_SLOTCNFLT_EN_WIDTH 1
301 #define MAX98926_VBSTOVFL_EN_MASK (1<<3)
302 #define MAX98926_VBSTOVFL_EN_SHIFT 3
303 #define MAX98926_VBSTOVFL_EN_WIDTH 1
304 #define MAX98926_VBATOVFL_EN_MASK (1<<2)
305 #define MAX98926_VBATOVFL_EN_SHIFT 2
306 #define MAX98926_VBATOVFL_EN_WIDTH 1
307 #define MAX98926_IMONOVFL_EN_MASK (1<<1)
308 #define MAX98926_IMONOVFL_EN_SHIFT 1
309 #define MAX98926_IMONOVFL_EN_WIDTH 1
310 #define MAX98926_VMONOVFL_EN_MASK (1<<0)
311 #define MAX98926_VMONOVFL_EN_SHIFT 0
312 #define MAX98926_VMONOVFL_EN_WIDTH 1
313
314 /* MAX98926_R00E_IRQ_CLEAR0 */
315 #define MAX98926_THERMWARN_END_CLR_MASK (1<<3)
316 #define MAX98926_THERMWARN_END_CLR_SHIFT 3
317 #define MAX98926_THERMWARN_END_CLR_WIDTH 1
318 #define MAX98926_THERMWARN_BGN_CLR_MASK (1<<2)
319 #define MAX98926_THERMWARN_BGN_CLR_SHIFT 2
320 #define MAX98926_THERMWARN_BGN_CLR_WIDTH 1
321 #define MAX98926_THERMSHDN_END_CLR_MASK (1<<1)
322 #define MAX98926_THERMSHDN_END_CLR_SHIFT 1
323 #define MAX98926_THERMSHDN_END_CLR_WIDTH 1
324 #define MAX98926_THERMSHDN_BGN_CLR_MASK (1<<0)
325 #define MAX98926_THERMSHDN_BGN_CLR_SHIFT 0
326 #define MAX98926_THERMSHDN_BGN_CLR_WIDTH 1
327
328 /* MAX98926_R00F_IRQ_CLEAR1 */
329 #define MAX98926_SPKCURNT_CLR_MASK (1<<5)
330 #define MAX98926_SPKCURNT_CLR_SHIFT 5
331 #define MAX98926_SPKCURNT_CLR_WIDTH 1
332 #define MAX98926_WATCHFAIL_CLR_MASK (1<<4)
333 #define MAX98926_WATCHFAIL_CLR_SHIFT 4
334 #define MAX98926_WATCHFAIL_CLR_WIDTH 1
335 #define MAX98926_ALCINFH_CLR_MASK (1<<3)
336 #define MAX98926_ALCINFH_CLR_SHIFT 3
337 #define MAX98926_ALCINFH_CLR_WIDTH 1
338 #define MAX98926_ALCACT_CLR_MASK (1<<2)
339 #define MAX98926_ALCACT_CLR_SHIFT 2
340 #define MAX98926_ALCACT_CLR_WIDTH 1
341 #define MAX98926_ALCMUT_CLR_MASK (1<<1)
342 #define MAX98926_ALCMUT_CLR_SHIFT 1
343 #define MAX98926_ALCMUT_CLR_WIDTH 1
344 #define MAX98926_ALCP_CLR_MASK (1<<0)
345 #define MAX98926_ALCP_CLR_SHIFT 0
346 #define MAX98926_ALCP_CLR_WIDTH 1
347
348 /* MAX98926_R010_IRQ_CLEAR2 */
349 #define MAX98926_SLOTOVRN_CLR_MASK (1<<6)
350 #define MAX98926_SLOTOVRN_CLR_SHIFT 6
351 #define MAX98926_SLOTOVRN_CLR_WIDTH 1
352 #define MAX98926_INVALSLOT_CLR_MASK (1<<5)
353 #define MAX98926_INVALSLOT_CLR_SHIFT 5
354 #define MAX98926_INVALSLOT_CLR_WIDTH 1
355 #define MAX98926_SLOTCNFLT_CLR_MASK (1<<4)
356 #define MAX98926_SLOTCNFLT_CLR_SHIFT 4
357 #define MAX98926_SLOTCNFLT_CLR_WIDTH 1
358 #define MAX98926_VBSTOVFL_CLR_MASK (1<<3)
359 #define MAX98926_VBSTOVFL_CLR_SHIFT 3
360 #define MAX98926_VBSTOVFL_CLR_WIDTH 1
361 #define MAX98926_VBATOVFL_CLR_MASK (1<<2)
362 #define MAX98926_VBATOVFL_CLR_SHIFT 2
363 #define MAX98926_VBATOVFL_CLR_WIDTH 1
364 #define MAX98926_IMONOVFL_CLR_MASK (1<<1)
365 #define MAX98926_IMONOVFL_CLR_SHIFT 1
366 #define MAX98926_IMONOVFL_CLR_WIDTH 1
367 #define MAX98926_VMONOVFL_CLR_MASK (1<<0)
368 #define MAX98926_VMONOVFL_CLR_SHIFT 0
369 #define MAX98926_VMONOVFL_CLR_WIDTH 1
370
371 /* MAX98926_R011_MAP0 */
372 #define MAX98926_ER_THERMWARN_EN_MASK (1<<7)
373 #define MAX98926_ER_THERMWARN_EN_SHIFT 7
374 #define MAX98926_ER_THERMWARN_EN_WIDTH 1
375 #define MAX98926_ER_THERMWARN_MAP_MASK (0x07<<4)
376 #define MAX98926_ER_THERMWARN_MAP_SHIFT 4
377 #define MAX98926_ER_THERMWARN_MAP_WIDTH 3
378
379 /* MAX98926_R012_MAP1 */
380 #define MAX98926_ER_ALCMUT_EN_MASK (1<<7)
381 #define MAX98926_ER_ALCMUT_EN_SHIFT 7
382 #define MAX98926_ER_ALCMUT_EN_WIDTH 1
383 #define MAX98926_ER_ALCMUT_MAP_MASK (0x07<<4)
384 #define MAX98926_ER_ALCMUT_MAP_SHIFT 4
385 #define MAX98926_ER_ALCMUT_MAP_WIDTH 3
386 #define MAX98926_ER_ALCP_EN_MASK (1<<3)
387 #define MAX98926_ER_ALCP_EN_SHIFT 3
388 #define MAX98926_ER_ALCP_EN_WIDTH 1
389 #define MAX98926_ER_ALCP_MAP_MASK (0x07<<0)
390 #define MAX98926_ER_ALCP_MAP_SHIFT 0
391 #define MAX98926_ER_ALCP_MAP_WIDTH 3
392
393 /* MAX98926_R013_MAP2 */
394 #define MAX98926_ER_ALCINFH_EN_MASK (1<<7)
395 #define MAX98926_ER_ALCINFH_EN_SHIFT 7
396 #define MAX98926_ER_ALCINFH_EN_WIDTH 1
397 #define MAX98926_ER_ALCINFH_MAP_MASK (0x07<<4)
398 #define MAX98926_ER_ALCINFH_MAP_SHIFT 4
399 #define MAX98926_ER_ALCINFH_MAP_WIDTH 3
400 #define MAX98926_ER_ALCACT_EN_MASK (1<<3)
401 #define MAX98926_ER_ALCACT_EN_SHIFT 3
402 #define MAX98926_ER_ALCACT_EN_WIDTH 1
403 #define MAX98926_ER_ALCACT_MAP_MASK (0x07<<0)
404 #define MAX98926_ER_ALCACT_MAP_SHIFT 0
405 #define MAX98926_ER_ALCACT_MAP_WIDTH 3
406
407 /* MAX98926_R014_MAP3 */
408 #define MAX98926_ER_SPKCURNT_EN_MASK (1<<7)
409 #define MAX98926_ER_SPKCURNT_EN_SHIFT 7
410 #define MAX98926_ER_SPKCURNT_EN_WIDTH 1
411 #define MAX98926_ER_SPKCURNT_MAP_MASK (0x07<<4)
412 #define MAX98926_ER_SPKCURNT_MAP_SHIFT 4
413 #define MAX98926_ER_SPKCURNT_MAP_WIDTH 3
414
415 /* MAX98926_R015_MAP4 */
416 /* RESERVED */
417
418 /* MAX98926_R016_MAP5 */
419 #define MAX98926_ER_IMONOVFL_EN_MASK (1<<7)
420 #define MAX98926_ER_IMONOVFL_EN_SHIFT 7
421 #define MAX98926_ER_IMONOVFL_EN_WIDTH 1
422 #define MAX98926_ER_IMONOVFL_MAP_MASK (0x07<<4)
423 #define MAX98926_ER_IMONOVFL_MAP_SHIFT 4
424 #define MAX98926_ER_IMONOVFL_MAP_WIDTH 3
425 #define MAX98926_ER_VMONOVFL_EN_MASK (1<<3)
426 #define MAX98926_ER_VMONOVFL_EN_SHIFT 3
427 #define MAX98926_ER_VMONOVFL_EN_WIDTH 1
428 #define MAX98926_ER_VMONOVFL_MAP_MASK (0x07<<0)
429 #define MAX98926_ER_VMONOVFL_MAP_SHIFT 0
430 #define MAX98926_ER_VMONOVFL_MAP_WIDTH 3
431
432 /* MAX98926_R017_MAP6 */
433 #define MAX98926_ER_VBSTOVFL_EN_MASK (1<<7)
434 #define MAX98926_ER_VBSTOVFL_EN_SHIFT 7
435 #define MAX98926_ER_VBSTOVFL_EN_WIDTH 1
436 #define MAX98926_ER_VBSTOVFL_MAP_MASK (0x07<<4)
437 #define MAX98926_ER_VBSTOVFL_MAP_SHIFT 4
438 #define MAX98926_ER_VBSTOVFL_MAP_WIDTH 3
439 #define MAX98926_ER_VBATOVFL_EN_MASK (1<<3)
440 #define MAX98926_ER_VBATOVFL_EN_SHIFT 3
441 #define MAX98926_ER_VBATOVFL_EN_WIDTH 1
442 #define MAX98926_ER_VBATOVFL_MAP_MASK (0x07<<0)
443 #define MAX98926_ER_VBATOVFL_MAP_SHIFT 0
444 #define MAX98926_ER_VBATOVFL_MAP_WIDTH 3
445
446 /* MAX98926_R018_MAP7 */
447 #define MAX98926_ER_INVALSLOT_EN_MASK (1<<7)
448 #define MAX98926_ER_INVALSLOT_EN_SHIFT 7
449 #define MAX98926_ER_INVALSLOT_EN_WIDTH 1
450 #define MAX98926_ER_INVALSLOT_MAP_MASK (0x07<<4)
451 #define MAX98926_ER_INVALSLOT_MAP_SHIFT 4
452 #define MAX98926_ER_INVALSLOT_MAP_WIDTH 3
453 #define MAX98926_ER_SLOTCNFLT_EN_MASK (1<<3)
454 #define MAX98926_ER_SLOTCNFLT_EN_SHIFT 3
455 #define MAX98926_ER_SLOTCNFLT_EN_WIDTH 1
456 #define MAX98926_ER_SLOTCNFLT_MAP_MASK (0x07<<0)
457 #define MAX98926_ER_SLOTCNFLT_MAP_SHIFT 0
458 #define MAX98926_ER_SLOTCNFLT_MAP_WIDTH 3
459
460 /* MAX98926_R019_MAP8 */
461 #define MAX98926_ER_SLOTOVRN_EN_MASK (1<<3)
462 #define MAX98926_ER_SLOTOVRN_EN_SHIFT 3
463 #define MAX98926_ER_SLOTOVRN_EN_WIDTH 1
464 #define MAX98926_ER_SLOTOVRN_MAP_MASK (0x07<<0)
465 #define MAX98926_ER_SLOTOVRN_MAP_SHIFT 0
466 #define MAX98926_ER_SLOTOVRN_MAP_WIDTH 3
467
468 /* MAX98926_R01A_DAI_CLK_MODE1 */
469 #define MAX98926_DAI_CLK_SOURCE_MASK (1<<6)
470 #define MAX98926_DAI_CLK_SOURCE_SHIFT 6
471 #define MAX98926_DAI_CLK_SOURCE_WIDTH 1
472 #define MAX98926_MDLL_MULT_MASK (0x0F<<0)
473 #define MAX98926_MDLL_MULT_SHIFT 0
474 #define MAX98926_MDLL_MULT_WIDTH 4
475
476 #define MAX98926_MDLL_MULT_MCLKx8 6
477 #define MAX98926_MDLL_MULT_MCLKx16 8
478
479 /* MAX98926_R01B_DAI_CLK_MODE2 */
480 #define MAX98926_DAI_SR_MASK (0x0F<<4)
481 #define MAX98926_DAI_SR_SHIFT 4
482 #define MAX98926_DAI_SR_WIDTH 4
483 #define MAX98926_DAI_MAS_MASK (1<<3)
484 #define MAX98926_DAI_MAS_SHIFT 3
485 #define MAX98926_DAI_MAS_WIDTH 1
486 #define MAX98926_DAI_BSEL_MASK (0x07<<0)
487 #define MAX98926_DAI_BSEL_SHIFT 0
488 #define MAX98926_DAI_BSEL_WIDTH 3
489
490 #define MAX98926_DAI_BSEL_32 (0 << MAX98926_DAI_BSEL_SHIFT)
491 #define MAX98926_DAI_BSEL_48 (1 << MAX98926_DAI_BSEL_SHIFT)
492 #define MAX98926_DAI_BSEL_64 (2 << MAX98926_DAI_BSEL_SHIFT)
493 #define MAX98926_DAI_BSEL_256 (6 << MAX98926_DAI_BSEL_SHIFT)
494
495 /* MAX98926_R01C_DAI_CLK_DIV_M_MSBS */
496 #define MAX98926_DAI_M_MSBS_MASK (0xFF<<0)
497 #define MAX98926_DAI_M_MSBS_SHIFT 0
498 #define MAX98926_DAI_M_MSBS_WIDTH 8
499
500 /* MAX98926_R01D_DAI_CLK_DIV_M_LSBS */
501 #define MAX98926_DAI_M_LSBS_MASK (0xFF<<0)
502 #define MAX98926_DAI_M_LSBS_SHIFT 0
503 #define MAX98926_DAI_M_LSBS_WIDTH 8
504
505 /* MAX98926_R01E_DAI_CLK_DIV_N_MSBS */
506 #define MAX98926_DAI_N_MSBS_MASK (0x7F<<0)
507 #define MAX98926_DAI_N_MSBS_SHIFT 0
508 #define MAX98926_DAI_N_MSBS_WIDTH 7
509
510 /* MAX98926_R01F_DAI_CLK_DIV_N_LSBS */
511 #define MAX98926_DAI_N_LSBS_MASK (0xFF<<0)
512 #define MAX98926_DAI_N_LSBS_SHIFT 0
513 #define MAX98926_DAI_N_LSBS_WIDTH 8
514
515 /* MAX98926_R020_FORMAT */
516 #define MAX98926_DAI_CHANSZ_MASK (0x03<<6)
517 #define MAX98926_DAI_CHANSZ_SHIFT 6
518 #define MAX98926_DAI_CHANSZ_WIDTH 2
519 #define MAX98926_DAI_INTERLEAVE_MASK (1<<5)
520 #define MAX98926_DAI_INTERLEAVE_SHIFT 5
521 #define MAX98926_DAI_INTERLEAVE_WIDTH 1
522 #define MAX98926_DAI_EXTBCLK_HIZ_MASK (1<<4)
523 #define MAX98926_DAI_EXTBCLK_HIZ_SHIFT 4
524 #define MAX98926_DAI_EXTBCLK_HIZ_WIDTH 1
525 #define MAX98926_DAI_WCI_MASK (1<<3)
526 #define MAX98926_DAI_WCI_SHIFT 3
527 #define MAX98926_DAI_WCI_WIDTH 1
528 #define MAX98926_DAI_BCI_MASK (1<<2)
529 #define MAX98926_DAI_BCI_SHIFT 2
530 #define MAX98926_DAI_BCI_WIDTH 1
531 #define MAX98926_DAI_DLY_MASK (1<<1)
532 #define MAX98926_DAI_DLY_SHIFT 1
533 #define MAX98926_DAI_DLY_WIDTH 1
534 #define MAX98926_DAI_TDM_MASK (1<<0)
535 #define MAX98926_DAI_TDM_SHIFT 0
536 #define MAX98926_DAI_TDM_WIDTH 1
537
538 #define MAX98926_DAI_CHANSZ_16 (1 << MAX98926_DAI_CHANSZ_SHIFT)
539 #define MAX98926_DAI_CHANSZ_24 (2 << MAX98926_DAI_CHANSZ_SHIFT)
540 #define MAX98926_DAI_CHANSZ_32 (3 << MAX98926_DAI_CHANSZ_SHIFT)
541
542 /* MAX98926_R021_TDM_SLOT_SELECT */
543 #define MAX98926_DAI_DO_EN_MASK (1<<7)
544 #define MAX98926_DAI_DO_EN_SHIFT 7
545 #define MAX98926_DAI_DO_EN_WIDTH 1
546 #define MAX98926_DAI_DIN_EN_MASK (1<<6)
547 #define MAX98926_DAI_DIN_EN_SHIFT 6
548 #define MAX98926_DAI_DIN_EN_WIDTH 1
549 #define MAX98926_DAI_INR_SOURCE_MASK (0x07<<3)
550 #define MAX98926_DAI_INR_SOURCE_SHIFT 3
551 #define MAX98926_DAI_INR_SOURCE_WIDTH 3
552 #define MAX98926_DAI_INL_SOURCE_MASK (0x07<<0)
553 #define MAX98926_DAI_INL_SOURCE_SHIFT 0
554 #define MAX98926_DAI_INL_SOURCE_WIDTH 3
555
556 /* MAX98926_R022_DOUT_CFG_VMON */
557 #define MAX98926_DAI_VMON_EN_MASK (1<<5)
558 #define MAX98926_DAI_VMON_EN_SHIFT 5
559 #define MAX98926_DAI_VMON_EN_WIDTH 1
560 #define MAX98926_DAI_VMON_SLOT_MASK (0x1F<<0)
561 #define MAX98926_DAI_VMON_SLOT_SHIFT 0
562 #define MAX98926_DAI_VMON_SLOT_WIDTH 5
563
564 #define MAX98926_DAI_VMON_SLOT_00_01 (0 << MAX98926_DAI_VMON_SLOT_SHIFT)
565 #define MAX98926_DAI_VMON_SLOT_01_02 (1 << MAX98926_DAI_VMON_SLOT_SHIFT)
566 #define MAX98926_DAI_VMON_SLOT_02_03 (2 << MAX98926_DAI_VMON_SLOT_SHIFT)
567 #define MAX98926_DAI_VMON_SLOT_03_04 (3 << MAX98926_DAI_VMON_SLOT_SHIFT)
568 #define MAX98926_DAI_VMON_SLOT_04_05 (4 << MAX98926_DAI_VMON_SLOT_SHIFT)
569 #define MAX98926_DAI_VMON_SLOT_05_06 (5 << MAX98926_DAI_VMON_SLOT_SHIFT)
570 #define MAX98926_DAI_VMON_SLOT_06_07 (6 << MAX98926_DAI_VMON_SLOT_SHIFT)
571 #define MAX98926_DAI_VMON_SLOT_07_08 (7 << MAX98926_DAI_VMON_SLOT_SHIFT)
572 #define MAX98926_DAI_VMON_SLOT_08_09 (8 << MAX98926_DAI_VMON_SLOT_SHIFT)
573 #define MAX98926_DAI_VMON_SLOT_09_0A (9 << MAX98926_DAI_VMON_SLOT_SHIFT)
574 #define MAX98926_DAI_VMON_SLOT_0A_0B (10 << MAX98926_DAI_VMON_SLOT_SHIFT)
575 #define MAX98926_DAI_VMON_SLOT_0B_0C (11 << MAX98926_DAI_VMON_SLOT_SHIFT)
576 #define MAX98926_DAI_VMON_SLOT_0C_0D (12 << MAX98926_DAI_VMON_SLOT_SHIFT)
577 #define MAX98926_DAI_VMON_SLOT_0D_0E (13 << MAX98926_DAI_VMON_SLOT_SHIFT)
578 #define MAX98926_DAI_VMON_SLOT_0E_0F (14 << MAX98926_DAI_VMON_SLOT_SHIFT)
579 #define MAX98926_DAI_VMON_SLOT_0F_10 (15 << MAX98926_DAI_VMON_SLOT_SHIFT)
580 #define MAX98926_DAI_VMON_SLOT_10_11 (16 << MAX98926_DAI_VMON_SLOT_SHIFT)
581 #define MAX98926_DAI_VMON_SLOT_11_12 (17 << MAX98926_DAI_VMON_SLOT_SHIFT)
582 #define MAX98926_DAI_VMON_SLOT_12_13 (18 << MAX98926_DAI_VMON_SLOT_SHIFT)
583 #define MAX98926_DAI_VMON_SLOT_13_14 (19 << MAX98926_DAI_VMON_SLOT_SHIFT)
584 #define MAX98926_DAI_VMON_SLOT_14_15 (20 << MAX98926_DAI_VMON_SLOT_SHIFT)
585 #define MAX98926_DAI_VMON_SLOT_15_16 (21 << MAX98926_DAI_VMON_SLOT_SHIFT)
586 #define MAX98926_DAI_VMON_SLOT_16_17 (22 << MAX98926_DAI_VMON_SLOT_SHIFT)
587 #define MAX98926_DAI_VMON_SLOT_17_18 (23 << MAX98926_DAI_VMON_SLOT_SHIFT)
588 #define MAX98926_DAI_VMON_SLOT_18_19 (24 << MAX98926_DAI_VMON_SLOT_SHIFT)
589 #define MAX98926_DAI_VMON_SLOT_19_1A (25 << MAX98926_DAI_VMON_SLOT_SHIFT)
590 #define MAX98926_DAI_VMON_SLOT_1A_1B (26 << MAX98926_DAI_VMON_SLOT_SHIFT)
591 #define MAX98926_DAI_VMON_SLOT_1B_1C (27 << MAX98926_DAI_VMON_SLOT_SHIFT)
592 #define MAX98926_DAI_VMON_SLOT_1C_1D (28 << MAX98926_DAI_VMON_SLOT_SHIFT)
593 #define MAX98926_DAI_VMON_SLOT_1D_1E (29 << MAX98926_DAI_VMON_SLOT_SHIFT)
594 #define MAX98926_DAI_VMON_SLOT_1E_1F (30 << MAX98926_DAI_VMON_SLOT_SHIFT)
595
596 /* MAX98926_R023_DOUT_CFG_IMON */
597 #define MAX98926_DAI_IMON_EN_MASK (1<<5)
598 #define MAX98926_DAI_IMON_EN_SHIFT 5
599 #define MAX98926_DAI_IMON_EN_WIDTH 1
600 #define MAX98926_DAI_IMON_SLOT_MASK (0x1F<<0)
601 #define MAX98926_DAI_IMON_SLOT_SHIFT 0
602 #define MAX98926_DAI_IMON_SLOT_WIDTH 5
603
604 #define MAX98926_DAI_IMON_SLOT_00_01 (0 << MAX98926_DAI_IMON_SLOT_SHIFT)
605 #define MAX98926_DAI_IMON_SLOT_01_02 (1 << MAX98926_DAI_IMON_SLOT_SHIFT)
606 #define MAX98926_DAI_IMON_SLOT_02_03 (2 << MAX98926_DAI_IMON_SLOT_SHIFT)
607 #define MAX98926_DAI_IMON_SLOT_03_04 (3 << MAX98926_DAI_IMON_SLOT_SHIFT)
608 #define MAX98926_DAI_IMON_SLOT_04_05 (4 << MAX98926_DAI_IMON_SLOT_SHIFT)
609 #define MAX98926_DAI_IMON_SLOT_05_06 (5 << MAX98926_DAI_IMON_SLOT_SHIFT)
610 #define MAX98926_DAI_IMON_SLOT_06_07 (6 << MAX98926_DAI_IMON_SLOT_SHIFT)
611 #define MAX98926_DAI_IMON_SLOT_07_08 (7 << MAX98926_DAI_IMON_SLOT_SHIFT)
612 #define MAX98926_DAI_IMON_SLOT_08_09 (8 << MAX98926_DAI_IMON_SLOT_SHIFT)
613 #define MAX98926_DAI_IMON_SLOT_09_0A (9 << MAX98926_DAI_IMON_SLOT_SHIFT)
614 #define MAX98926_DAI_IMON_SLOT_0A_0B (10 << MAX98926_DAI_IMON_SLOT_SHIFT)
615 #define MAX98926_DAI_IMON_SLOT_0B_0C (11 << MAX98926_DAI_IMON_SLOT_SHIFT)
616 #define MAX98926_DAI_IMON_SLOT_0C_0D (12 << MAX98926_DAI_IMON_SLOT_SHIFT)
617 #define MAX98926_DAI_IMON_SLOT_0D_0E (13 << MAX98926_DAI_IMON_SLOT_SHIFT)
618 #define MAX98926_DAI_IMON_SLOT_0E_0F (14 << MAX98926_DAI_IMON_SLOT_SHIFT)
619 #define MAX98926_DAI_IMON_SLOT_0F_10 (15 << MAX98926_DAI_IMON_SLOT_SHIFT)
620 #define MAX98926_DAI_IMON_SLOT_10_11 (16 << MAX98926_DAI_IMON_SLOT_SHIFT)
621 #define MAX98926_DAI_IMON_SLOT_11_12 (17 << MAX98926_DAI_IMON_SLOT_SHIFT)
622 #define MAX98926_DAI_IMON_SLOT_12_13 (18 << MAX98926_DAI_IMON_SLOT_SHIFT)
623 #define MAX98926_DAI_IMON_SLOT_13_14 (19 << MAX98926_DAI_IMON_SLOT_SHIFT)
624 #define MAX98926_DAI_IMON_SLOT_14_15 (20 << MAX98926_DAI_IMON_SLOT_SHIFT)
625 #define MAX98926_DAI_IMON_SLOT_15_16 (21 << MAX98926_DAI_IMON_SLOT_SHIFT)
626 #define MAX98926_DAI_IMON_SLOT_16_17 (22 << MAX98926_DAI_IMON_SLOT_SHIFT)
627 #define MAX98926_DAI_IMON_SLOT_17_18 (23 << MAX98926_DAI_IMON_SLOT_SHIFT)
628 #define MAX98926_DAI_IMON_SLOT_18_19 (24 << MAX98926_DAI_IMON_SLOT_SHIFT)
629 #define MAX98926_DAI_IMON_SLOT_19_1A (25 << MAX98926_DAI_IMON_SLOT_SHIFT)
630 #define MAX98926_DAI_IMON_SLOT_1A_1B (26 << MAX98926_DAI_IMON_SLOT_SHIFT)
631 #define MAX98926_DAI_IMON_SLOT_1B_1C (27 << MAX98926_DAI_IMON_SLOT_SHIFT)
632 #define MAX98926_DAI_IMON_SLOT_1C_1D (28 << MAX98926_DAI_IMON_SLOT_SHIFT)
633 #define MAX98926_DAI_IMON_SLOT_1D_1E (29 << MAX98926_DAI_IMON_SLOT_SHIFT)
634 #define MAX98926_DAI_IMON_SLOT_1E_1F (30 << MAX98926_DAI_IMON_SLOT_SHIFT)
635
636 /* MAX98926_R024_DOUT_CFG_VBAT */
637 #define MAX98926_DAI_INTERLEAVE_SLOT_MASK (0x1F<<0)
638 #define MAX98926_DAI_INTERLEAVE_SLOT_SHIFT 0
639 #define MAX98926_DAI_INTERLEAVE_SLOT_WIDTH 5
640
641 /* MAX98926_R025_DOUT_CFG_VBST */
642 #define MAX98926_DAI_VBST_EN_MASK (1<<5)
643 #define MAX98926_DAI_VBST_EN_SHIFT 5
644 #define MAX98926_DAI_VBST_EN_WIDTH 1
645 #define MAX98926_DAI_VBST_SLOT_MASK (0x1F<<0)
646 #define MAX98926_DAI_VBST_SLOT_SHIFT 0
647 #define MAX98926_DAI_VBST_SLOT_WIDTH 5
648
649 /* MAX98926_R026_DOUT_CFG_FLAG */
650 #define MAX98926_DAI_FLAG_EN_MASK (1<<5)
651 #define MAX98926_DAI_FLAG_EN_SHIFT 5
652 #define MAX98926_DAI_FLAG_EN_WIDTH 1
653 #define MAX98926_DAI_FLAG_SLOT_MASK (0x1F<<0)
654 #define MAX98926_DAI_FLAG_SLOT_SHIFT 0
655 #define MAX98926_DAI_FLAG_SLOT_WIDTH 5
656
657 /* MAX98926_R027_DOUT_HIZ_CFG1 */
658 #define MAX98926_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0)
659 #define MAX98926_DAI_SLOT_HIZ_CFG1_SHIFT 0
660 #define MAX98926_DAI_SLOT_HIZ_CFG1_WIDTH 8
661
662 /* MAX98926_R028_DOUT_HIZ_CFG2 */
663 #define MAX98926_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0)
664 #define MAX98926_DAI_SLOT_HIZ_CFG2_SHIFT 0
665 #define MAX98926_DAI_SLOT_HIZ_CFG2_WIDTH 8
666
667 /* MAX98926_R029_DOUT_HIZ_CFG3 */
668 #define MAX98926_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0)
669 #define MAX98926_DAI_SLOT_HIZ_CFG3_SHIFT 0
670 #define MAX98926_DAI_SLOT_HIZ_CFG3_WIDTH 8
671
672 /* MAX98926_R02A_DOUT_HIZ_CFG4 */
673 #define MAX98926_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0)
674 #define MAX98926_DAI_SLOT_HIZ_CFG4_SHIFT 0
675 #define MAX98926_DAI_SLOT_HIZ_CFG4_WIDTH 8
676
677 /* MAX98926_R02B_DOUT_DRV_STRENGTH */
678 #define MAX98926_DAI_OUT_DRIVE_MASK (0x03<<0)
679 #define MAX98926_DAI_OUT_DRIVE_SHIFT 0
680 #define MAX98926_DAI_OUT_DRIVE_WIDTH 2
681
682 /* MAX98926_R02C_FILTERS */
683 #define MAX98926_ADC_DITHER_EN_MASK (1<<7)
684 #define MAX98926_ADC_DITHER_EN_SHIFT 7
685 #define MAX98926_ADC_DITHER_EN_WIDTH 1
686 #define MAX98926_IV_DCB_EN_MASK (1<<6)
687 #define MAX98926_IV_DCB_EN_SHIFT 6
688 #define MAX98926_IV_DCB_EN_WIDTH 1
689 #define MAX98926_DAC_DITHER_EN_MASK (1<<4)
690 #define MAX98926_DAC_DITHER_EN_SHIFT 4
691 #define MAX98926_DAC_DITHER_EN_WIDTH 1
692 #define MAX98926_DAC_FILTER_MODE_MASK (1<<3)
693 #define MAX98926_DAC_FILTER_MODE_SHIFT 3
694 #define MAX98926_DAC_FILTER_MODE_WIDTH 1
695 #define MAX98926_DAC_HPF_MASK (0x07<<0)
696 #define MAX98926_DAC_HPF_SHIFT 0
697 #define MAX98926_DAC_HPF_WIDTH 3
698 #define MAX98926_DAC_HPF_DISABLE (0 << MAX98926_DAC_HPF_SHIFT)
699 #define MAX98926_DAC_HPF_DC_BLOCK (1 << MAX98926_DAC_HPF_SHIFT)
700 #define MAX98926_DAC_HPF_EN_100 (2 << MAX98926_DAC_HPF_SHIFT)
701 #define MAX98926_DAC_HPF_EN_200 (3 << MAX98926_DAC_HPF_SHIFT)
702 #define MAX98926_DAC_HPF_EN_400 (4 << MAX98926_DAC_HPF_SHIFT)
703 #define MAX98926_DAC_HPF_EN_800 (5 << MAX98926_DAC_HPF_SHIFT)
704
705 /* MAX98926_R02D_GAIN */
706 #define MAX98926_DAC_IN_SEL_MASK (0x03<<5)
707 #define MAX98926_DAC_IN_SEL_SHIFT 5
708 #define MAX98926_DAC_IN_SEL_WIDTH 2
709 #define MAX98926_SPK_GAIN_MASK (0x1F<<0)
710 #define MAX98926_SPK_GAIN_SHIFT 0
711 #define MAX98926_SPK_GAIN_WIDTH 5
712
713 #define MAX98926_DAC_IN_SEL_LEFT_DAI (0 << MAX98926_DAC_IN_SEL_SHIFT)
714 #define MAX98926_DAC_IN_SEL_RIGHT_DAI (1 << MAX98926_DAC_IN_SEL_SHIFT)
715 #define MAX98926_DAC_IN_SEL_SUMMED_DAI (2 << MAX98926_DAC_IN_SEL_SHIFT)
716 #define MAX98926_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << MAX98926_DAC_IN_SEL_SHIFT)
717
718 /* MAX98926_R02E_GAIN_RAMPING */
719 #define MAX98926_SPK_RMP_EN_MASK (1<<1)
720 #define MAX98926_SPK_RMP_EN_SHIFT 1
721 #define MAX98926_SPK_RMP_EN_WIDTH 1
722 #define MAX98926_SPK_ZCD_EN_MASK (1<<0)
723 #define MAX98926_SPK_ZCD_EN_SHIFT 0
724 #define MAX98926_SPK_ZCD_EN_WIDTH 1
725
726 /* MAX98926_R02F_SPK_AMP */
727 #define MAX98926_SPK_MODE_MASK (1<<0)
728 #define MAX98926_SPK_MODE_SHIFT 0
729 #define MAX98926_SPK_MODE_WIDTH 1
730 #define MAX98926_INSELECT_MODE_MASK (1<<1)
731 #define MAX98926_INSELECT_MODE_SHIFT 1
732 #define MAX98926_INSELECT_MODE_WIDTH 1
733
734 /* MAX98926_R030_THRESHOLD */
735 #define MAX98926_ALC_EN_MASK (1<<5)
736 #define MAX98926_ALC_EN_SHIFT 5
737 #define MAX98926_ALC_EN_WIDTH 1
738 #define MAX98926_ALC_TH_MASK (0x1F<<0)
739 #define MAX98926_ALC_TH_SHIFT 0
740 #define MAX98926_ALC_TH_WIDTH 5
741
742 /* MAX98926_R031_ALC_ATTACK */
743 #define MAX98926_ALC_ATK_STEP_MASK (0x0F<<4)
744 #define MAX98926_ALC_ATK_STEP_SHIFT 4
745 #define MAX98926_ALC_ATK_STEP_WIDTH 4
746 #define MAX98926_ALC_ATK_RATE_MASK (0x7<<0)
747 #define MAX98926_ALC_ATK_RATE_SHIFT 0
748 #define MAX98926_ALC_ATK_RATE_WIDTH 3
749
750 /* MAX98926_R032_ALC_ATTEN_RLS */
751 #define MAX98926_ALC_MAX_ATTEN_MASK (0x0F<<4)
752 #define MAX98926_ALC_MAX_ATTEN_SHIFT 4
753 #define MAX98926_ALC_MAX_ATTEN_WIDTH 4
754 #define MAX98926_ALC_RLS_RATE_MASK (0x7<<0)
755 #define MAX98926_ALC_RLS_RATE_SHIFT 0
756 #define MAX98926_ALC_RLS_RATE_WIDTH 3
757
758 /* MAX98926_R033_ALC_HOLD_RLS */
759 #define MAX98926_ALC_RLS_TGR_MASK (1<<0)
760 #define MAX98926_ALC_RLS_TGR_SHIFT 0
761 #define MAX98926_ALC_RLS_TGR_WIDTH 1
762
763 /* MAX98926_R034_ALC_CONFIGURATION */
764 #define MAX98926_ALC_MUTE_EN_MASK (1<<7)
765 #define MAX98926_ALC_MUTE_EN_SHIFT 7
766 #define MAX98926_ALC_MUTE_EN_WIDTH 1
767 #define MAX98926_ALC_MUTE_DLY_MASK (0x07<<4)
768 #define MAX98926_ALC_MUTE_DLY_SHIFT 4
769 #define MAX98926_ALC_MUTE_DLY_WIDTH 3
770 #define MAX98926_ALC_RLS_DBT_MASK (0x07<<0)
771 #define MAX98926_ALC_RLS_DBT_SHIFT 0
772 #define MAX98926_ALC_RLS_DBT_WIDTH 3
773
774 /* MAX98926_R035_BOOST_CONVERTER */
775 #define MAX98926_BST_SYNC_MASK (1<<7)
776 #define MAX98926_BST_SYNC_SHIFT 7
777 #define MAX98926_BST_SYNC_WIDTH 1
778 #define MAX98926_BST_PHASE_MASK (0x03<<4)
779 #define MAX98926_BST_PHASE_SHIFT 4
780 #define MAX98926_BST_PHASE_WIDTH 2
781 #define MAX98926_BST_SKIP_MODE_MASK (0x03<<0)
782 #define MAX98926_BST_SKIP_MODE_SHIFT 0
783 #define MAX98926_BST_SKIP_MODE_WIDTH 2
784
785 /* MAX98926_R036_BLOCK_ENABLE */
786 #define MAX98926_BST_EN_MASK (1<<7)
787 #define MAX98926_BST_EN_SHIFT 7
788 #define MAX98926_BST_EN_WIDTH 1
789 #define MAX98926_WATCH_EN_MASK (1<<6)
790 #define MAX98926_WATCH_EN_SHIFT 6
791 #define MAX98926_WATCH_EN_WIDTH 1
792 #define MAX98926_CLKMON_EN_MASK (1<<5)
793 #define MAX98926_CLKMON_EN_SHIFT 5
794 #define MAX98926_CLKMON_EN_WIDTH 1
795 #define MAX98926_SPK_EN_MASK (1<<4)
796 #define MAX98926_SPK_EN_SHIFT 4
797 #define MAX98926_SPK_EN_WIDTH 1
798 #define MAX98926_ADC_VBST_EN_MASK (1<<3)
799 #define MAX98926_ADC_VBST_EN_SHIFT 3
800 #define MAX98926_ADC_VBST_EN_WIDTH 1
801 #define MAX98926_ADC_VBAT_EN_MASK (1<<2)
802 #define MAX98926_ADC_VBAT_EN_SHIFT 2
803 #define MAX98926_ADC_VBAT_EN_WIDTH 1
804 #define MAX98926_ADC_IMON_EN_MASK (1<<1)
805 #define MAX98926_ADC_IMON_EN_SHIFT 1
806 #define MAX98926_ADC_IMON_EN_WIDTH 1
807 #define MAX98926_ADC_VMON_EN_MASK (1<<0)
808 #define MAX98926_ADC_VMON_EN_SHIFT 0
809 #define MAX98926_ADC_VMON_EN_WIDTH 1
810
811 /* MAX98926_R037_CONFIGURATION */
812 #define MAX98926_BST_VOUT_MASK (0x0F<<4)
813 #define MAX98926_BST_VOUT_SHIFT 4
814 #define MAX98926_BST_VOUT_WIDTH 4
815 #define MAX98926_THERMWARN_LEVEL_MASK (0x03<<2)
816 #define MAX98926_THERMWARN_LEVEL_SHIFT 2
817 #define MAX98926_THERMWARN_LEVEL_WIDTH 2
818 #define MAX98926_WATCH_TIME_MASK (0x03<<0)
819 #define MAX98926_WATCH_TIME_SHIFT 0
820 #define MAX98926_WATCH_TIME_WIDTH 2
821
822 /* MAX98926_R038_GLOBAL_ENABLE */
823 #define MAX98926_EN_MASK (1<<7)
824 #define MAX98926_EN_SHIFT 7
825 #define MAX98926_EN_WIDTH 1
826
827 /* MAX98926_R03A_BOOST_LIMITER */
828 #define MAX98926_BST_ILIM_MASK (0xF<<4)
829 #define MAX98926_BST_ILIM_SHIFT 4
830 #define MAX98926_BST_ILIM_WIDTH 4
831
832 /* MAX98926_R0FF_VERSION */
833 #define MAX98926_REV_ID_MASK (0xFF<<0)
834 #define MAX98926_REV_ID_SHIFT 0
835 #define MAX98926_REV_ID_WIDTH 8
836
837 struct max98926_priv {
838 struct regmap *regmap;
839 struct snd_soc_component *component;
840 unsigned int sysclk;
841 unsigned int v_slot;
842 unsigned int i_slot;
843 unsigned int ch_size;
844 unsigned int interleave_mode;
845 };
846 #endif
847
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