1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8 #include <linux/platform_device.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/sched.h>
14 #include <linux/mfd/mt6397/core.h>
15 #include <linux/regulator/consumer.h>
16
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19
20 #include "mt6358.h"
21
22 enum {
23 AUDIO_ANALOG_VOLUME_HSOUTL,
24 AUDIO_ANALOG_VOLUME_HSOUTR,
25 AUDIO_ANALOG_VOLUME_HPOUTL,
26 AUDIO_ANALOG_VOLUME_HPOUTR,
27 AUDIO_ANALOG_VOLUME_LINEOUTL,
28 AUDIO_ANALOG_VOLUME_LINEOUTR,
29 AUDIO_ANALOG_VOLUME_MICAMP1,
30 AUDIO_ANALOG_VOLUME_MICAMP2,
31 AUDIO_ANALOG_VOLUME_TYPE_MAX
32 };
33
34 enum {
35 MUX_ADC_L,
36 MUX_ADC_R,
37 MUX_PGA_L,
38 MUX_PGA_R,
39 MUX_MIC_TYPE,
40 MUX_HP_L,
41 MUX_HP_R,
42 MUX_NUM,
43 };
44
45 enum {
46 DEVICE_HP,
47 DEVICE_LO,
48 DEVICE_RCV,
49 DEVICE_MIC1,
50 DEVICE_MIC2,
51 DEVICE_NUM
52 };
53
54 /* Supply widget subseq */
55 enum {
56 /* common */
57 SUPPLY_SEQ_CLK_BUF,
58 SUPPLY_SEQ_AUD_GLB,
59 SUPPLY_SEQ_CLKSQ,
60 SUPPLY_SEQ_VOW_AUD_LPW,
61 SUPPLY_SEQ_AUD_VOW,
62 SUPPLY_SEQ_VOW_CLK,
63 SUPPLY_SEQ_VOW_LDO,
64 SUPPLY_SEQ_TOP_CK,
65 SUPPLY_SEQ_TOP_CK_LAST,
66 SUPPLY_SEQ_AUD_TOP,
67 SUPPLY_SEQ_AUD_TOP_LAST,
68 SUPPLY_SEQ_AFE,
69 /* capture */
70 SUPPLY_SEQ_ADC_SUPPLY,
71 };
72
73 enum {
74 CH_L = 0,
75 CH_R,
76 NUM_CH,
77 };
78
79 #define REG_STRIDE 2
80
81 struct mt6358_priv {
82 struct device *dev;
83 struct regmap *regmap;
84
85 unsigned int dl_rate;
86 unsigned int ul_rate;
87
88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
89 unsigned int mux_select[MUX_NUM];
90
91 int dev_counter[DEVICE_NUM];
92
93 int mtkaif_protocol;
94
95 struct regulator *avdd_reg;
96
97 int wov_enabled;
98
99 int dmic_one_wire_mode;
100 };
101
102 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
103 int mtkaif_protocol)
104 {
105 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
106
107 priv->mtkaif_protocol = mtkaif_protocol;
108 return 0;
109 }
110 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol);
111
112 static void playback_gpio_set(struct mt6358_priv *priv)
113 {
114 /* set gpio mosi mode */
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
116 0x01f8, 0x01f8);
117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
118 0xffff, 0x0249);
119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
120 0xffff, 0x0249);
121 }
122
123 static void playback_gpio_reset(struct mt6358_priv *priv)
124 {
125 /* set pad_aud_*_mosi to GPIO mode and dir input
126 * reason:
127 * pad_aud_dat_mosi*, because the pin is used as boot strap
128 * don't clean clk/sync, for mtkaif protocol 2
129 */
130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
131 0x01f8, 0x01f8);
132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
133 0x01f8, 0x0000);
134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
135 0xf << 8, 0x0);
136 }
137
138 static void capture_gpio_set(struct mt6358_priv *priv)
139 {
140 /* set gpio miso mode */
141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
142 0xffff, 0xffff);
143 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
144 0xffff, 0x0249);
145 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
146 0xffff, 0x0249);
147 }
148
149 static void capture_gpio_reset(struct mt6358_priv *priv)
150 {
151 /* set pad_aud_*_miso to GPIO mode and dir input
152 * reason:
153 * pad_aud_clk_miso, because when playback only the miso_clk
154 * will also have 26m, so will have power leak
155 * pad_aud_dat_miso*, because the pin is used as boot strap
156 */
157 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
158 0xffff, 0xffff);
159 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
160 0xffff, 0x0000);
161 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
162 0xf << 12, 0x0);
163 }
164
165 /* use only when not govern by DAPM */
166 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
167 {
168 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
169 0x1 << RG_XO_AUDIO_EN_M_SFT,
170 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
171 return 0;
172 }
173
174 /* use only when not govern by DAPM */
175 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
176 {
177 /* audio clk source from internal dcxo */
178 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
179 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
180 0x0);
181
182 /* Enable/disable CLKSQ 26MHz */
183 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
184 RG_CLKSQ_EN_MASK_SFT,
185 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
186 return 0;
187 }
188
189 /* use only when not govern by DAPM */
190 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
191 {
192 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
193 RG_AUDGLB_PWRDN_VA28_MASK_SFT,
194 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
195 return 0;
196 }
197
198 /* use only when not govern by DAPM */
199 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
200 {
201 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
202 0x0066, enable ? 0x0 : 0x66);
203 return 0;
204 }
205
206 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
207 {
208 switch (priv->mtkaif_protocol) {
209 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
210 /* MTKAIF TX format setting */
211 regmap_update_bits(priv->regmap,
212 MT6358_AFE_ADDA_MTKAIF_CFG0,
213 0xffff, 0x0010);
214 /* enable aud_pad TX fifos */
215 regmap_update_bits(priv->regmap,
216 MT6358_AFE_AUD_PAD_TOP,
217 0xff00, 0x3800);
218 regmap_update_bits(priv->regmap,
219 MT6358_AFE_AUD_PAD_TOP,
220 0xff00, 0x3900);
221 break;
222 case MT6358_MTKAIF_PROTOCOL_2:
223 /* MTKAIF TX format setting */
224 regmap_update_bits(priv->regmap,
225 MT6358_AFE_ADDA_MTKAIF_CFG0,
226 0xffff, 0x0010);
227 /* enable aud_pad TX fifos */
228 regmap_update_bits(priv->regmap,
229 MT6358_AFE_AUD_PAD_TOP,
230 0xff00, 0x3100);
231 break;
232 case MT6358_MTKAIF_PROTOCOL_1:
233 default:
234 /* MTKAIF TX format setting */
235 regmap_update_bits(priv->regmap,
236 MT6358_AFE_ADDA_MTKAIF_CFG0,
237 0xffff, 0x0000);
238 /* enable aud_pad TX fifos */
239 regmap_update_bits(priv->regmap,
240 MT6358_AFE_AUD_PAD_TOP,
241 0xff00, 0x3100);
242 break;
243 }
244 return 0;
245 }
246
247 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
248 {
249 /* disable aud_pad TX fifos */
250 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
251 0xff00, 0x3000);
252 return 0;
253 }
254
255 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
256 {
257 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
258
259 playback_gpio_set(priv);
260 capture_gpio_set(priv);
261 mt6358_mtkaif_tx_enable(priv);
262
263 mt6358_set_dcxo(priv, true);
264 mt6358_set_aud_global_bias(priv, true);
265 mt6358_set_clksq(priv, true);
266 mt6358_set_topck(priv, true);
267
268 /* set dat_miso_loopback on */
269 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
270 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
271 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
272 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
273 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
274 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
275 return 0;
276 }
277 EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable);
278
279 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
280 {
281 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
282
283 /* set dat_miso_loopback off */
284 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
285 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
286 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
287 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
288 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
289 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
290
291 mt6358_set_topck(priv, false);
292 mt6358_set_clksq(priv, false);
293 mt6358_set_aud_global_bias(priv, false);
294 mt6358_set_dcxo(priv, false);
295
296 mt6358_mtkaif_tx_disable(priv);
297 playback_gpio_reset(priv);
298 capture_gpio_reset(priv);
299 return 0;
300 }
301 EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable);
302
303 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
304 int phase_1, int phase_2)
305 {
306 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
307
308 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
309 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
310 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
311 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
312 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
313 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
314 return 0;
315 }
316 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase);
317
318 /* dl pga gain */
319 enum {
320 DL_GAIN_8DB = 0,
321 DL_GAIN_0DB = 8,
322 DL_GAIN_N_1DB = 9,
323 DL_GAIN_N_10DB = 18,
324 DL_GAIN_N_40DB = 0x1f,
325 };
326
327 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
328 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
329 #define DL_GAIN_REG_MASK 0x0f9f
330
331 static void hp_zcd_disable(struct mt6358_priv *priv)
332 {
333 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
334 }
335
336 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
337 {
338 int i, stage;
339 int target = 7;
340
341 /* Enable/Reduce HPL/R main output stage step by step */
342 for (i = 0; i <= target; i++) {
343 stage = up ? i : target - i;
344 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
345 0x7 << 8, stage << 8);
346 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
347 0x7 << 11, stage << 11);
348 usleep_range(100, 150);
349 }
350 }
351
352 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
353 {
354 int i, stage;
355
356 /* Reduce HP aux feedback loop gain step by step */
357 for (i = 0; i <= 0xf; i++) {
358 stage = up ? i : 0xf - i;
359 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
360 0xf << 12, stage << 12);
361 usleep_range(100, 150);
362 }
363 }
364
365 static void hp_pull_down(struct mt6358_priv *priv, bool enable)
366 {
367 int i;
368
369 if (enable) {
370 for (i = 0x0; i <= 0x6; i++) {
371 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
372 0x7, i);
373 usleep_range(600, 700);
374 }
375 } else {
376 for (i = 0x6; i >= 0x1; i--) {
377 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
378 0x7, i);
379 usleep_range(600, 700);
380 }
381 }
382 }
383
384 static bool is_valid_hp_pga_idx(int reg_idx)
385 {
386 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
387 reg_idx == DL_GAIN_N_40DB;
388 }
389
390 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
391 {
392 int offset = 0, count = 0, reg_idx;
393
394 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
395 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
396 __func__, from, to);
397
398 dev_info(priv->dev, "%s(), from %d, to %d\n",
399 __func__, from, to);
400
401 if (to > from)
402 offset = to - from;
403 else
404 offset = from - to;
405
406 while (offset >= 0) {
407 if (to > from)
408 reg_idx = from + count;
409 else
410 reg_idx = from - count;
411
412 if (is_valid_hp_pga_idx(reg_idx)) {
413 regmap_update_bits(priv->regmap,
414 MT6358_ZCD_CON2,
415 DL_GAIN_REG_MASK,
416 (reg_idx << 7) | reg_idx);
417 usleep_range(200, 300);
418 }
419 offset--;
420 count++;
421 }
422 }
423
424 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426 {
427 struct snd_soc_component *component =
428 snd_soc_kcontrol_component(kcontrol);
429 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
430 struct soc_mixer_control *mc =
431 (struct soc_mixer_control *)kcontrol->private_value;
432 unsigned int reg = 0;
433 int ret;
434
435 ret = snd_soc_put_volsw(kcontrol, ucontrol);
436 if (ret < 0)
437 return ret;
438
439 switch (mc->reg) {
440 case MT6358_ZCD_CON2:
441 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®);
442 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
443 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
444 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
445 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
446 break;
447 case MT6358_ZCD_CON1:
448 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®);
449 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
450 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
451 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
452 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
453 break;
454 case MT6358_ZCD_CON3:
455 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®);
456 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
457 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
458 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
459 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
460 break;
461 case MT6358_AUDENC_ANA_CON0:
462 case MT6358_AUDENC_ANA_CON1:
463 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®);
464 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
465 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
466 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®);
467 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
468 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
469 break;
470 }
471
472 return ret;
473 }
474
475 static void mt6358_restore_pga(struct mt6358_priv *priv);
476
477 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv)
478 {
479 /* analog */
480 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
481 0xffff, 0x0000);
482 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
483 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
484 0xffff, 0x0800);
485 mt6358_restore_pga(priv);
486
487 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929);
488 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
489 0xffff, 0x0025);
490 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
491 0xffff, 0x0005);
492
493 /* digital */
494 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
495 0xffff, 0x0000);
496 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120);
497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff);
498 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200);
499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424);
500 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac);
501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e);
502 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000);
503 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
504 0xffff, 0x0000);
505 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
506 0xffff, 0x0451);
507 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1);
508
509 return 0;
510 }
511
512 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv)
513 {
514 /* digital */
515 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000);
516 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
517 0xffff, 0x0450);
518 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
519 0xffff, 0x0c00);
520 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100);
521 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c);
522 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879);
523 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323);
524 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400);
525 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000);
526 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8);
527 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
528 0xffff, 0x0000);
529
530 /* analog */
531 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
532 0xffff, 0x0004);
533 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
534 0xffff, 0x0000);
535 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829);
536 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
537 0xffff, 0x0000);
538 mt6358_restore_pga(priv);
539 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
540 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
541 0xffff, 0x0010);
542
543 return 0;
544 }
545
546 static int mt6358_get_wov(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol)
548 {
549 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
550 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
551
552 ucontrol->value.integer.value[0] = priv->wov_enabled;
553 return 0;
554 }
555
556 static int mt6358_put_wov(struct snd_kcontrol *kcontrol,
557 struct snd_ctl_elem_value *ucontrol)
558 {
559 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
560 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
561 int enabled = ucontrol->value.integer.value[0];
562
563 if (enabled < 0 || enabled > 1)
564 return -EINVAL;
565
566 if (priv->wov_enabled != enabled) {
567 if (enabled)
568 mt6358_enable_wov_phase2(priv);
569 else
570 mt6358_disable_wov_phase2(priv);
571
572 priv->wov_enabled = enabled;
573
574 return 1;
575 }
576
577 return 0;
578 }
579
580 static int mt6358_dmic_mode_get(struct snd_kcontrol *kcontrol,
581 struct snd_ctl_elem_value *ucontrol)
582 {
583 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
584 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
585
586 ucontrol->value.integer.value[0] = priv->dmic_one_wire_mode;
587 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode);
588
589 return 0;
590 }
591
592 static int mt6358_dmic_mode_set(struct snd_kcontrol *kcontrol,
593 struct snd_ctl_elem_value *ucontrol)
594 {
595 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
596 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
597 int enabled = ucontrol->value.integer.value[0];
598
599 if (enabled < 0 || enabled > 1)
600 return -EINVAL;
601
602 if (priv->dmic_one_wire_mode != enabled) {
603 priv->dmic_one_wire_mode = enabled;
604 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode);
605
606 return 1;
607 }
608 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode);
609
610 return 0;
611 }
612
613 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
614 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
615
616 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
617 /* dl pga gain */
618 SOC_DOUBLE_EXT_TLV("Headphone Volume",
619 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
620 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
621 SOC_DOUBLE_EXT_TLV("Lineout Volume",
622 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
623 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
624 SOC_SINGLE_EXT_TLV("Handset Volume",
625 MT6358_ZCD_CON3, 0, 0x12, 1,
626 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
627 /* ul pga gain */
628 SOC_DOUBLE_R_EXT_TLV("PGA Volume",
629 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
630 8, 4, 0,
631 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
632
633 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
634 mt6358_get_wov, mt6358_put_wov),
635
636 SOC_SINGLE_BOOL_EXT("Dmic Mode Switch", 0,
637 mt6358_dmic_mode_get, mt6358_dmic_mode_set),
638 };
639
640 /* MUX */
641 /* LOL MUX */
642 static const char * const lo_in_mux_map[] = {
643 "Open", "Mute", "Playback", "Test Mode"
644 };
645
646 static int lo_in_mux_map_value[] = {
647 0x0, 0x1, 0x2, 0x3,
648 };
649
650 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
651 MT6358_AUDDEC_ANA_CON7,
652 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
653 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
654 lo_in_mux_map,
655 lo_in_mux_map_value);
656
657 static const struct snd_kcontrol_new lo_in_mux_control =
658 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
659
660 /*HP MUX */
661 enum {
662 HP_MUX_OPEN = 0,
663 HP_MUX_HPSPK,
664 HP_MUX_HP,
665 HP_MUX_TEST_MODE,
666 HP_MUX_HP_IMPEDANCE,
667 HP_MUX_MASK = 0x7,
668 };
669
670 static const char * const hp_in_mux_map[] = {
671 "Open",
672 "LoudSPK Playback",
673 "Audio Playback",
674 "Test Mode",
675 "HP Impedance",
676 };
677
678 static int hp_in_mux_map_value[] = {
679 HP_MUX_OPEN,
680 HP_MUX_HPSPK,
681 HP_MUX_HP,
682 HP_MUX_TEST_MODE,
683 HP_MUX_HP_IMPEDANCE,
684 };
685
686 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
687 SND_SOC_NOPM,
688 0,
689 HP_MUX_MASK,
690 hp_in_mux_map,
691 hp_in_mux_map_value);
692
693 static const struct snd_kcontrol_new hpl_in_mux_control =
694 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
695
696 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
697 SND_SOC_NOPM,
698 0,
699 HP_MUX_MASK,
700 hp_in_mux_map,
701 hp_in_mux_map_value);
702
703 static const struct snd_kcontrol_new hpr_in_mux_control =
704 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
705
706 /* RCV MUX */
707 enum {
708 RCV_MUX_OPEN = 0,
709 RCV_MUX_MUTE,
710 RCV_MUX_VOICE_PLAYBACK,
711 RCV_MUX_TEST_MODE,
712 RCV_MUX_MASK = 0x3,
713 };
714
715 static const char * const rcv_in_mux_map[] = {
716 "Open", "Mute", "Voice Playback", "Test Mode"
717 };
718
719 static int rcv_in_mux_map_value[] = {
720 RCV_MUX_OPEN,
721 RCV_MUX_MUTE,
722 RCV_MUX_VOICE_PLAYBACK,
723 RCV_MUX_TEST_MODE,
724 };
725
726 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
727 SND_SOC_NOPM,
728 0,
729 RCV_MUX_MASK,
730 rcv_in_mux_map,
731 rcv_in_mux_map_value);
732
733 static const struct snd_kcontrol_new rcv_in_mux_control =
734 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
735
736 /* DAC In MUX */
737 static const char * const dac_in_mux_map[] = {
738 "Normal Path", "Sgen"
739 };
740
741 static int dac_in_mux_map_value[] = {
742 0x0, 0x1,
743 };
744
745 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
746 MT6358_AFE_TOP_CON0,
747 DL_SINE_ON_SFT,
748 DL_SINE_ON_MASK,
749 dac_in_mux_map,
750 dac_in_mux_map_value);
751
752 static const struct snd_kcontrol_new dac_in_mux_control =
753 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
754
755 /* AIF Out MUX */
756 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
757 MT6358_AFE_TOP_CON0,
758 UL_SINE_ON_SFT,
759 UL_SINE_ON_MASK,
760 dac_in_mux_map,
761 dac_in_mux_map_value);
762
763 static const struct snd_kcontrol_new aif_out_mux_control =
764 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
765
766 /* Mic Type MUX */
767 enum {
768 MIC_TYPE_MUX_IDLE = 0,
769 MIC_TYPE_MUX_ACC,
770 MIC_TYPE_MUX_DMIC,
771 MIC_TYPE_MUX_DCC,
772 MIC_TYPE_MUX_DCC_ECM_DIFF,
773 MIC_TYPE_MUX_DCC_ECM_SINGLE,
774 MIC_TYPE_MUX_MASK = 0x7,
775 };
776
777 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
778 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
779 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
780
781 static const char * const mic_type_mux_map[] = {
782 "Idle",
783 "ACC",
784 "DMIC",
785 "DCC",
786 "DCC_ECM_DIFF",
787 "DCC_ECM_SINGLE",
788 };
789
790 static int mic_type_mux_map_value[] = {
791 MIC_TYPE_MUX_IDLE,
792 MIC_TYPE_MUX_ACC,
793 MIC_TYPE_MUX_DMIC,
794 MIC_TYPE_MUX_DCC,
795 MIC_TYPE_MUX_DCC_ECM_DIFF,
796 MIC_TYPE_MUX_DCC_ECM_SINGLE,
797 };
798
799 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
800 SND_SOC_NOPM,
801 0,
802 MIC_TYPE_MUX_MASK,
803 mic_type_mux_map,
804 mic_type_mux_map_value);
805
806 static const struct snd_kcontrol_new mic_type_mux_control =
807 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
808
809 /* ADC L MUX */
810 enum {
811 ADC_MUX_IDLE = 0,
812 ADC_MUX_AIN0,
813 ADC_MUX_PREAMPLIFIER,
814 ADC_MUX_IDLE1,
815 ADC_MUX_MASK = 0x3,
816 };
817
818 static const char * const adc_left_mux_map[] = {
819 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
820 };
821
822 static int adc_mux_map_value[] = {
823 ADC_MUX_IDLE,
824 ADC_MUX_AIN0,
825 ADC_MUX_PREAMPLIFIER,
826 ADC_MUX_IDLE1,
827 };
828
829 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
830 SND_SOC_NOPM,
831 0,
832 ADC_MUX_MASK,
833 adc_left_mux_map,
834 adc_mux_map_value);
835
836 static const struct snd_kcontrol_new adc_left_mux_control =
837 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
838
839 /* ADC R MUX */
840 static const char * const adc_right_mux_map[] = {
841 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
842 };
843
844 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
845 SND_SOC_NOPM,
846 0,
847 ADC_MUX_MASK,
848 adc_right_mux_map,
849 adc_mux_map_value);
850
851 static const struct snd_kcontrol_new adc_right_mux_control =
852 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
853
854 /* PGA L MUX */
855 enum {
856 PGA_MUX_NONE = 0,
857 PGA_MUX_AIN0,
858 PGA_MUX_AIN1,
859 PGA_MUX_AIN2,
860 PGA_MUX_MASK = 0x3,
861 };
862
863 static const char * const pga_mux_map[] = {
864 "None", "AIN0", "AIN1", "AIN2"
865 };
866
867 static int pga_mux_map_value[] = {
868 PGA_MUX_NONE,
869 PGA_MUX_AIN0,
870 PGA_MUX_AIN1,
871 PGA_MUX_AIN2,
872 };
873
874 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
875 SND_SOC_NOPM,
876 0,
877 PGA_MUX_MASK,
878 pga_mux_map,
879 pga_mux_map_value);
880
881 static const struct snd_kcontrol_new pga_left_mux_control =
882 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
883
884 /* PGA R MUX */
885 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
886 SND_SOC_NOPM,
887 0,
888 PGA_MUX_MASK,
889 pga_mux_map,
890 pga_mux_map_value);
891
892 static const struct snd_kcontrol_new pga_right_mux_control =
893 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
894
895 static int mt_clksq_event(struct snd_soc_dapm_widget *w,
896 struct snd_kcontrol *kcontrol,
897 int event)
898 {
899 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
900 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
901
902 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
903
904 switch (event) {
905 case SND_SOC_DAPM_PRE_PMU:
906 /* audio clk source from internal dcxo */
907 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
908 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
909 0x0);
910 break;
911 default:
912 break;
913 }
914
915 return 0;
916 }
917
918 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
919 struct snd_kcontrol *kcontrol,
920 int event)
921 {
922 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
923 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
924
925 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
926
927 switch (event) {
928 case SND_SOC_DAPM_PRE_PMU:
929 /* sdm audio fifo clock power on */
930 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
931 /* scrambler clock on enable */
932 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
933 /* sdm power on */
934 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
935 /* sdm fifo enable */
936 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
937
938 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
939 0xff3f,
940 0x0000);
941 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
942 0xffff,
943 0x0001);
944 break;
945 case SND_SOC_DAPM_POST_PMD:
946 /* DL scrambler disabling sequence */
947 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
948 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
949 break;
950 default:
951 break;
952 }
953
954 return 0;
955 }
956
957 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
958 struct snd_kcontrol *kcontrol,
959 int event)
960 {
961 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
962 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
963
964 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
965 __func__, event, priv->dl_rate);
966
967 switch (event) {
968 case SND_SOC_DAPM_PRE_PMU:
969 playback_gpio_set(priv);
970
971 /* sdm audio fifo clock power on */
972 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
973 /* scrambler clock on enable */
974 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
975 /* sdm power on */
976 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
977 /* sdm fifo enable */
978 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
979 break;
980 case SND_SOC_DAPM_POST_PMD:
981 /* DL scrambler disabling sequence */
982 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
983 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
984
985 playback_gpio_reset(priv);
986 break;
987 default:
988 break;
989 }
990
991 return 0;
992 }
993
994 static int mtk_hp_enable(struct mt6358_priv *priv)
995 {
996 /* Pull-down HPL/R to AVSS28_AUD */
997 hp_pull_down(priv, true);
998 /* release HP CMFB gate rstb */
999 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1000 0x1 << 6, 0x1 << 6);
1001
1002 /* Reduce ESD resistance of AU_REFN */
1003 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1004
1005 /* Set HPR/HPL gain as minimum (~ -40dB) */
1006 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
1007
1008 /* Turn on DA_600K_NCP_VA18 */
1009 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1010 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1011 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1012 /* Toggle RG_DIVCKS_CHG */
1013 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1014 /* Set NCP soft start mode as default mode: 100us */
1015 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1016 /* Enable NCP */
1017 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1018 usleep_range(250, 270);
1019
1020 /* Enable cap-less LDOs (1.5V) */
1021 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1022 0x1055, 0x1055);
1023 /* Enable NV regulator (-1.2V) */
1024 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1025 usleep_range(100, 120);
1026
1027 /* Disable AUD_ZCD */
1028 hp_zcd_disable(priv);
1029
1030 /* Disable headphone short-circuit protection */
1031 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1032
1033 /* Enable IBIST */
1034 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1035
1036 /* Set HP DR bias current optimization, 010: 6uA */
1037 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1038 /* Set HP & ZCD bias current optimization */
1039 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1040 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1041 /* Set HPP/N STB enhance circuits */
1042 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1043
1044 /* Enable HP aux output stage */
1045 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
1046 /* Enable HP aux feedback loop */
1047 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
1048 /* Enable HP aux CMFB loop */
1049 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1050 /* Enable HP driver bias circuits */
1051 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1052 /* Enable HP driver core circuits */
1053 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1054 /* Short HP main output to HP aux output stage */
1055 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
1056
1057 /* Enable HP main CMFB loop */
1058 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1059 /* Disable HP aux CMFB loop */
1060 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1061
1062 /* Select CMFB resistor bulk to AC mode */
1063 /* Selec HS/LO cap size (6.5pF default) */
1064 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1065
1066 /* Enable HP main output stage */
1067 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
1068 /* Enable HPR/L main output stage step by step */
1069 hp_main_output_ramp(priv, true);
1070
1071 /* Reduce HP aux feedback loop gain */
1072 hp_aux_feedback_loop_gain_ramp(priv, true);
1073 /* Disable HP aux feedback loop */
1074 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1075
1076 /* apply volume setting */
1077 headset_volume_ramp(priv,
1078 DL_GAIN_N_10DB,
1079 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1080
1081 /* Disable HP aux output stage */
1082 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1083 /* Unshort HP main output to HP aux output stage */
1084 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
1085 usleep_range(100, 120);
1086
1087 /* Enable AUD_CLK */
1088 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1089 /* Enable Audio DAC */
1090 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
1091 /* Enable low-noise mode of DAC */
1092 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
1093 usleep_range(100, 120);
1094
1095 /* Switch HPL MUX to audio DAC */
1096 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
1097 /* Switch HPR MUX to audio DAC */
1098 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
1099
1100 /* Disable Pull-down HPL/R to AVSS28_AUD */
1101 hp_pull_down(priv, false);
1102
1103 return 0;
1104 }
1105
1106 static int mtk_hp_disable(struct mt6358_priv *priv)
1107 {
1108 /* Pull-down HPL/R to AVSS28_AUD */
1109 hp_pull_down(priv, true);
1110
1111 /* HPR/HPL mux to open */
1112 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1113 0x0f00, 0x0000);
1114
1115 /* Disable low-noise mode of DAC */
1116 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1117 0x0001, 0x0000);
1118
1119 /* Disable Audio DAC */
1120 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1121 0x000f, 0x0000);
1122
1123 /* Disable AUD_CLK */
1124 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1125
1126 /* Short HP main output to HP aux output stage */
1127 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1128 /* Enable HP aux output stage */
1129 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1130
1131 /* decrease HPL/R gain to normal gain step by step */
1132 headset_volume_ramp(priv,
1133 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1134 DL_GAIN_N_40DB);
1135
1136 /* Enable HP aux feedback loop */
1137 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1138
1139 /* Reduce HP aux feedback loop gain */
1140 hp_aux_feedback_loop_gain_ramp(priv, false);
1141
1142 /* decrease HPR/L main output stage step by step */
1143 hp_main_output_ramp(priv, false);
1144
1145 /* Disable HP main output stage */
1146 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1147
1148 /* Enable HP aux CMFB loop */
1149 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1150
1151 /* Disable HP main CMFB loop */
1152 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1153
1154 /* Unshort HP main output to HP aux output stage */
1155 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1156 0x3 << 6, 0x0);
1157
1158 /* Disable HP driver core circuits */
1159 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1160 0x3 << 4, 0x0);
1161
1162 /* Disable HP driver bias circuits */
1163 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1164 0x3 << 6, 0x0);
1165
1166 /* Disable HP aux CMFB loop */
1167 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1168
1169 /* Disable HP aux feedback loop */
1170 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1171 0x3 << 4, 0x0);
1172
1173 /* Disable HP aux output stage */
1174 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1175 0x3 << 2, 0x0);
1176
1177 /* Disable IBIST */
1178 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1179 0x1 << 8, 0x1 << 8);
1180
1181 /* Disable NV regulator (-1.2V) */
1182 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1183 /* Disable cap-less LDOs (1.5V) */
1184 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1185 0x1055, 0x0);
1186 /* Disable NCP */
1187 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1188 0x1, 0x1);
1189
1190 /* Increase ESD resistance of AU_REFN */
1191 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1192 0x1 << 14, 0x0);
1193
1194 /* Set HP CMFB gate rstb */
1195 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1196 0x1 << 6, 0x0);
1197 /* disable Pull-down HPL/R to AVSS28_AUD */
1198 hp_pull_down(priv, false);
1199
1200 return 0;
1201 }
1202
1203 static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1204 {
1205 /* Pull-down HPL/R to AVSS28_AUD */
1206 hp_pull_down(priv, true);
1207 /* release HP CMFB gate rstb */
1208 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1209 0x1 << 6, 0x1 << 6);
1210
1211 /* Reduce ESD resistance of AU_REFN */
1212 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1213
1214 /* Set HPR/HPL gain to -10dB */
1215 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1216
1217 /* Turn on DA_600K_NCP_VA18 */
1218 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1219 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1220 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1221 /* Toggle RG_DIVCKS_CHG */
1222 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1223 /* Set NCP soft start mode as default mode: 100us */
1224 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1225 /* Enable NCP */
1226 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1227 usleep_range(250, 270);
1228
1229 /* Enable cap-less LDOs (1.5V) */
1230 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1231 0x1055, 0x1055);
1232 /* Enable NV regulator (-1.2V) */
1233 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1234 usleep_range(100, 120);
1235
1236 /* Disable AUD_ZCD */
1237 hp_zcd_disable(priv);
1238
1239 /* Disable headphone short-circuit protection */
1240 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1241
1242 /* Enable IBIST */
1243 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1244
1245 /* Set HP DR bias current optimization, 010: 6uA */
1246 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1247 /* Set HP & ZCD bias current optimization */
1248 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1249 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1250 /* Set HPP/N STB enhance circuits */
1251 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1252
1253 /* Disable Pull-down HPL/R to AVSS28_AUD */
1254 hp_pull_down(priv, false);
1255
1256 /* Enable HP driver bias circuits */
1257 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1258 /* Enable HP driver core circuits */
1259 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1260 /* Enable HP main CMFB loop */
1261 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1262
1263 /* Select CMFB resistor bulk to AC mode */
1264 /* Selec HS/LO cap size (6.5pF default) */
1265 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1266
1267 /* Enable HP main output stage */
1268 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1269 /* Enable HPR/L main output stage step by step */
1270 hp_main_output_ramp(priv, true);
1271
1272 /* Set LO gain as minimum (~ -40dB) */
1273 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1274 /* apply volume setting */
1275 headset_volume_ramp(priv,
1276 DL_GAIN_N_10DB,
1277 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1278
1279 /* Set LO STB enhance circuits */
1280 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1281 /* Enable LO driver bias circuits */
1282 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1283 /* Enable LO driver core circuits */
1284 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1285
1286 /* Set LOL gain to normal gain step by step */
1287 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1288 RG_AUDLOLGAIN_MASK_SFT,
1289 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1290 RG_AUDLOLGAIN_SFT);
1291 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1292 RG_AUDLORGAIN_MASK_SFT,
1293 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1294 RG_AUDLORGAIN_SFT);
1295
1296 /* Enable AUD_CLK */
1297 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1298 /* Enable Audio DAC */
1299 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1300 /* Enable low-noise mode of DAC */
1301 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1302 /* Switch LOL MUX to audio DAC */
1303 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1304 /* Switch HPL/R MUX to Line-out */
1305 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1306
1307 return 0;
1308 }
1309
1310 static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1311 {
1312 /* HPR/HPL mux to open */
1313 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1314 0x0f00, 0x0000);
1315 /* LOL mux to open */
1316 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1317 0x3 << 2, 0x0000);
1318
1319 /* Disable Audio DAC */
1320 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1321 0x000f, 0x0000);
1322
1323 /* Disable AUD_CLK */
1324 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1325
1326 /* decrease HPL/R gain to normal gain step by step */
1327 headset_volume_ramp(priv,
1328 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1329 DL_GAIN_N_40DB);
1330
1331 /* decrease LOL gain to minimum gain step by step */
1332 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1333 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1334
1335 /* decrease HPR/L main output stage step by step */
1336 hp_main_output_ramp(priv, false);
1337
1338 /* Disable HP main output stage */
1339 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1340
1341 /* Short HP main output to HP aux output stage */
1342 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1343 /* Enable HP aux output stage */
1344 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1345
1346 /* Enable HP aux feedback loop */
1347 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1348
1349 /* Reduce HP aux feedback loop gain */
1350 hp_aux_feedback_loop_gain_ramp(priv, false);
1351
1352 /* Disable HP driver core circuits */
1353 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1354 0x3 << 4, 0x0);
1355 /* Disable LO driver core circuits */
1356 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1357 0x1, 0x0);
1358
1359 /* Disable HP driver bias circuits */
1360 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1361 0x3 << 6, 0x0);
1362 /* Disable LO driver bias circuits */
1363 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1364 0x1 << 1, 0x0);
1365
1366 /* Disable HP aux CMFB loop */
1367 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1368 0xff << 8, 0x0000);
1369
1370 /* Disable IBIST */
1371 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1372 0x1 << 8, 0x1 << 8);
1373 /* Disable NV regulator (-1.2V) */
1374 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1375 /* Disable cap-less LDOs (1.5V) */
1376 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1377 /* Disable NCP */
1378 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1379
1380 /* Set HP CMFB gate rstb */
1381 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1382 0x1 << 6, 0x0);
1383 /* disable Pull-down HPL/R to AVSS28_AUD */
1384 hp_pull_down(priv, false);
1385
1386 return 0;
1387 }
1388
1389 static int mt_hp_event(struct snd_soc_dapm_widget *w,
1390 struct snd_kcontrol *kcontrol,
1391 int event)
1392 {
1393 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1394 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1395 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1396 int device = DEVICE_HP;
1397
1398 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1399 __func__,
1400 event,
1401 priv->dev_counter[device],
1402 mux);
1403
1404 switch (event) {
1405 case SND_SOC_DAPM_PRE_PMU:
1406 priv->dev_counter[device]++;
1407 if (priv->dev_counter[device] > 1)
1408 break; /* already enabled, do nothing */
1409 else if (priv->dev_counter[device] <= 0)
1410 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1411 __func__,
1412 priv->dev_counter[device]);
1413
1414 priv->mux_select[MUX_HP_L] = mux;
1415
1416 if (mux == HP_MUX_HP)
1417 mtk_hp_enable(priv);
1418 else if (mux == HP_MUX_HPSPK)
1419 mtk_hp_spk_enable(priv);
1420 break;
1421 case SND_SOC_DAPM_PRE_PMD:
1422 priv->dev_counter[device]--;
1423 if (priv->dev_counter[device] > 0) {
1424 break; /* still being used, don't close */
1425 } else if (priv->dev_counter[device] < 0) {
1426 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1427 __func__,
1428 priv->dev_counter[device]);
1429 priv->dev_counter[device] = 0;
1430 break;
1431 }
1432
1433 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1434 mtk_hp_disable(priv);
1435 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1436 mtk_hp_spk_disable(priv);
1437
1438 priv->mux_select[MUX_HP_L] = mux;
1439 break;
1440 default:
1441 break;
1442 }
1443
1444 return 0;
1445 }
1446
1447 static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1448 struct snd_kcontrol *kcontrol,
1449 int event)
1450 {
1451 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1452 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1453
1454 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1455 __func__,
1456 event,
1457 dapm_kcontrol_get_value(w->kcontrols[0]));
1458
1459 switch (event) {
1460 case SND_SOC_DAPM_PRE_PMU:
1461 /* Reduce ESD resistance of AU_REFN */
1462 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1463
1464 /* Turn on DA_600K_NCP_VA18 */
1465 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1466 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1467 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1468 /* Toggle RG_DIVCKS_CHG */
1469 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1470 /* Set NCP soft start mode as default mode: 100us */
1471 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1472 /* Enable NCP */
1473 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1474 usleep_range(250, 270);
1475
1476 /* Enable cap-less LDOs (1.5V) */
1477 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1478 0x1055, 0x1055);
1479 /* Enable NV regulator (-1.2V) */
1480 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1481 usleep_range(100, 120);
1482
1483 /* Disable AUD_ZCD */
1484 hp_zcd_disable(priv);
1485
1486 /* Disable handset short-circuit protection */
1487 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1488
1489 /* Enable IBIST */
1490 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1491 /* Set HP DR bias current optimization, 010: 6uA */
1492 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1493 /* Set HP & ZCD bias current optimization */
1494 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1495 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1496 /* Set HS STB enhance circuits */
1497 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1498
1499 /* Disable HP main CMFB loop */
1500 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1501 /* Select CMFB resistor bulk to AC mode */
1502 /* Selec HS/LO cap size (6.5pF default) */
1503 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1504
1505 /* Enable HS driver bias circuits */
1506 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1507 /* Enable HS driver core circuits */
1508 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1509
1510 /* Enable AUD_CLK */
1511 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1512 0x1, 0x1);
1513
1514 /* Enable Audio DAC */
1515 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1516 /* Enable low-noise mode of DAC */
1517 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1518 /* Switch HS MUX to audio DAC */
1519 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1520 break;
1521 case SND_SOC_DAPM_PRE_PMD:
1522 /* HS mux to open */
1523 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1524 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1525 RCV_MUX_OPEN);
1526
1527 /* Disable Audio DAC */
1528 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1529 0x000f, 0x0000);
1530
1531 /* Disable AUD_CLK */
1532 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1533 0x1, 0x0);
1534
1535 /* decrease HS gain to minimum gain step by step */
1536 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1537
1538 /* Disable HS driver core circuits */
1539 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1540 0x1, 0x0);
1541
1542 /* Disable HS driver bias circuits */
1543 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1544 0x1 << 1, 0x0000);
1545
1546 /* Disable HP aux CMFB loop */
1547 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1548 0xff << 8, 0x0);
1549
1550 /* Enable HP main CMFB Switch */
1551 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1552 0xff << 8, 0x2 << 8);
1553
1554 /* Disable IBIST */
1555 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1556 0x1 << 8, 0x1 << 8);
1557
1558 /* Disable NV regulator (-1.2V) */
1559 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1560 0x1, 0x0);
1561 /* Disable cap-less LDOs (1.5V) */
1562 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1563 0x1055, 0x0);
1564 /* Disable NCP */
1565 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1566 0x1, 0x1);
1567 break;
1568 default:
1569 break;
1570 }
1571
1572 return 0;
1573 }
1574
1575 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1576 struct snd_kcontrol *kcontrol,
1577 int event)
1578 {
1579 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1580 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1581
1582 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1583 __func__, event, priv->ul_rate);
1584
1585 switch (event) {
1586 case SND_SOC_DAPM_PRE_PMU:
1587 capture_gpio_set(priv);
1588 break;
1589 case SND_SOC_DAPM_POST_PMD:
1590 capture_gpio_reset(priv);
1591 break;
1592 default:
1593 break;
1594 }
1595
1596 return 0;
1597 }
1598
1599 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1600 struct snd_kcontrol *kcontrol,
1601 int event)
1602 {
1603 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1604 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1605
1606 dev_dbg(priv->dev, "%s(), event 0x%x\n",
1607 __func__, event);
1608
1609 switch (event) {
1610 case SND_SOC_DAPM_PRE_PMU:
1611 /* Enable audio ADC CLKGEN */
1612 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1613 0x1 << 5, 0x1 << 5);
1614 /* ADC CLK from CLKGEN (13MHz) */
1615 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1616 0x0000);
1617 /* Enable LCLDO_ENC 1P8V */
1618 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1619 0x2500, 0x0100);
1620 /* LCLDO_ENC remote sense */
1621 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1622 0x2500, 0x2500);
1623 break;
1624 case SND_SOC_DAPM_POST_PMD:
1625 /* LCLDO_ENC remote sense off */
1626 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1627 0x2500, 0x0100);
1628 /* disable LCLDO_ENC 1P8V */
1629 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1630 0x2500, 0x0000);
1631
1632 /* ADC CLK from CLKGEN (13MHz) */
1633 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1634 /* disable audio ADC CLKGEN */
1635 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1636 0x1 << 5, 0x0 << 5);
1637 break;
1638 default:
1639 break;
1640 }
1641
1642 return 0;
1643 }
1644
1645 static int mt6358_amic_enable(struct mt6358_priv *priv)
1646 {
1647 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1648 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1649 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1650
1651 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1652 __func__, mic_type, mux_pga_l, mux_pga_r);
1653
1654 if (IS_DCC_BASE(mic_type)) {
1655 /* DCC 50k CLK (from 26M) */
1656 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1657 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1658 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1659 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1660 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1661 }
1662
1663 /* mic bias 0 */
1664 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1665 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1666 switch (mic_type) {
1667 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1668 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1669 0xff00, 0x7700);
1670 break;
1671 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1672 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1673 0xff00, 0x1100);
1674 break;
1675 default:
1676 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1677 0xff00, 0x0000);
1678 break;
1679 }
1680 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1681 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1682 0xff, 0x21);
1683 }
1684
1685 /* mic bias 1 */
1686 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1687 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1688 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1689 regmap_write(priv->regmap,
1690 MT6358_AUDENC_ANA_CON10, 0x0161);
1691 else
1692 regmap_write(priv->regmap,
1693 MT6358_AUDENC_ANA_CON10, 0x0061);
1694 }
1695
1696 if (IS_DCC_BASE(mic_type)) {
1697 /* Audio L/R preamplifier DCC precharge */
1698 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1699 0xf8ff, 0x0004);
1700 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1701 0xf8ff, 0x0004);
1702 } else {
1703 /* reset reg */
1704 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1705 0xf8ff, 0x0000);
1706 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1707 0xf8ff, 0x0000);
1708 }
1709
1710 if (mux_pga_l != PGA_MUX_NONE) {
1711 /* L preamplifier input sel */
1712 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1713 RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1714 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1715
1716 /* L preamplifier enable */
1717 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1718 RG_AUDPREAMPLON_MASK_SFT,
1719 0x1 << RG_AUDPREAMPLON_SFT);
1720
1721 if (IS_DCC_BASE(mic_type)) {
1722 /* L preamplifier DCCEN */
1723 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1724 RG_AUDPREAMPLDCCEN_MASK_SFT,
1725 0x1 << RG_AUDPREAMPLDCCEN_SFT);
1726 }
1727
1728 /* L ADC input sel : L PGA. Enable audio L ADC */
1729 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1730 RG_AUDADCLINPUTSEL_MASK_SFT,
1731 ADC_MUX_PREAMPLIFIER <<
1732 RG_AUDADCLINPUTSEL_SFT);
1733 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1734 RG_AUDADCLPWRUP_MASK_SFT,
1735 0x1 << RG_AUDADCLPWRUP_SFT);
1736 }
1737
1738 if (mux_pga_r != PGA_MUX_NONE) {
1739 /* R preamplifier input sel */
1740 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1741 RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1742 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1743
1744 /* R preamplifier enable */
1745 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1746 RG_AUDPREAMPRON_MASK_SFT,
1747 0x1 << RG_AUDPREAMPRON_SFT);
1748
1749 if (IS_DCC_BASE(mic_type)) {
1750 /* R preamplifier DCCEN */
1751 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1752 RG_AUDPREAMPRDCCEN_MASK_SFT,
1753 0x1 << RG_AUDPREAMPRDCCEN_SFT);
1754 }
1755
1756 /* R ADC input sel : R PGA. Enable audio R ADC */
1757 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1758 RG_AUDADCRINPUTSEL_MASK_SFT,
1759 ADC_MUX_PREAMPLIFIER <<
1760 RG_AUDADCRINPUTSEL_SFT);
1761 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1762 RG_AUDADCRPWRUP_MASK_SFT,
1763 0x1 << RG_AUDADCRPWRUP_SFT);
1764 }
1765
1766 if (IS_DCC_BASE(mic_type)) {
1767 usleep_range(100, 150);
1768 /* Audio L preamplifier DCC precharge off */
1769 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1770 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1771 /* Audio R preamplifier DCC precharge off */
1772 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1773 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1774
1775 /* Short body to ground in PGA */
1776 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1777 0x1 << 12, 0x0);
1778 }
1779
1780 /* here to set digital part */
1781 mt6358_mtkaif_tx_enable(priv);
1782
1783 /* UL dmic setting off */
1784 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1785
1786 /* UL turn on */
1787 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1788
1789 return 0;
1790 }
1791
1792 static void mt6358_amic_disable(struct mt6358_priv *priv)
1793 {
1794 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1795 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1796 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1797
1798 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1799 __func__, mic_type, mux_pga_l, mux_pga_r);
1800
1801 /* UL turn off */
1802 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1803 0x0001, 0x0000);
1804
1805 /* disable aud_pad TX fifos */
1806 mt6358_mtkaif_tx_disable(priv);
1807
1808 /* L ADC input sel : off, disable L ADC */
1809 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1810 0xf000, 0x0000);
1811 /* L preamplifier DCCEN */
1812 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1813 0x1 << 1, 0x0);
1814 /* L preamplifier input sel : off, L PGA 0 dB gain */
1815 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1816 0xfffb, 0x0000);
1817
1818 /* disable L preamplifier DCC precharge */
1819 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1820 0x1 << 2, 0x0);
1821
1822 /* R ADC input sel : off, disable R ADC */
1823 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1824 0xf000, 0x0000);
1825 /* R preamplifier DCCEN */
1826 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1827 0x1 << 1, 0x0);
1828 /* R preamplifier input sel : off, R PGA 0 dB gain */
1829 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1830 0x0ffb, 0x0000);
1831
1832 /* disable R preamplifier DCC precharge */
1833 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1834 0x1 << 2, 0x0);
1835
1836 /* mic bias */
1837 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1838 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1839
1840 /* Disable MICBIAS1 */
1841 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1842 0x0001, 0x0000);
1843
1844 if (IS_DCC_BASE(mic_type)) {
1845 /* dcclk_gen_on=1'b0 */
1846 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1847 /* dcclk_pdn=1'b1 */
1848 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1849 /* dcclk_ref_ck_sel=2'b00 */
1850 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1851 /* dcclk_div=11'b00100000011 */
1852 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1853 }
1854 }
1855
1856 static int mt6358_dmic_enable(struct mt6358_priv *priv)
1857 {
1858 dev_info(priv->dev, "%s()\n", __func__);
1859
1860 /* mic bias */
1861 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1862 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1863
1864 /* RG_BANDGAPGEN=1'b0 */
1865 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1866 0x1 << 12, 0x0);
1867
1868 /* DMIC enable */
1869 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1870
1871 /* here to set digital part */
1872 mt6358_mtkaif_tx_enable(priv);
1873
1874 /* UL dmic setting */
1875 if (priv->dmic_one_wire_mode)
1876 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400);
1877 else
1878 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1879
1880 /* UL turn on */
1881 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1882
1883 /* Prevent pop noise form dmic hw */
1884 msleep(100);
1885
1886 return 0;
1887 }
1888
1889 static void mt6358_dmic_disable(struct mt6358_priv *priv)
1890 {
1891 dev_info(priv->dev, "%s()\n", __func__);
1892
1893 /* UL turn off */
1894 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1895 0x0003, 0x0000);
1896
1897 /* disable aud_pad TX fifos */
1898 mt6358_mtkaif_tx_disable(priv);
1899
1900 /* DMIC disable */
1901 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1902
1903 /* mic bias */
1904 /* MISBIAS0 = 1P7V */
1905 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1906
1907 /* RG_BANDGAPGEN=1'b0 */
1908 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1909 0x1 << 12, 0x0);
1910
1911 /* MICBIA0 disable */
1912 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1913 }
1914
1915 static void mt6358_restore_pga(struct mt6358_priv *priv)
1916 {
1917 unsigned int gain_l, gain_r;
1918
1919 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1920 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1921
1922 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1923 RG_AUDPREAMPLGAIN_MASK_SFT,
1924 gain_l << RG_AUDPREAMPLGAIN_SFT);
1925 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1926 RG_AUDPREAMPRGAIN_MASK_SFT,
1927 gain_r << RG_AUDPREAMPRGAIN_SFT);
1928 }
1929
1930 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1931 struct snd_kcontrol *kcontrol,
1932 int event)
1933 {
1934 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1935 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1936 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1937
1938 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1939 __func__, event, mux);
1940
1941 switch (event) {
1942 case SND_SOC_DAPM_WILL_PMU:
1943 priv->mux_select[MUX_MIC_TYPE] = mux;
1944 break;
1945 case SND_SOC_DAPM_PRE_PMU:
1946 switch (mux) {
1947 case MIC_TYPE_MUX_DMIC:
1948 mt6358_dmic_enable(priv);
1949 break;
1950 default:
1951 mt6358_amic_enable(priv);
1952 break;
1953 }
1954 mt6358_restore_pga(priv);
1955
1956 break;
1957 case SND_SOC_DAPM_POST_PMD:
1958 switch (priv->mux_select[MUX_MIC_TYPE]) {
1959 case MIC_TYPE_MUX_DMIC:
1960 mt6358_dmic_disable(priv);
1961 break;
1962 default:
1963 mt6358_amic_disable(priv);
1964 break;
1965 }
1966
1967 priv->mux_select[MUX_MIC_TYPE] = mux;
1968 break;
1969 default:
1970 break;
1971 }
1972
1973 return 0;
1974 }
1975
1976 static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1977 struct snd_kcontrol *kcontrol,
1978 int event)
1979 {
1980 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1981 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1982 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1983
1984 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1985 __func__, event, mux);
1986
1987 priv->mux_select[MUX_ADC_L] = mux;
1988
1989 return 0;
1990 }
1991
1992 static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1993 struct snd_kcontrol *kcontrol,
1994 int event)
1995 {
1996 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1997 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1998 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1999
2000 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2001 __func__, event, mux);
2002
2003 priv->mux_select[MUX_ADC_R] = mux;
2004
2005 return 0;
2006 }
2007
2008 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
2009 struct snd_kcontrol *kcontrol,
2010 int event)
2011 {
2012 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2013 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2014 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2015
2016 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2017 __func__, event, mux);
2018
2019 priv->mux_select[MUX_PGA_L] = mux;
2020
2021 return 0;
2022 }
2023
2024 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
2025 struct snd_kcontrol *kcontrol,
2026 int event)
2027 {
2028 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2029 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2030 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
2031
2032 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
2033 __func__, event, mux);
2034
2035 priv->mux_select[MUX_PGA_R] = mux;
2036
2037 return 0;
2038 }
2039
2040 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
2041 struct snd_kcontrol *kcontrol,
2042 int event)
2043 {
2044 switch (event) {
2045 case SND_SOC_DAPM_POST_PMU:
2046 usleep_range(250, 270);
2047 break;
2048 case SND_SOC_DAPM_PRE_PMD:
2049 usleep_range(250, 270);
2050 break;
2051 default:
2052 break;
2053 }
2054
2055 return 0;
2056 }
2057
2058 /* DAPM Widgets */
2059 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
2060 /* Global Supply*/
2061 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
2062 MT6358_DCXO_CW14,
2063 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2064 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
2065 MT6358_AUDDEC_ANA_CON13,
2066 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2067 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
2068 MT6358_AUDENC_ANA_CON6,
2069 RG_CLKSQ_EN_SFT, 0,
2070 mt_clksq_event,
2071 SND_SOC_DAPM_PRE_PMU),
2072 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
2073 MT6358_AUD_TOP_CKPDN_CON0,
2074 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2075 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
2076 MT6358_AUD_TOP_CKPDN_CON0,
2077 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2078 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
2079 MT6358_AUD_TOP_CKPDN_CON0,
2080 RG_AUD_CK_PDN_SFT, 1,
2081 mt_delay_250_event,
2082 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2083 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
2084 MT6358_AUD_TOP_CKPDN_CON0,
2085 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2086
2087 /* Digital Clock */
2088 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
2089 MT6358_AUDIO_TOP_CON0,
2090 PDN_AFE_CTL_SFT, 1,
2091 mt_delay_250_event,
2092 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2093 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
2094 MT6358_AUDIO_TOP_CON0,
2095 PDN_DAC_CTL_SFT, 1, NULL, 0),
2096 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
2097 MT6358_AUDIO_TOP_CON0,
2098 PDN_ADC_CTL_SFT, 1, NULL, 0),
2099 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
2100 MT6358_AUDIO_TOP_CON0,
2101 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2102 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
2103 MT6358_AUDIO_TOP_CON0,
2104 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2105 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
2106 MT6358_AUDIO_TOP_CON0,
2107 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2108 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
2109 MT6358_AUDIO_TOP_CON0,
2110 PDN_RESERVED_SFT, 1, NULL, 0),
2111
2112 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
2113 0, 0, NULL, 0),
2114
2115 /* AFE ON */
2116 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
2117 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2118 NULL, 0),
2119
2120 /* AIF Rx*/
2121 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2122 MT6358_AFE_DL_SRC2_CON0_L,
2123 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2124 mt_aif_in_event,
2125 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2126
2127 /* DL Supply */
2128 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
2129 0, 0, NULL, 0),
2130
2131 /* DAC */
2132 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2133
2134 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2135
2136 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2137
2138 /* LOL */
2139 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2140
2141 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
2142 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2143
2144 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
2145 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2146
2147 /* Headphone */
2148 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2149 &hpl_in_mux_control,
2150 mt_hp_event,
2151 SND_SOC_DAPM_PRE_PMU |
2152 SND_SOC_DAPM_PRE_PMD),
2153
2154 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2155 &hpr_in_mux_control,
2156 mt_hp_event,
2157 SND_SOC_DAPM_PRE_PMU |
2158 SND_SOC_DAPM_PRE_PMD),
2159
2160 /* Receiver */
2161 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2162 &rcv_in_mux_control,
2163 mt_rcv_event,
2164 SND_SOC_DAPM_PRE_PMU |
2165 SND_SOC_DAPM_PRE_PMD),
2166
2167 /* Outputs */
2168 SND_SOC_DAPM_OUTPUT("Receiver"),
2169 SND_SOC_DAPM_OUTPUT("Headphone L"),
2170 SND_SOC_DAPM_OUTPUT("Headphone R"),
2171 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2172 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2173 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2174 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2175
2176 /* SGEN */
2177 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2178 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2179 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2180 SGEN_MUTE_SW_CTL_SFT, 1,
2181 mt_sgen_event,
2182 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2183 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2184 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2185
2186 SND_SOC_DAPM_INPUT("SGEN DL"),
2187
2188 /* Uplinks */
2189 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2190 SND_SOC_NOPM, 0, 0,
2191 mt_aif_out_event,
2192 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2193
2194 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2195 SND_SOC_NOPM, 0, 0,
2196 mt_adc_supply_event,
2197 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2198
2199 /* Uplinks MUX */
2200 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2201 &aif_out_mux_control),
2202
2203 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2204 &mic_type_mux_control,
2205 mt_mic_type_event,
2206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2207 SND_SOC_DAPM_WILL_PMU),
2208
2209 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2210 &adc_left_mux_control,
2211 mt_adc_l_event,
2212 SND_SOC_DAPM_WILL_PMU),
2213 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2214 &adc_right_mux_control,
2215 mt_adc_r_event,
2216 SND_SOC_DAPM_WILL_PMU),
2217
2218 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2219 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2220
2221 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2222 &pga_left_mux_control,
2223 mt_pga_left_event,
2224 SND_SOC_DAPM_WILL_PMU),
2225 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2226 &pga_right_mux_control,
2227 mt_pga_right_event,
2228 SND_SOC_DAPM_WILL_PMU),
2229
2230 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2231 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2232
2233 /* UL input */
2234 SND_SOC_DAPM_INPUT("AIN0"),
2235 SND_SOC_DAPM_INPUT("AIN1"),
2236 SND_SOC_DAPM_INPUT("AIN2"),
2237 };
2238
2239 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2240 /* Capture */
2241 {"AIF1TX", NULL, "AIF Out Mux"},
2242 {"AIF1TX", NULL, "CLK_BUF"},
2243 {"AIF1TX", NULL, "AUDGLB"},
2244 {"AIF1TX", NULL, "CLKSQ Audio"},
2245
2246 {"AIF1TX", NULL, "AUD_CK"},
2247 {"AIF1TX", NULL, "AUDIF_CK"},
2248
2249 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2250 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2251 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2252 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2253 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2254
2255 {"AIF1TX", NULL, "AFE_ON"},
2256
2257 {"AIF Out Mux", NULL, "Mic Type Mux"},
2258
2259 {"Mic Type Mux", "ACC", "ADC L"},
2260 {"Mic Type Mux", "ACC", "ADC R"},
2261 {"Mic Type Mux", "DCC", "ADC L"},
2262 {"Mic Type Mux", "DCC", "ADC R"},
2263 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2264 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2265 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2266 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2267 {"Mic Type Mux", "DMIC", "AIN0"},
2268 {"Mic Type Mux", "DMIC", "AIN2"},
2269
2270 {"ADC L", NULL, "ADC L Mux"},
2271 {"ADC L", NULL, "ADC Supply"},
2272 {"ADC R", NULL, "ADC R Mux"},
2273 {"ADC R", NULL, "ADC Supply"},
2274
2275 {"ADC L Mux", "Left Preamplifier", "PGA L"},
2276
2277 {"ADC R Mux", "Right Preamplifier", "PGA R"},
2278
2279 {"PGA L", NULL, "PGA L Mux"},
2280 {"PGA R", NULL, "PGA R Mux"},
2281
2282 {"PGA L Mux", "AIN0", "AIN0"},
2283 {"PGA L Mux", "AIN1", "AIN1"},
2284 {"PGA L Mux", "AIN2", "AIN2"},
2285
2286 {"PGA R Mux", "AIN0", "AIN0"},
2287 {"PGA R Mux", "AIN1", "AIN1"},
2288 {"PGA R Mux", "AIN2", "AIN2"},
2289
2290 /* DL Supply */
2291 {"DL Power Supply", NULL, "CLK_BUF"},
2292 {"DL Power Supply", NULL, "AUDGLB"},
2293 {"DL Power Supply", NULL, "CLKSQ Audio"},
2294
2295 {"DL Power Supply", NULL, "AUDNCP_CK"},
2296 {"DL Power Supply", NULL, "ZCD13M_CK"},
2297 {"DL Power Supply", NULL, "AUD_CK"},
2298 {"DL Power Supply", NULL, "AUDIF_CK"},
2299
2300 /* DL Digital Supply */
2301 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2302 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2303 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2304
2305 {"DL Digital Clock", NULL, "AFE_ON"},
2306
2307 {"AIF_RX", NULL, "DL Digital Clock"},
2308
2309 /* DL Path */
2310 {"DAC In Mux", "Normal Path", "AIF_RX"},
2311
2312 {"DAC In Mux", "Sgen", "SGEN DL"},
2313 {"SGEN DL", NULL, "SGEN DL SRC"},
2314 {"SGEN DL", NULL, "SGEN MUTE"},
2315 {"SGEN DL", NULL, "SGEN DL Enable"},
2316 {"SGEN DL", NULL, "DL Digital Clock"},
2317 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2318
2319 {"DACL", NULL, "DAC In Mux"},
2320 {"DACL", NULL, "DL Power Supply"},
2321
2322 {"DACR", NULL, "DAC In Mux"},
2323 {"DACR", NULL, "DL Power Supply"},
2324
2325 /* Lineout Path */
2326 {"LOL Mux", "Playback", "DACL"},
2327
2328 {"LOL Buffer", NULL, "LOL Mux"},
2329 {"LOL Buffer", NULL, "LO Stability Enh"},
2330
2331 {"LINEOUT L", NULL, "LOL Buffer"},
2332
2333 /* Headphone Path */
2334 {"HPL Mux", "Audio Playback", "DACL"},
2335 {"HPR Mux", "Audio Playback", "DACR"},
2336 {"HPL Mux", "HP Impedance", "DACL"},
2337 {"HPR Mux", "HP Impedance", "DACR"},
2338 {"HPL Mux", "LoudSPK Playback", "DACL"},
2339 {"HPR Mux", "LoudSPK Playback", "DACR"},
2340
2341 {"Headphone L", NULL, "HPL Mux"},
2342 {"Headphone R", NULL, "HPR Mux"},
2343 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2344 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2345 {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2346
2347 /* Receiver Path */
2348 {"RCV Mux", "Voice Playback", "DACL"},
2349 {"Receiver", NULL, "RCV Mux"},
2350 };
2351
2352 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2353 struct snd_pcm_hw_params *params,
2354 struct snd_soc_dai *dai)
2355 {
2356 struct snd_soc_component *cmpnt = dai->component;
2357 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2358 unsigned int rate = params_rate(params);
2359
2360 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2361 __func__,
2362 substream->stream,
2363 rate,
2364 substream->number);
2365
2366 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2367 priv->dl_rate = rate;
2368 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2369 priv->ul_rate = rate;
2370
2371 return 0;
2372 }
2373
2374 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2375 .hw_params = mt6358_codec_dai_hw_params,
2376 };
2377
2378 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
2379 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
2380 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
2381
2382 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2383 {
2384 .name = "mt6358-snd-codec-aif1",
2385 .playback = {
2386 .stream_name = "AIF1 Playback",
2387 .channels_min = 1,
2388 .channels_max = 2,
2389 .rates = SNDRV_PCM_RATE_8000_48000 |
2390 SNDRV_PCM_RATE_96000 |
2391 SNDRV_PCM_RATE_192000,
2392 .formats = MT6358_FORMATS,
2393 },
2394 .capture = {
2395 .stream_name = "AIF1 Capture",
2396 .channels_min = 1,
2397 .channels_max = 2,
2398 .rates = SNDRV_PCM_RATE_8000 |
2399 SNDRV_PCM_RATE_16000 |
2400 SNDRV_PCM_RATE_32000 |
2401 SNDRV_PCM_RATE_48000,
2402 .formats = MT6358_FORMATS,
2403 },
2404 .ops = &mt6358_codec_dai_ops,
2405 },
2406 };
2407
2408 static void mt6358_codec_init_reg(struct mt6358_priv *priv)
2409 {
2410 /* Disable HeadphoneL/HeadphoneR short circuit protection */
2411 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2412 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2413 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2414 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2415 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2416 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2417 /* Disable voice short circuit protection */
2418 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2419 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2420 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2421 /* disable LO buffer left short circuit protection */
2422 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2423 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2424 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2425
2426 /* accdet s/w enable */
2427 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2428 0xFFFF, 0x700E);
2429
2430 /* gpio miso driving set to 4mA */
2431 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2432
2433 /* set gpio */
2434 playback_gpio_reset(priv);
2435 capture_gpio_reset(priv);
2436 }
2437
2438 static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2439 {
2440 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2441 int ret;
2442
2443 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2444
2445 mt6358_codec_init_reg(priv);
2446
2447 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2448 if (IS_ERR(priv->avdd_reg)) {
2449 dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2450 return PTR_ERR(priv->avdd_reg);
2451 }
2452
2453 ret = regulator_enable(priv->avdd_reg);
2454 if (ret)
2455 return ret;
2456
2457 return 0;
2458 }
2459
2460 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2461 .probe = mt6358_codec_probe,
2462 .controls = mt6358_snd_controls,
2463 .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2464 .dapm_widgets = mt6358_dapm_widgets,
2465 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2466 .dapm_routes = mt6358_dapm_routes,
2467 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2468 .endianness = 1,
2469 };
2470
2471 static void mt6358_parse_dt(struct mt6358_priv *priv)
2472 {
2473 int ret;
2474 struct device *dev = priv->dev;
2475
2476 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode",
2477 &priv->dmic_one_wire_mode);
2478 if (ret) {
2479 dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
2480 __func__);
2481 priv->dmic_one_wire_mode = 0;
2482 }
2483 }
2484
2485 static int mt6358_platform_driver_probe(struct platform_device *pdev)
2486 {
2487 struct mt6358_priv *priv;
2488 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2489
2490 priv = devm_kzalloc(&pdev->dev,
2491 sizeof(struct mt6358_priv),
2492 GFP_KERNEL);
2493 if (!priv)
2494 return -ENOMEM;
2495
2496 dev_set_drvdata(&pdev->dev, priv);
2497
2498 priv->dev = &pdev->dev;
2499
2500 priv->regmap = mt6397->regmap;
2501 if (IS_ERR(priv->regmap))
2502 return PTR_ERR(priv->regmap);
2503
2504 mt6358_parse_dt(priv);
2505
2506 dev_info(priv->dev, "%s(), dev name %s\n",
2507 __func__, dev_name(&pdev->dev));
2508
2509 return devm_snd_soc_register_component(&pdev->dev,
2510 &mt6358_soc_component_driver,
2511 mt6358_dai_driver,
2512 ARRAY_SIZE(mt6358_dai_driver));
2513 }
2514
2515 static const struct of_device_id mt6358_of_match[] = {
2516 {.compatible = "mediatek,mt6358-sound",},
2517 {.compatible = "mediatek,mt6366-sound",},
2518 {}
2519 };
2520 MODULE_DEVICE_TABLE(of, mt6358_of_match);
2521
2522 static struct platform_driver mt6358_platform_driver = {
2523 .driver = {
2524 .name = "mt6358-sound",
2525 .of_match_table = mt6358_of_match,
2526 },
2527 .probe = mt6358_platform_driver_probe,
2528 };
2529
2530 module_platform_driver(mt6358_platform_driver)
2531
2532 /* Module information */
2533 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2534 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2535 MODULE_LICENSE("GPL v2");
2536
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