1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver
4 //
5 // Copyright 2021 Nuvoton Technology Corp.
6 // Author: John Hsu <kchsu0@nuvoton.com>
7 // Co-author: Seven Lee <wtli@nuvoton.com>
8 //
9
10 #include <linux/acpi.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/math64.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/jack.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
27 #include "nau8821.h"
28
29 #define NAU8821_JD_ACTIVE_HIGH BIT(0)
30
31 static int nau8821_quirk;
32 static int quirk_override = -1;
33 module_param_named(quirk, quirk_override, uint, 0444);
34 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
35
36 #define NAU_FREF_MAX 13500000
37 #define NAU_FVCO_MAX 100000000
38 #define NAU_FVCO_MIN 90000000
39
40 #define NAU8821_BUTTON SND_JACK_BTN_0
41
42 /* the maximum frequency of CLK_ADC and CLK_DAC */
43 #define CLK_DA_AD_MAX 6144000
44
45 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
46 int clk_id, unsigned int freq);
47 static bool nau8821_is_jack_inserted(struct regmap *regmap);
48
49 struct nau8821_fll {
50 int mclk_src;
51 int ratio;
52 int fll_frac;
53 int fll_int;
54 int clk_ref_div;
55 };
56
57 struct nau8821_fll_attr {
58 unsigned int param;
59 unsigned int val;
60 };
61
62 /* scaling for mclk from sysclk_src output */
63 static const struct nau8821_fll_attr mclk_src_scaling[] = {
64 { 1, 0x0 },
65 { 2, 0x2 },
66 { 4, 0x3 },
67 { 8, 0x4 },
68 { 16, 0x5 },
69 { 32, 0x6 },
70 { 3, 0x7 },
71 { 6, 0xa },
72 { 12, 0xb },
73 { 24, 0xc },
74 { 48, 0xd },
75 { 96, 0xe },
76 { 5, 0xf },
77 };
78
79 /* ratio for input clk freq */
80 static const struct nau8821_fll_attr fll_ratio[] = {
81 { 512000, 0x01 },
82 { 256000, 0x02 },
83 { 128000, 0x04 },
84 { 64000, 0x08 },
85 { 32000, 0x10 },
86 { 8000, 0x20 },
87 { 4000, 0x40 },
88 };
89
90 static const struct nau8821_fll_attr fll_pre_scalar[] = {
91 { 0, 0x0 },
92 { 1, 0x1 },
93 { 2, 0x2 },
94 { 3, 0x3 },
95 };
96
97 /* over sampling rate */
98 struct nau8821_osr_attr {
99 unsigned int osr;
100 unsigned int clk_src;
101 };
102
103 static const struct nau8821_osr_attr osr_dac_sel[] = {
104 { 64, 2 }, /* OSR 64, SRC 1/4 */
105 { 256, 0 }, /* OSR 256, SRC 1 */
106 { 128, 1 }, /* OSR 128, SRC 1/2 */
107 { 0, 0 },
108 { 32, 3 }, /* OSR 32, SRC 1/8 */
109 };
110
111 static const struct nau8821_osr_attr osr_adc_sel[] = {
112 { 32, 3 }, /* OSR 32, SRC 1/8 */
113 { 64, 2 }, /* OSR 64, SRC 1/4 */
114 { 128, 1 }, /* OSR 128, SRC 1/2 */
115 { 256, 0 }, /* OSR 256, SRC 1 */
116 };
117
118 struct nau8821_dmic_speed {
119 unsigned int param;
120 unsigned int val;
121 };
122
123 static const struct nau8821_dmic_speed dmic_speed_sel[] = {
124 { 0, 0x0 }, /*SPEED 1, SRC 1 */
125 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */
126 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */
127 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */
128 };
129
130 static const struct reg_default nau8821_reg_defaults[] = {
131 { NAU8821_R01_ENA_CTRL, 0x00ff },
132 { NAU8821_R03_CLK_DIVIDER, 0x0050 },
133 { NAU8821_R04_FLL1, 0x0 },
134 { NAU8821_R05_FLL2, 0x00bc },
135 { NAU8821_R06_FLL3, 0x0008 },
136 { NAU8821_R07_FLL4, 0x0010 },
137 { NAU8821_R08_FLL5, 0x4000 },
138 { NAU8821_R09_FLL6, 0x6900 },
139 { NAU8821_R0A_FLL7, 0x0031 },
140 { NAU8821_R0B_FLL8, 0x26e9 },
141 { NAU8821_R0D_JACK_DET_CTRL, 0x0 },
142 { NAU8821_R0F_INTERRUPT_MASK, 0x0 },
143 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
144 { NAU8821_R13_DMIC_CTRL, 0x0 },
145 { NAU8821_R1A_GPIO12_CTRL, 0x0 },
146 { NAU8821_R1B_TDM_CTRL, 0x0 },
147 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
148 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
149 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
150 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
151 { NAU8821_R21_BIQ0_COF1, 0x0 },
152 { NAU8821_R22_BIQ0_COF2, 0x0 },
153 { NAU8821_R23_BIQ0_COF3, 0x0 },
154 { NAU8821_R24_BIQ0_COF4, 0x0 },
155 { NAU8821_R25_BIQ0_COF5, 0x0 },
156 { NAU8821_R26_BIQ0_COF6, 0x0 },
157 { NAU8821_R27_BIQ0_COF7, 0x0 },
158 { NAU8821_R28_BIQ0_COF8, 0x0 },
159 { NAU8821_R29_BIQ0_COF9, 0x0 },
160 { NAU8821_R2A_BIQ0_COF10, 0x0 },
161 { NAU8821_R2B_ADC_RATE, 0x0002 },
162 { NAU8821_R2C_DAC_CTRL1, 0x0082 },
163 { NAU8821_R2D_DAC_CTRL2, 0x0 },
164 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
165 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
166 { NAU8821_R31_MUTE_CTRL, 0x0 },
167 { NAU8821_R32_HSVOL_CTRL, 0x0 },
168 { NAU8821_R34_DACR_CTRL, 0xcfcf },
169 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
170 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
171 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
172 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
173 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
174 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
175 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
176 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
177 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
178 { NAU8821_R41_BIQ1_COF1, 0x0 },
179 { NAU8821_R42_BIQ1_COF2, 0x0 },
180 { NAU8821_R43_BIQ1_COF3, 0x0 },
181 { NAU8821_R44_BIQ1_COF4, 0x0 },
182 { NAU8821_R45_BIQ1_COF5, 0x0 },
183 { NAU8821_R46_BIQ1_COF6, 0x0 },
184 { NAU8821_R47_BIQ1_COF7, 0x0 },
185 { NAU8821_R48_BIQ1_COF8, 0x0 },
186 { NAU8821_R49_BIQ1_COF9, 0x0 },
187 { NAU8821_R4A_BIQ1_COF10, 0x0 },
188 { NAU8821_R4B_CLASSG_CTRL, 0x0 },
189 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
190 { NAU8821_R4D_IMM_RMS_L, 0x0 },
191 { NAU8821_R53_OTPDOUT_1, 0xaad8 },
192 { NAU8821_R54_OTPDOUT_2, 0x0002 },
193 { NAU8821_R55_MISC_CTRL, 0x0 },
194 { NAU8821_R66_BIAS_ADJ, 0x0 },
195 { NAU8821_R68_TRIM_SETTINGS, 0x0 },
196 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
197 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
198 { NAU8821_R6B_PGA_MUTE, 0x0 },
199 { NAU8821_R71_ANALOG_ADC_1, 0x0011 },
200 { NAU8821_R72_ANALOG_ADC_2, 0x0020 },
201 { NAU8821_R73_RDAC, 0x0008 },
202 { NAU8821_R74_MIC_BIAS, 0x0006 },
203 { NAU8821_R76_BOOST, 0x0 },
204 { NAU8821_R77_FEPGA, 0x0 },
205 { NAU8821_R7E_PGA_GAIN, 0x0 },
206 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
207 { NAU8821_R80_CHARGE_PUMP, 0x0 },
208 };
209
210 static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
211 {
212 switch (reg) {
213 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
214 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
215 case NAU8821_R0D_JACK_DET_CTRL:
216 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
217 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
218 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
219 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
220 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
221 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
222 case NAU8821_R51_FUSE_CTRL1:
223 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
224 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
225 case NAU8821_R66_BIAS_ADJ:
226 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
227 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
228 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
229 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
230 return true;
231 default:
232 return false;
233 }
234 }
235
236 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
237 {
238 switch (reg) {
239 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
240 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
241 case NAU8821_R0D_JACK_DET_CTRL:
242 case NAU8821_R0F_INTERRUPT_MASK:
243 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
244 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
245 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
246 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
247 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
248 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
249 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
250 case NAU8821_R51_FUSE_CTRL1:
251 case NAU8821_R55_MISC_CTRL:
252 case NAU8821_R5A_SOFTWARE_RST:
253 case NAU8821_R66_BIAS_ADJ:
254 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
255 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
256 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
257 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
258 return true;
259 default:
260 return false;
261 }
262 }
263
264 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
265 {
266 switch (reg) {
267 case NAU8821_R00_RESET:
268 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
269 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
270 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
271 case NAU8821_R4D_IMM_RMS_L:
272 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
273 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
274 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
275 return true;
276 default:
277 return false;
278 }
279 }
280
281 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
282 struct snd_ctl_elem_value *ucontrol)
283 {
284 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
285 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
286
287 if (!component->regmap)
288 return -EINVAL;
289
290 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
291 ucontrol->value.bytes.data, params->max);
292
293 return 0;
294 }
295
296 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298 {
299 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
300 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
301 void *data;
302
303 if (!component->regmap)
304 return -EINVAL;
305
306 data = kmemdup(ucontrol->value.bytes.data,
307 params->max, GFP_KERNEL | GFP_DMA);
308 if (!data)
309 return -ENOMEM;
310
311 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
312 data, params->max);
313
314 kfree(data);
315
316 return 0;
317 }
318
319 static const char * const nau8821_adc_decimation[] = {
320 "32", "64", "128", "256" };
321
322 static const struct soc_enum nau8821_adc_decimation_enum =
323 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
324 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
325
326 static const char * const nau8821_dac_oversampl[] = {
327 "64", "256", "128", "", "32" };
328
329 static const struct soc_enum nau8821_dac_oversampl_enum =
330 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
331 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
332
333 static const char * const nau8821_adc_drc_noise_gate[] = {
334 "1:1", "2:1", "4:1", "8:1" };
335
336 static const struct soc_enum nau8821_adc_drc_noise_gate_enum =
337 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT,
338 ARRAY_SIZE(nau8821_adc_drc_noise_gate),
339 nau8821_adc_drc_noise_gate);
340
341 static const char * const nau8821_adc_drc_expansion_slope[] = {
342 "1:1", "2:1", "4:1" };
343
344 static const struct soc_enum nau8821_adc_drc_expansion_slope_enum =
345 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT,
346 ARRAY_SIZE(nau8821_adc_drc_expansion_slope),
347 nau8821_adc_drc_expansion_slope);
348
349 static const char * const nau8821_adc_drc_lower_region[] = {
350 "", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" };
351
352 static const struct soc_enum nau8821_adc_drc_lower_region_enum =
353 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
354 NAU8821_DRC_CMP2_SLP_ADC_SFT,
355 ARRAY_SIZE(nau8821_adc_drc_lower_region),
356 nau8821_adc_drc_lower_region);
357
358 static const char * const nau8821_higher_region[] = {
359 "", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" };
360
361 static const struct soc_enum nau8821_higher_region_enum =
362 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
363 NAU8821_DRC_CMP1_SLP_ADC_SFT,
364 ARRAY_SIZE(nau8821_higher_region),
365 nau8821_higher_region);
366
367 static const char * const nau8821_limiter_slope[] = {
368 "", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" };
369
370 static const struct soc_enum nau8821_limiter_slope_enum =
371 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
372 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope),
373 nau8821_limiter_slope);
374
375 static const char * const nau8821_detection_attack_time[] = {
376 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts",
377 "", "511Ts" };
378
379 static const struct soc_enum nau8821_detection_attack_time_enum =
380 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY,
381 NAU8821_DRC_PK_COEF1_ADC_SFT,
382 ARRAY_SIZE(nau8821_detection_attack_time),
383 nau8821_detection_attack_time);
384
385 static const char * const nau8821_detection_release_time[] = {
386 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts",
387 "8191Ts", "", "16383Ts" };
388
389 static const struct soc_enum nau8821_detection_release_time_enum =
390 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY,
391 NAU8821_DRC_PK_COEF2_ADC_SFT,
392 ARRAY_SIZE(nau8821_detection_release_time),
393 nau8821_detection_release_time);
394
395 static const char * const nau8821_attack_time[] = {
396 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts",
397 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" };
398
399 static const struct soc_enum nau8821_attack_time_enum =
400 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT,
401 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time);
402
403 static const char * const nau8821_decay_time[] = {
404 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts",
405 "8191Ts", "16383Ts", "32757Ts", "65535Ts" };
406
407 static const struct soc_enum nau8821_decay_time_enum =
408 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT,
409 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time);
410
411 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
412 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
413 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
414 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
415 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
416 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
417 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500);
418 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800);
419
420 static const struct snd_kcontrol_new nau8821_controls[] = {
421 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
422 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
423 0xff, 0, adc_vol_tlv),
424 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
425 12, 8, 0x0f, 0, sidetone_vol_tlv),
426 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
427 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
428 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
429 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
430 0xcf, 0, playback_vol_tlv),
431 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
432 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
433 37, 0, fepga_gain_tlv),
434 SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
435 NAU8821_R2F_DAC_DGAIN_CTRL,
436 0, 8, 0xff, 0, crosstalk_vol_tlv),
437 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34,
438 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv),
439 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34,
440 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv),
441
442 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum),
443 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum),
444 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum),
445 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum),
446 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum),
447 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum),
448 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum),
449 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum),
450 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum),
451 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12,
452 NAU8821_DRC_ENA_ADC_SFT, 1, 0),
453
454 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
455 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
456 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
457 nau8821_biq_coeff_get, nau8821_biq_coeff_put),
458 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
459 NAU8821_ADCPHS_SFT, 1, 0),
460 };
461
462 static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
463 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
464 NAU8821_DMIC_EN_SFT, 1, 0);
465
466 static int dmic_clock_control(struct snd_soc_dapm_widget *w,
467 struct snd_kcontrol *k, int event)
468 {
469 struct snd_soc_component *component =
470 snd_soc_dapm_to_component(w->dapm);
471 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
472 int i, speed_selection = -1, clk_adc_src, clk_adc;
473 unsigned int clk_divider_r03;
474
475 /* The DMIC clock is gotten from adc clock divided by
476 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or
477 * less than nau8821->dmic_clk_threshold.
478 */
479 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
480 &clk_divider_r03);
481 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
482 >> NAU8821_CLK_ADC_SRC_SFT;
483 clk_adc = (nau8821->fs * 256) >> clk_adc_src;
484
485 for (i = 0 ; i < 4 ; i++)
486 if ((clk_adc >> dmic_speed_sel[i].param) <=
487 nau8821->dmic_clk_threshold) {
488 speed_selection = dmic_speed_sel[i].val;
489 break;
490 }
491 if (i == 4)
492 return -EINVAL;
493
494 dev_dbg(nau8821->dev,
495 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
496 clk_adc, nau8821->dmic_clk_threshold,
497 dmic_speed_sel[i].param, dmic_speed_sel[i].val);
498 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
499 NAU8821_DMIC_SRC_MASK,
500 (speed_selection << NAU8821_DMIC_SRC_SFT));
501
502 return 0;
503 }
504
505 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
506 struct snd_kcontrol *kcontrol, int event)
507 {
508 struct snd_soc_component *component =
509 snd_soc_dapm_to_component(w->dapm);
510 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
511
512 switch (event) {
513 case SND_SOC_DAPM_POST_PMU:
514 msleep(nau8821->adc_delay);
515 break;
516 case SND_SOC_DAPM_POST_PMD:
517 break;
518 default:
519 return -EINVAL;
520 }
521
522 return 0;
523 }
524
525 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
526 struct snd_kcontrol *kcontrol, int event)
527 {
528 struct snd_soc_component *component =
529 snd_soc_dapm_to_component(w->dapm);
530 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
531
532 switch (event) {
533 case SND_SOC_DAPM_POST_PMU:
534 msleep(nau8821->adc_delay);
535 break;
536 case SND_SOC_DAPM_POST_PMD:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 return 0;
543 }
544
545 static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
546 struct snd_kcontrol *kcontrol, int event)
547 {
548 struct snd_soc_component *component =
549 snd_soc_dapm_to_component(w->dapm);
550 struct nau8821 *nau8821 =
551 snd_soc_component_get_drvdata(component);
552
553 switch (event) {
554 case SND_SOC_DAPM_POST_PMU:
555 /* Prevent startup click by letting charge pump to ramp up */
556 msleep(20);
557 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
558 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
559 break;
560 case SND_SOC_DAPM_PRE_PMD:
561 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
562 NAU8821_JAMNODCLOW, 0);
563 break;
564 default:
565 return -EINVAL;
566 }
567
568 return 0;
569 }
570
571 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
572 struct snd_kcontrol *kcontrol, int event)
573 {
574 struct snd_soc_component *component =
575 snd_soc_dapm_to_component(w->dapm);
576 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
577
578 switch (event) {
579 case SND_SOC_DAPM_PRE_PMU:
580 /* Disables the TESTDAC to let DAC signal pass through. */
581 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
582 NAU8821_BIAS_TESTDAC_EN, 0);
583 break;
584 case SND_SOC_DAPM_POST_PMD:
585 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
586 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
587 break;
588 default:
589 return -EINVAL;
590 }
591
592 return 0;
593 }
594
595 static int system_clock_control(struct snd_soc_dapm_widget *w,
596 struct snd_kcontrol *k, int event)
597 {
598 struct snd_soc_component *component =
599 snd_soc_dapm_to_component(w->dapm);
600 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
601
602 if (SND_SOC_DAPM_EVENT_OFF(event)) {
603 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
604 /* Set clock source to disable or internal clock before the
605 * playback or capture end. Codec needs clock for Jack
606 * detection and button press if jack inserted; otherwise,
607 * the clock should be closed.
608 */
609 if (nau8821_is_jack_inserted(nau8821->regmap)) {
610 nau8821_configure_sysclk(nau8821,
611 NAU8821_CLK_INTERNAL, 0);
612 } else {
613 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
614 }
615 }
616 return 0;
617 }
618
619 static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w,
620 struct snd_kcontrol *kcontrol, int event)
621 {
622 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
623 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
624
625 if (!nau8821->left_input_single_end)
626 return 0;
627
628 switch (event) {
629 case SND_SOC_DAPM_POST_PMU:
630 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA,
631 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK,
632 NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF);
633 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST,
634 NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN);
635 break;
636 case SND_SOC_DAPM_POST_PMD:
637 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA,
638 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0);
639 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST,
640 NAU8821_HP_BOOST_DISCHRG_EN, 0);
641 break;
642 default:
643 break;
644 }
645
646 return 0;
647 }
648
649 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
650 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
651 system_clock_control, SND_SOC_DAPM_POST_PMD),
652 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
653 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
654 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
655 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
656 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
657 NAU8821_POWERUP_ADCL_SFT, 0),
658 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
659 NAU8821_POWERUP_ADCR_SFT, 0),
660 /* single-ended design only on the left */
661 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
662 NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event,
663 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
664 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
665 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
666 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
667 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
668 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
669 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
670 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
672 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
673 0, 0, &nau8821_dmic_mode_switch),
674 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
675 NAU8821_I2S_TRISTATE_SFT, 1),
676 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
677
678 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
679 NAU8821_DACL_EN_SFT, 0, NULL, 0),
680 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
681 NAU8821_DACR_EN_SFT, 0, NULL, 0),
682 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
683 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
684 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
685 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
686 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
687 NAU8821_EN_DACR_SFT, 0),
688 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
689 NAU8821_EN_DACL_SFT, 0),
690 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
691 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
692 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
693 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
694 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
695 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
696 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
697 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
698 NAU8821_R7F_POWER_UP_CONTROL,
699 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
700 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
701 NAU8821_R7F_POWER_UP_CONTROL,
702 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
703 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
704 NAU8821_R7F_POWER_UP_CONTROL,
705 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
706 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
707 NAU8821_R7F_POWER_UP_CONTROL,
708 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
709 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
710 NAU8821_R7F_POWER_UP_CONTROL,
711 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
712 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
713 NAU8821_R7F_POWER_UP_CONTROL,
714 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
715 SND_SOC_DAPM_PGA_S("Output DACL", 7,
716 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
717 0, nau8821_output_dac_event,
718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
719 SND_SOC_DAPM_PGA_S("Output DACR", 7,
720 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
721 0, nau8821_output_dac_event,
722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
723
724 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
725 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
726 NAU8821_R0D_JACK_DET_CTRL,
727 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
728 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
729 NAU8821_R0D_JACK_DET_CTRL,
730 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
731
732 /* High current HPOL/R boost driver */
733 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
734 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
735 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
736 NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
737
738 SND_SOC_DAPM_INPUT("MICL"),
739 SND_SOC_DAPM_INPUT("MICR"),
740 SND_SOC_DAPM_INPUT("DMIC"),
741 SND_SOC_DAPM_OUTPUT("HPOL"),
742 SND_SOC_DAPM_OUTPUT("HPOR"),
743 };
744
745 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
746 {"DMIC Enable", "Switch", "DMIC"},
747 {"DMIC Enable", NULL, "DMIC Clock"},
748
749 {"Frontend PGA L", NULL, "MICL"},
750 {"Frontend PGA R", NULL, "MICR"},
751 {"Frontend PGA L", NULL, "MICBIAS"},
752 {"Frontend PGA R", NULL, "MICBIAS"},
753
754 {"ADCL Power", NULL, "Frontend PGA L"},
755 {"ADCR Power", NULL, "Frontend PGA R"},
756
757 {"ADCL Digital path", NULL, "ADCL Power"},
758 {"ADCR Digital path", NULL, "ADCR Power"},
759 {"ADCL Digital path", NULL, "DMIC Enable"},
760 {"ADCR Digital path", NULL, "DMIC Enable"},
761
762 {"AIFTX", NULL, "ADCL Digital path"},
763 {"AIFTX", NULL, "ADCR Digital path"},
764
765 {"AIFTX", NULL, "System Clock"},
766 {"AIFRX", NULL, "System Clock"},
767
768 {"DDACL", NULL, "AIFRX"},
769 {"DDACR", NULL, "AIFRX"},
770
771 {"HP amp L", NULL, "DDACL"},
772 {"HP amp R", NULL, "DDACR"},
773
774 {"Charge Pump", NULL, "HP amp L"},
775 {"Charge Pump", NULL, "HP amp R"},
776
777 {"ADACL", NULL, "Charge Pump"},
778 {"ADACR", NULL, "Charge Pump"},
779 {"ADACL Clock", NULL, "ADACL"},
780 {"ADACR Clock", NULL, "ADACR"},
781
782 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
783 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
784 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
785 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
786 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
787 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
788 {"Output DACL", NULL, "Output Driver L Stage 3"},
789 {"Output DACR", NULL, "Output Driver R Stage 3"},
790
791 {"HPOL Pulldown", NULL, "Output DACL"},
792 {"HPOR Pulldown", NULL, "Output DACR"},
793 {"HP Boost Driver", NULL, "HPOL Pulldown"},
794 {"HP Boost Driver", NULL, "HPOR Pulldown"},
795
796 {"Class G", NULL, "HP Boost Driver"},
797 {"HPOL", NULL, "Class G"},
798 {"HPOR", NULL, "Class G"},
799 };
800
801 static const struct nau8821_osr_attr *
802 nau8821_get_osr(struct nau8821 *nau8821, int stream)
803 {
804 unsigned int osr;
805
806 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
807 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
808 osr &= NAU8821_DAC_OVERSAMPLE_MASK;
809 if (osr >= ARRAY_SIZE(osr_dac_sel))
810 return NULL;
811 return &osr_dac_sel[osr];
812 } else {
813 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
814 osr &= NAU8821_ADC_SYNC_DOWN_MASK;
815 if (osr >= ARRAY_SIZE(osr_adc_sel))
816 return NULL;
817 return &osr_adc_sel[osr];
818 }
819 }
820
821 static int nau8821_dai_startup(struct snd_pcm_substream *substream,
822 struct snd_soc_dai *dai)
823 {
824 struct snd_soc_component *component = dai->component;
825 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
826 const struct nau8821_osr_attr *osr;
827
828 osr = nau8821_get_osr(nau8821, substream->stream);
829 if (!osr || !osr->osr)
830 return -EINVAL;
831
832 return snd_pcm_hw_constraint_minmax(substream->runtime,
833 SNDRV_PCM_HW_PARAM_RATE,
834 0, CLK_DA_AD_MAX / osr->osr);
835 }
836
837 static int nau8821_hw_params(struct snd_pcm_substream *substream,
838 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
839 {
840 struct snd_soc_component *component = dai->component;
841 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
842 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div;
843 const struct nau8821_osr_attr *osr;
844
845 nau8821->fs = params_rate(params);
846 /* CLK_DAC or CLK_ADC = OSR * FS
847 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
848 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
849 * values must be selected such that the maximum frequency is less
850 * than 6.144 MHz.
851 */
852 osr = nau8821_get_osr(nau8821, substream->stream);
853 if (!osr || !osr->osr)
854 return -EINVAL;
855 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
856 return -EINVAL;
857 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
858 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
859 NAU8821_CLK_DAC_SRC_MASK,
860 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
861 else
862 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
863 NAU8821_CLK_ADC_SRC_MASK,
864 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
865
866 /* make BCLK and LRC divde configuration if the codec as master. */
867 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
868 if (ctrl_val & NAU8821_I2S_MS_MASTER) {
869 /* get the bclk and fs ratio */
870 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
871 if (bclk_fs <= 32)
872 clk_div = 3;
873 else if (bclk_fs <= 64)
874 clk_div = 2;
875 else if (bclk_fs <= 128)
876 clk_div = 1;
877 else {
878 return -EINVAL;
879 }
880 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
881 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
882 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
883 }
884
885 switch (params_width(params)) {
886 case 16:
887 val_len |= NAU8821_I2S_DL_16;
888 break;
889 case 20:
890 val_len |= NAU8821_I2S_DL_20;
891 break;
892 case 24:
893 val_len |= NAU8821_I2S_DL_24;
894 break;
895 case 32:
896 val_len |= NAU8821_I2S_DL_32;
897 break;
898 default:
899 return -EINVAL;
900 }
901
902 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
903 NAU8821_I2S_DL_MASK, val_len);
904
905 return 0;
906 }
907
908 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
909 {
910 struct snd_soc_component *component = codec_dai->component;
911 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
912 unsigned int ctrl1_val = 0, ctrl2_val = 0;
913
914 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
915 case SND_SOC_DAIFMT_CBP_CFP:
916 ctrl2_val |= NAU8821_I2S_MS_MASTER;
917 break;
918 case SND_SOC_DAIFMT_CBC_CFC:
919 break;
920 default:
921 return -EINVAL;
922 }
923
924 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
925 case SND_SOC_DAIFMT_NB_NF:
926 break;
927 case SND_SOC_DAIFMT_IB_NF:
928 ctrl1_val |= NAU8821_I2S_BP_INV;
929 break;
930 default:
931 return -EINVAL;
932 }
933
934 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
935 case SND_SOC_DAIFMT_I2S:
936 ctrl1_val |= NAU8821_I2S_DF_I2S;
937 break;
938 case SND_SOC_DAIFMT_LEFT_J:
939 ctrl1_val |= NAU8821_I2S_DF_LEFT;
940 break;
941 case SND_SOC_DAIFMT_RIGHT_J:
942 ctrl1_val |= NAU8821_I2S_DF_RIGTH;
943 break;
944 case SND_SOC_DAIFMT_DSP_A:
945 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
946 break;
947 case SND_SOC_DAIFMT_DSP_B:
948 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
949 ctrl1_val |= NAU8821_I2S_PCMB_EN;
950 break;
951 default:
952 return -EINVAL;
953 }
954
955 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
956 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
957 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
958 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
959 NAU8821_I2S_MS_MASK, ctrl2_val);
960
961 return 0;
962 }
963
964 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
965 int direction)
966 {
967 struct snd_soc_component *component = dai->component;
968 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
969 unsigned int val = 0;
970
971 if (mute)
972 val = NAU8821_DAC_SOFT_MUTE;
973
974 return regmap_update_bits(nau8821->regmap,
975 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
976 }
977
978 static const struct snd_soc_dai_ops nau8821_dai_ops = {
979 .startup = nau8821_dai_startup,
980 .hw_params = nau8821_hw_params,
981 .set_fmt = nau8821_set_dai_fmt,
982 .mute_stream = nau8821_digital_mute,
983 .no_capture_mute = 1,
984 };
985
986 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
987 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
988 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
989
990 static struct snd_soc_dai_driver nau8821_dai = {
991 .name = NUVOTON_CODEC_DAI,
992 .playback = {
993 .stream_name = "Playback",
994 .channels_min = 1,
995 .channels_max = 2,
996 .rates = NAU8821_RATES,
997 .formats = NAU8821_FORMATS,
998 },
999 .capture = {
1000 .stream_name = "Capture",
1001 .channels_min = 1,
1002 .channels_max = 2,
1003 .rates = NAU8821_RATES,
1004 .formats = NAU8821_FORMATS,
1005 },
1006 .ops = &nau8821_dai_ops,
1007 };
1008
1009
1010 static bool nau8821_is_jack_inserted(struct regmap *regmap)
1011 {
1012 bool active_high, is_high;
1013 int status, jkdet;
1014
1015 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
1016 active_high = jkdet & NAU8821_JACK_POLARITY;
1017 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
1018 is_high = status & NAU8821_GPIO2_IN;
1019 /* return jack connection status according to jack insertion logic
1020 * active high or active low.
1021 */
1022 return active_high == is_high;
1023 }
1024
1025 static void nau8821_int_status_clear_all(struct regmap *regmap)
1026 {
1027 int active_irq, clear_irq, i;
1028
1029 /* Reset the intrruption status from rightmost bit if the corres-
1030 * ponding irq event occurs.
1031 */
1032 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
1033 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
1034 clear_irq = (0x1 << i);
1035 if (active_irq & clear_irq)
1036 regmap_write(regmap,
1037 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1038 }
1039 }
1040
1041 static void nau8821_eject_jack(struct nau8821 *nau8821)
1042 {
1043 struct snd_soc_dapm_context *dapm = nau8821->dapm;
1044 struct regmap *regmap = nau8821->regmap;
1045 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1046
1047 /* Detach 2kOhm Resistors from MICBIAS to MICGND */
1048 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1049 NAU8821_MICBIAS_JKR2, 0);
1050 /* HPL/HPR short to ground */
1051 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1052 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1053 snd_soc_component_disable_pin(component, "MICBIAS");
1054 snd_soc_dapm_sync(dapm);
1055
1056 /* Clear all interruption status */
1057 nau8821_int_status_clear_all(regmap);
1058
1059 /* Enable the insertion interruption, disable the ejection inter-
1060 * ruption, and then bypass de-bounce circuit.
1061 */
1062 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1063 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
1064 NAU8821_IRQ_EJECT_DIS);
1065 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1066 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1067 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1068 NAU8821_IRQ_EJECT_EN);
1069
1070 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1071 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
1072
1073 /* Close clock for jack type detection at manual mode */
1074 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
1075 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1076
1077 /* Recover to normal channel input */
1078 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1079 NAU8821_ADC_R_SRC_EN, 0);
1080 if (nau8821->key_enable) {
1081 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1082 NAU8821_IRQ_KEY_RELEASE_EN |
1083 NAU8821_IRQ_KEY_PRESS_EN,
1084 NAU8821_IRQ_KEY_RELEASE_EN |
1085 NAU8821_IRQ_KEY_PRESS_EN);
1086 regmap_update_bits(regmap,
1087 NAU8821_R12_INTERRUPT_DIS_CTRL,
1088 NAU8821_IRQ_KEY_RELEASE_DIS |
1089 NAU8821_IRQ_KEY_PRESS_DIS,
1090 NAU8821_IRQ_KEY_RELEASE_DIS |
1091 NAU8821_IRQ_KEY_PRESS_DIS);
1092 }
1093
1094 }
1095
1096 static void nau8821_jdet_work(struct work_struct *work)
1097 {
1098 struct nau8821 *nau8821 =
1099 container_of(work, struct nau8821, jdet_work);
1100 struct snd_soc_dapm_context *dapm = nau8821->dapm;
1101 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1102 struct regmap *regmap = nau8821->regmap;
1103 int jack_status_reg, mic_detected, event = 0, event_mask = 0;
1104
1105 snd_soc_component_force_enable_pin(component, "MICBIAS");
1106 snd_soc_dapm_sync(dapm);
1107 msleep(20);
1108
1109 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
1110 mic_detected = !(jack_status_reg & NAU8821_KEYDET);
1111 if (mic_detected) {
1112 dev_dbg(nau8821->dev, "Headset connected\n");
1113 event |= SND_JACK_HEADSET;
1114
1115 /* 2kOhm Resistor from MICBIAS to MICGND1 */
1116 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1117 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
1118 /* Latch Right Channel Analog data
1119 * input into the Right Channel Filter
1120 */
1121 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1122 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
1123 if (nau8821->key_enable) {
1124 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1125 NAU8821_IRQ_KEY_RELEASE_EN |
1126 NAU8821_IRQ_KEY_PRESS_EN, 0);
1127 regmap_update_bits(regmap,
1128 NAU8821_R12_INTERRUPT_DIS_CTRL,
1129 NAU8821_IRQ_KEY_RELEASE_DIS |
1130 NAU8821_IRQ_KEY_PRESS_DIS, 0);
1131 } else {
1132 snd_soc_component_disable_pin(component, "MICBIAS");
1133 snd_soc_dapm_sync(nau8821->dapm);
1134 }
1135 } else {
1136 dev_dbg(nau8821->dev, "Headphone connected\n");
1137 event |= SND_JACK_HEADPHONE;
1138 snd_soc_component_disable_pin(component, "MICBIAS");
1139 snd_soc_dapm_sync(dapm);
1140 }
1141 event_mask |= SND_JACK_HEADSET;
1142 snd_soc_jack_report(nau8821->jack, event, event_mask);
1143 }
1144
1145 /* Enable interruptions with internal clock. */
1146 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
1147 {
1148 struct regmap *regmap = nau8821->regmap;
1149
1150 /* Enable internal VCO needed for interruptions */
1151 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
1152 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
1153
1154 /* Chip needs one FSCLK cycle in order to generate interruptions,
1155 * as we cannot guarantee one will be provided by the system. Turning
1156 * master mode on then off enables us to generate that FSCLK cycle
1157 * with a minimum of contention on the clock bus.
1158 */
1159 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1160 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
1161 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1162 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
1163
1164 /* Not bypass de-bounce circuit */
1165 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1166 NAU8821_JACK_DET_DB_BYPASS, 0);
1167
1168 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1169 NAU8821_IRQ_EJECT_EN, 0);
1170 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1171 NAU8821_IRQ_EJECT_DIS, 0);
1172 }
1173
1174 static irqreturn_t nau8821_interrupt(int irq, void *data)
1175 {
1176 struct nau8821 *nau8821 = (struct nau8821 *)data;
1177 struct regmap *regmap = nau8821->regmap;
1178 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1179
1180 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
1181 dev_err(nau8821->dev, "failed to read irq status\n");
1182 return IRQ_NONE;
1183 }
1184
1185 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
1186
1187 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
1188 NAU8821_JACK_EJECT_DETECTED) {
1189 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1190 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
1191 nau8821_eject_jack(nau8821);
1192 event_mask |= SND_JACK_HEADSET;
1193 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
1194 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) {
1195 event |= NAU8821_BUTTON;
1196 event_mask |= NAU8821_BUTTON;
1197 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ;
1198 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) {
1199 event_mask = NAU8821_BUTTON;
1200 clear_irq = NAU8821_KEY_RELEASE_IRQ;
1201 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
1202 NAU8821_JACK_INSERT_DETECTED) {
1203 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1204 NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
1205 if (nau8821_is_jack_inserted(regmap)) {
1206 /* detect microphone and jack type */
1207 cancel_work_sync(&nau8821->jdet_work);
1208 schedule_work(&nau8821->jdet_work);
1209 /* Turn off insertion interruption at manual mode */
1210 regmap_update_bits(regmap,
1211 NAU8821_R12_INTERRUPT_DIS_CTRL,
1212 NAU8821_IRQ_INSERT_DIS,
1213 NAU8821_IRQ_INSERT_DIS);
1214 regmap_update_bits(regmap,
1215 NAU8821_R0F_INTERRUPT_MASK,
1216 NAU8821_IRQ_INSERT_EN,
1217 NAU8821_IRQ_INSERT_EN);
1218 nau8821_setup_inserted_irq(nau8821);
1219 } else {
1220 dev_warn(nau8821->dev,
1221 "Inserted IRQ fired but not connected\n");
1222 nau8821_eject_jack(nau8821);
1223 }
1224 }
1225
1226 if (!clear_irq)
1227 clear_irq = active_irq;
1228 /* clears the rightmost interruption */
1229 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1230
1231 if (event_mask)
1232 snd_soc_jack_report(nau8821->jack, event, event_mask);
1233
1234 return IRQ_HANDLED;
1235 }
1236
1237 static const struct regmap_config nau8821_regmap_config = {
1238 .val_bits = NAU8821_REG_DATA_LEN,
1239 .reg_bits = NAU8821_REG_ADDR_LEN,
1240
1241 .max_register = NAU8821_REG_MAX,
1242 .readable_reg = nau8821_readable_reg,
1243 .writeable_reg = nau8821_writeable_reg,
1244 .volatile_reg = nau8821_volatile_reg,
1245
1246 .cache_type = REGCACHE_RBTREE,
1247 .reg_defaults = nau8821_reg_defaults,
1248 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
1249 };
1250
1251 static int nau8821_component_probe(struct snd_soc_component *component)
1252 {
1253 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1254 struct snd_soc_dapm_context *dapm =
1255 snd_soc_component_get_dapm(component);
1256
1257 nau8821->dapm = dapm;
1258
1259 return 0;
1260 }
1261
1262 /**
1263 * nau8821_calc_fll_param - Calculate FLL parameters.
1264 * @fll_in: external clock provided to codec.
1265 * @fs: sampling rate.
1266 * @fll_param: Pointer to structure of FLL parameters.
1267 *
1268 * Calculate FLL parameters to configure codec.
1269 *
1270 * Returns 0 for success or negative error code.
1271 */
1272 static int nau8821_calc_fll_param(unsigned int fll_in,
1273 unsigned int fs, struct nau8821_fll *fll_param)
1274 {
1275 u64 fvco, fvco_max;
1276 unsigned int fref, i, fvco_sel;
1277
1278 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by
1279 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1280 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK
1281 */
1282 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1283 fref = fll_in >> fll_pre_scalar[i].param;
1284 if (fref <= NAU_FREF_MAX)
1285 break;
1286 }
1287 if (i == ARRAY_SIZE(fll_pre_scalar))
1288 return -EINVAL;
1289 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1290
1291 /* Choose the FLL ratio based on FREF */
1292 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1293 if (fref >= fll_ratio[i].param)
1294 break;
1295 }
1296 if (i == ARRAY_SIZE(fll_ratio))
1297 return -EINVAL;
1298 fll_param->ratio = fll_ratio[i].val;
1299
1300 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1301 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1302 * guaranteed across the full range of operation.
1303 * FDCO = freq_out * 2 * mclk_src_scaling
1304 */
1305 fvco_max = 0;
1306 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1307 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1308 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1309 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1310 fvco_max < fvco) {
1311 fvco_max = fvco;
1312 fvco_sel = i;
1313 }
1314 }
1315 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1316 return -EINVAL;
1317 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1318
1319 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
1320 * input based on FDCO, FREF and FLL ratio.
1321 */
1322 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1323 fll_param->fll_int = (fvco >> 24) & 0x3ff;
1324 fll_param->fll_frac = fvco & 0xffffff;
1325
1326 return 0;
1327 }
1328
1329 static void nau8821_fll_apply(struct nau8821 *nau8821,
1330 struct nau8821_fll *fll_param)
1331 {
1332 struct regmap *regmap = nau8821->regmap;
1333
1334 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1335 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
1336 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1337 /* Make DSP operate at high speed for better performance. */
1338 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1339 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
1340 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1341 /* FLL 24-bit fractional input */
1342 regmap_write(regmap, NAU8821_R0A_FLL7,
1343 (fll_param->fll_frac >> 16) & 0xff);
1344 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1345 /* FLL 10-bit integer input */
1346 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1347 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1348 /* FLL pre-scaler */
1349 regmap_update_bits(regmap, NAU8821_R07_FLL4,
1350 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
1351 NAU8821_HIGHBW_EN |
1352 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1353 /* select divided VCO input */
1354 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1355 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
1356 /* Disable free-running mode */
1357 regmap_update_bits(regmap,
1358 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
1359 if (fll_param->fll_frac) {
1360 /* set FLL loop filter enable and cutoff frequency at 500Khz */
1361 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1362 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1363 NAU8821_FLL_FTR_SW_MASK,
1364 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1365 NAU8821_FLL_FTR_SW_FILTER);
1366 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1367 NAU8821_SDM_EN | NAU8821_CUTOFF500,
1368 NAU8821_SDM_EN | NAU8821_CUTOFF500);
1369 } else {
1370 /* disable FLL loop filter and cutoff frequency */
1371 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1372 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1373 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
1374 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1375 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
1376 }
1377 }
1378
1379 /**
1380 * nau8821_set_fll - FLL configuration of nau8821
1381 * @component: codec component
1382 * @pll_id: PLL requested
1383 * @source: clock source
1384 * @freq_in: frequency of input clock source
1385 * @freq_out: must be 256*Fs in order to achieve the best performance
1386 *
1387 * The FLL function can select BCLK or MCLK as the input clock source.
1388 *
1389 * Returns 0 if the parameters have been applied successfully
1390 * or negative error code.
1391 */
1392 static int nau8821_set_fll(struct snd_soc_component *component,
1393 int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
1394 {
1395 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1396 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
1397 int ret, fs;
1398
1399 fs = freq_out >> 8;
1400 ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
1401 if (ret) {
1402 dev_err(nau8821->dev,
1403 "Unsupported input clock %d to output clock %d\n",
1404 freq_in, freq_out);
1405 return ret;
1406 }
1407 dev_dbg(nau8821->dev,
1408 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1409 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1410 fll_param->fll_int, fll_param->clk_ref_div);
1411
1412 nau8821_fll_apply(nau8821, fll_param);
1413 mdelay(2);
1414 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1415 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1416
1417 return 0;
1418 }
1419
1420 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
1421 {
1422 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1423 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
1424 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1425 NAU8821_DCO_EN, 0);
1426 /* Make DSP operate as default setting for power saving. */
1427 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1428 NAU8821_ICTRL_LATCH_MASK, 0);
1429 }
1430
1431 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
1432 int clk_id, unsigned int freq)
1433 {
1434 struct regmap *regmap = nau8821->regmap;
1435
1436 switch (clk_id) {
1437 case NAU8821_CLK_DIS:
1438 /* Clock provided externally and disable internal VCO clock */
1439 nau8821_configure_mclk_as_sysclk(regmap);
1440 break;
1441 case NAU8821_CLK_MCLK:
1442 nau8821_configure_mclk_as_sysclk(regmap);
1443 /* MCLK not changed by clock tree */
1444 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1445 NAU8821_CLK_MCLK_SRC_MASK, 0);
1446 break;
1447 case NAU8821_CLK_INTERNAL:
1448 if (nau8821_is_jack_inserted(regmap)) {
1449 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1450 NAU8821_DCO_EN, NAU8821_DCO_EN);
1451 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1452 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1453 /* Decrease the VCO frequency and make DSP operate
1454 * as default setting for power saving.
1455 */
1456 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1457 NAU8821_CLK_MCLK_SRC_MASK, 0xf);
1458 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1459 NAU8821_ICTRL_LATCH_MASK |
1460 NAU8821_FLL_RATIO_MASK, 0x10);
1461 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1462 NAU8821_SDM_EN, NAU8821_SDM_EN);
1463 }
1464 break;
1465 case NAU8821_CLK_FLL_MCLK:
1466 /* Higher FLL reference input frequency can only set lower
1467 * gain error, such as 0000 for input reference from MCLK
1468 * 12.288Mhz.
1469 */
1470 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1471 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1472 NAU8821_FLL_CLK_SRC_MCLK | 0);
1473 break;
1474 case NAU8821_CLK_FLL_BLK:
1475 /* If FLL reference input is from low frequency source,
1476 * higher error gain can apply such as 0xf which has
1477 * the most sensitive gain error correction threshold,
1478 * Therefore, FLL has the most accurate DCO to
1479 * target frequency.
1480 */
1481 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1482 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1483 NAU8821_FLL_CLK_SRC_BLK |
1484 (0xf << NAU8821_GAIN_ERR_SFT));
1485 break;
1486 case NAU8821_CLK_FLL_FS:
1487 /* If FLL reference input is from low frequency source,
1488 * higher error gain can apply such as 0xf which has
1489 * the most sensitive gain error correction threshold,
1490 * Therefore, FLL has the most accurate DCO to
1491 * target frequency.
1492 */
1493 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1494 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1495 NAU8821_FLL_CLK_SRC_FS |
1496 (0xf << NAU8821_GAIN_ERR_SFT));
1497 break;
1498 default:
1499 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1500 return -EINVAL;
1501 }
1502 nau8821->clk_id = clk_id;
1503 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1504 nau8821->clk_id);
1505
1506 return 0;
1507 }
1508
1509 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
1510 int source, unsigned int freq, int dir)
1511 {
1512 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1513
1514 return nau8821_configure_sysclk(nau8821, clk_id, freq);
1515 }
1516
1517 static int nau8821_resume_setup(struct nau8821 *nau8821)
1518 {
1519 struct regmap *regmap = nau8821->regmap;
1520
1521 /* Close clock when jack type detection at manual mode */
1522 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1523 if (nau8821->irq) {
1524 /* Clear all interruption status */
1525 nau8821_int_status_clear_all(regmap);
1526
1527 /* Enable both insertion and ejection interruptions, and then
1528 * bypass de-bounce circuit.
1529 */
1530 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1531 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
1532 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1533 NAU8821_JACK_DET_DB_BYPASS,
1534 NAU8821_JACK_DET_DB_BYPASS);
1535 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1536 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
1537 }
1538
1539 return 0;
1540 }
1541
1542 static int nau8821_set_bias_level(struct snd_soc_component *component,
1543 enum snd_soc_bias_level level)
1544 {
1545 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1546 struct regmap *regmap = nau8821->regmap;
1547
1548 switch (level) {
1549 case SND_SOC_BIAS_ON:
1550 break;
1551
1552 case SND_SOC_BIAS_PREPARE:
1553 break;
1554
1555 case SND_SOC_BIAS_STANDBY:
1556 /* Setup codec configuration after resume */
1557 if (snd_soc_component_get_bias_level(component) ==
1558 SND_SOC_BIAS_OFF)
1559 nau8821_resume_setup(nau8821);
1560 break;
1561
1562 case SND_SOC_BIAS_OFF:
1563 /* HPL/HPR short to ground */
1564 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1565 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1566 if (nau8821->irq) {
1567 /* Reset the configuration of jack type for detection.
1568 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2.
1569 */
1570 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1571 NAU8821_MICBIAS_JKR2, 0);
1572 /* Turn off all interruptions before system shutdown.
1573 * Keep theinterruption quiet before resume
1574 * setup completes.
1575 */
1576 regmap_write(regmap,
1577 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
1578 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1579 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1580 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
1581 }
1582 break;
1583 default:
1584 break;
1585 }
1586
1587 return 0;
1588 }
1589
1590 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
1591 {
1592 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1593
1594 if (nau8821->irq)
1595 disable_irq(nau8821->irq);
1596 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1597 /* Power down codec power; don't support button wakeup */
1598 snd_soc_component_disable_pin(component, "MICBIAS");
1599 snd_soc_dapm_sync(nau8821->dapm);
1600 regcache_cache_only(nau8821->regmap, true);
1601 regcache_mark_dirty(nau8821->regmap);
1602
1603 return 0;
1604 }
1605
1606 static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
1607 {
1608 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1609
1610 regcache_cache_only(nau8821->regmap, false);
1611 regcache_sync(nau8821->regmap);
1612 if (nau8821->irq)
1613 enable_irq(nau8821->irq);
1614
1615 return 0;
1616 }
1617
1618 static const struct snd_soc_component_driver nau8821_component_driver = {
1619 .probe = nau8821_component_probe,
1620 .set_sysclk = nau8821_set_sysclk,
1621 .set_pll = nau8821_set_fll,
1622 .set_bias_level = nau8821_set_bias_level,
1623 .suspend = nau8821_suspend,
1624 .resume = nau8821_resume,
1625 .controls = nau8821_controls,
1626 .num_controls = ARRAY_SIZE(nau8821_controls),
1627 .dapm_widgets = nau8821_dapm_widgets,
1628 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets),
1629 .dapm_routes = nau8821_dapm_routes,
1630 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes),
1631 .suspend_bias_off = 1,
1632 .idle_bias_on = 1,
1633 .use_pmdown_time = 1,
1634 .endianness = 1,
1635 };
1636
1637 /**
1638 * nau8821_enable_jack_detect - Specify a jack for event reporting
1639 *
1640 * @component: component to register the jack with
1641 * @jack: jack to use to report headset and button events on
1642 *
1643 * After this function has been called the headset insert/remove and button
1644 * events will be routed to the given jack. Jack can be null to stop
1645 * reporting.
1646 */
1647 int nau8821_enable_jack_detect(struct snd_soc_component *component,
1648 struct snd_soc_jack *jack)
1649 {
1650 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1651 int ret;
1652
1653 nau8821->jack = jack;
1654 /* Initiate jack detection work queue */
1655 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1656 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1657 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1658 "nau8821", nau8821);
1659 if (ret) {
1660 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1661 nau8821->irq, ret);
1662 return ret;
1663 }
1664
1665 return ret;
1666 }
1667 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
1668
1669 static void nau8821_reset_chip(struct regmap *regmap)
1670 {
1671 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1672 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1673 }
1674
1675 static void nau8821_print_device_properties(struct nau8821 *nau8821)
1676 {
1677 struct device *dev = nau8821->dev;
1678
1679 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
1680 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
1681 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
1682 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
1683 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
1684 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
1685 dev_dbg(dev, "jack-insert-debounce: %d\n",
1686 nau8821->jack_insert_debounce);
1687 dev_dbg(dev, "jack-eject-debounce: %d\n",
1688 nau8821->jack_eject_debounce);
1689 dev_dbg(dev, "dmic-clk-threshold: %d\n",
1690 nau8821->dmic_clk_threshold);
1691 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable);
1692 dev_dbg(dev, "adc-delay-ms: %d\n", nau8821->adc_delay);
1693 }
1694
1695 static int nau8821_read_device_properties(struct device *dev,
1696 struct nau8821 *nau8821)
1697 {
1698 int ret;
1699
1700 nau8821->jkdet_enable = device_property_read_bool(dev,
1701 "nuvoton,jkdet-enable");
1702 nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1703 "nuvoton,jkdet-pull-enable");
1704 nau8821->jkdet_pull_up = device_property_read_bool(dev,
1705 "nuvoton,jkdet-pull-up");
1706 nau8821->key_enable = device_property_read_bool(dev,
1707 "nuvoton,key-enable");
1708 nau8821->left_input_single_end = device_property_read_bool(dev,
1709 "nuvoton,left-input-single-end");
1710 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1711 &nau8821->jkdet_polarity);
1712 if (ret)
1713 nau8821->jkdet_polarity = 1;
1714 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1715 &nau8821->micbias_voltage);
1716 if (ret)
1717 nau8821->micbias_voltage = 6;
1718 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1719 &nau8821->vref_impedance);
1720 if (ret)
1721 nau8821->vref_impedance = 2;
1722 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1723 &nau8821->jack_insert_debounce);
1724 if (ret)
1725 nau8821->jack_insert_debounce = 7;
1726 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1727 &nau8821->jack_eject_debounce);
1728 if (ret)
1729 nau8821->jack_eject_debounce = 0;
1730 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1731 &nau8821->dmic_clk_threshold);
1732 if (ret)
1733 nau8821->dmic_clk_threshold = 3072000;
1734 ret = device_property_read_u32(dev, "nuvoton,dmic-slew-rate",
1735 &nau8821->dmic_slew_rate);
1736 if (ret)
1737 nau8821->dmic_slew_rate = 0;
1738 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms",
1739 &nau8821->adc_delay);
1740 if (ret)
1741 nau8821->adc_delay = 125;
1742 if (nau8821->adc_delay < 125 || nau8821->adc_delay > 500)
1743 dev_warn(dev, "Please set the suitable delay time!\n");
1744
1745 return 0;
1746 }
1747
1748 static void nau8821_init_regs(struct nau8821 *nau8821)
1749 {
1750 struct regmap *regmap = nau8821->regmap;
1751
1752 /* Enable Bias/Vmid */
1753 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1754 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
1755 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1756 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
1757 /* VMID Tieoff setting and enable TESTDAC.
1758 * This sets the analog DAC inputs to a '' input signal to avoid
1759 * any glitches due to power up transients in both the analog and
1760 * digital DAC circuit.
1761 */
1762 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1763 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
1764 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1765 NAU8821_BIAS_TESTDAC_EN);
1766 /* Disable short Frame Sync detection logic */
1767 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
1768 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
1769 /* Disable Boost Driver, Automatic Short circuit protection enable */
1770 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1771 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1772 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
1773 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1774 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
1775 /* Class G timer 64ms */
1776 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
1777 NAU8821_CLASSG_TIMER_MASK,
1778 0x20 << NAU8821_CLASSG_TIMER_SFT);
1779 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1780 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
1781 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1782 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
1783 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1784 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
1785 /* Disable DACR/L power */
1786 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
1787 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
1788 /* DAC clock delay 2ns, VREF */
1789 regmap_update_bits(regmap, NAU8821_R73_RDAC,
1790 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
1791 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
1792 (0x3 << NAU8821_DAC_VREF_SFT));
1793
1794 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1795 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1796 /* Default oversampling/decimations settings are unusable
1797 * (audible hiss). Set it to something better.
1798 */
1799 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1800 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
1801 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
1802 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
1803 regmap_update_bits(regmap, NAU8821_R13_DMIC_CTRL,
1804 NAU8821_DMIC_SLEW_MASK, nau8821->dmic_slew_rate <<
1805 NAU8821_DMIC_SLEW_SFT);
1806 if (nau8821->left_input_single_end) {
1807 regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE,
1808 NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN);
1809 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1810 NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN);
1811 }
1812 }
1813
1814 static int nau8821_setup_irq(struct nau8821 *nau8821)
1815 {
1816 struct regmap *regmap = nau8821->regmap;
1817
1818 /* Jack detection */
1819 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1820 NAU8821_JKDET_OUTPUT_EN,
1821 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1822 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1823 NAU8821_JKDET_PULL_EN,
1824 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1825 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1826 NAU8821_JKDET_PULL_UP,
1827 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1828 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1829 NAU8821_JACK_POLARITY,
1830 /* jkdet_polarity - 1 is for active-low */
1831 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1832 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1833 NAU8821_JACK_INSERT_DEBOUNCE_MASK,
1834 nau8821->jack_insert_debounce <<
1835 NAU8821_JACK_INSERT_DEBOUNCE_SFT);
1836 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1837 NAU8821_JACK_EJECT_DEBOUNCE_MASK,
1838 nau8821->jack_eject_debounce <<
1839 NAU8821_JACK_EJECT_DEBOUNCE_SFT);
1840 /* Pull up IRQ pin */
1841 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1842 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
1843 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
1844 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
1845 /* Disable interruption before codec initiation done */
1846 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1847 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
1848
1849 return 0;
1850 }
1851
1852 /* Please keep this list alphabetically sorted */
1853 static const struct dmi_system_id nau8821_quirk_table[] = {
1854 {
1855 /* Positivo CW14Q01P-V2 */
1856 .matches = {
1857 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1858 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"),
1859 },
1860 .driver_data = (void *)(NAU8821_JD_ACTIVE_HIGH),
1861 },
1862 {}
1863 };
1864
1865 static void nau8821_check_quirks(void)
1866 {
1867 const struct dmi_system_id *dmi_id;
1868
1869 if (quirk_override != -1) {
1870 nau8821_quirk = quirk_override;
1871 return;
1872 }
1873
1874 dmi_id = dmi_first_match(nau8821_quirk_table);
1875 if (dmi_id)
1876 nau8821_quirk = (unsigned long)dmi_id->driver_data;
1877 }
1878
1879 static int nau8821_i2c_probe(struct i2c_client *i2c)
1880 {
1881 struct device *dev = &i2c->dev;
1882 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1883 int ret, value;
1884
1885 if (!nau8821) {
1886 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
1887 if (!nau8821)
1888 return -ENOMEM;
1889 nau8821_read_device_properties(dev, nau8821);
1890 }
1891 i2c_set_clientdata(i2c, nau8821);
1892
1893 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1894 if (IS_ERR(nau8821->regmap))
1895 return PTR_ERR(nau8821->regmap);
1896
1897 nau8821->dev = dev;
1898 nau8821->irq = i2c->irq;
1899
1900 nau8821_check_quirks();
1901
1902 if (nau8821_quirk & NAU8821_JD_ACTIVE_HIGH)
1903 nau8821->jkdet_polarity = 0;
1904
1905 nau8821_print_device_properties(nau8821);
1906
1907 nau8821_reset_chip(nau8821->regmap);
1908 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1909 if (ret) {
1910 dev_err(dev, "Failed to read device id (%d)\n", ret);
1911 return ret;
1912 }
1913 nau8821_init_regs(nau8821);
1914
1915 if (i2c->irq)
1916 nau8821_setup_irq(nau8821);
1917
1918 ret = devm_snd_soc_register_component(&i2c->dev,
1919 &nau8821_component_driver, &nau8821_dai, 1);
1920
1921 return ret;
1922 }
1923
1924 static const struct i2c_device_id nau8821_i2c_ids[] = {
1925 { "nau8821" },
1926 { }
1927 };
1928 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
1929
1930 #ifdef CONFIG_OF
1931 static const struct of_device_id nau8821_of_ids[] = {
1932 { .compatible = "nuvoton,nau8821", },
1933 {}
1934 };
1935 MODULE_DEVICE_TABLE(of, nau8821_of_ids);
1936 #endif
1937
1938 #ifdef CONFIG_ACPI
1939 static const struct acpi_device_id nau8821_acpi_match[] = {
1940 { "NVTN2020", 0 },
1941 {},
1942 };
1943 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
1944 #endif
1945
1946 static struct i2c_driver nau8821_driver = {
1947 .driver = {
1948 .name = "nau8821",
1949 .of_match_table = of_match_ptr(nau8821_of_ids),
1950 .acpi_match_table = ACPI_PTR(nau8821_acpi_match),
1951 },
1952 .probe = nau8821_i2c_probe,
1953 .id_table = nau8821_i2c_ids,
1954 };
1955 module_i2c_driver(nau8821_driver);
1956
1957 MODULE_DESCRIPTION("ASoC nau8821 driver");
1958 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>");
1959 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>");
1960 MODULE_LICENSE("GPL");
1961
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.