1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * NAU8825 ALSA SoC audio driver
4 *
5 * Copyright 2015 Google Inc.
6 * Author: Anatol Pomozov <anatol.pomozov@chrominium.org>
7 */
8
9 #ifndef __NAU8825_H__
10 #define __NAU8825_H__
11
12 #define NAU8825_REG_RESET 0x00
13 #define NAU8825_REG_ENA_CTRL 0x01
14 #define NAU8825_REG_IIC_ADDR_SET 0x02
15 #define NAU8825_REG_CLK_DIVIDER 0x03
16 #define NAU8825_REG_FLL1 0x04
17 #define NAU8825_REG_FLL2 0x05
18 #define NAU8825_REG_FLL3 0x06
19 #define NAU8825_REG_FLL4 0x07
20 #define NAU8825_REG_FLL5 0x08
21 #define NAU8825_REG_FLL6 0x09
22 #define NAU8825_REG_FLL_VCO_RSV 0x0a
23 #define NAU8825_REG_HSD_CTRL 0x0c
24 #define NAU8825_REG_JACK_DET_CTRL 0x0d
25 #define NAU8825_REG_INTERRUPT_MASK 0x0f
26 #define NAU8825_REG_IRQ_STATUS 0x10
27 #define NAU8825_REG_INT_CLR_KEY_STATUS 0x11
28 #define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12
29 #define NAU8825_REG_SAR_CTRL 0x13
30 #define NAU8825_REG_KEYDET_CTRL 0x14
31 #define NAU8825_REG_VDET_THRESHOLD_1 0x15
32 #define NAU8825_REG_VDET_THRESHOLD_2 0x16
33 #define NAU8825_REG_VDET_THRESHOLD_3 0x17
34 #define NAU8825_REG_VDET_THRESHOLD_4 0x18
35 #define NAU8825_REG_GPIO34_CTRL 0x19
36 #define NAU8825_REG_GPIO12_CTRL 0x1a
37 #define NAU8825_REG_TDM_CTRL 0x1b
38 #define NAU8825_REG_I2S_PCM_CTRL1 0x1c
39 #define NAU8825_REG_I2S_PCM_CTRL2 0x1d
40 #define NAU8825_REG_LEFT_TIME_SLOT 0x1e
41 #define NAU8825_REG_RIGHT_TIME_SLOT 0x1f
42 #define NAU8825_REG_BIQ_CTRL 0x20
43 #define NAU8825_REG_BIQ_COF1 0x21
44 #define NAU8825_REG_BIQ_COF2 0x22
45 #define NAU8825_REG_BIQ_COF3 0x23
46 #define NAU8825_REG_BIQ_COF4 0x24
47 #define NAU8825_REG_BIQ_COF5 0x25
48 #define NAU8825_REG_BIQ_COF6 0x26
49 #define NAU8825_REG_BIQ_COF7 0x27
50 #define NAU8825_REG_BIQ_COF8 0x28
51 #define NAU8825_REG_BIQ_COF9 0x29
52 #define NAU8825_REG_BIQ_COF10 0x2a
53 #define NAU8825_REG_ADC_RATE 0x2b
54 #define NAU8825_REG_DAC_CTRL1 0x2c
55 #define NAU8825_REG_DAC_CTRL2 0x2d
56 #define NAU8825_REG_DAC_DGAIN_CTRL 0x2f
57 #define NAU8825_REG_ADC_DGAIN_CTRL 0x30
58 #define NAU8825_REG_MUTE_CTRL 0x31
59 #define NAU8825_REG_HSVOL_CTRL 0x32
60 #define NAU8825_REG_DACL_CTRL 0x33
61 #define NAU8825_REG_DACR_CTRL 0x34
62 #define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38
63 #define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39
64 #define NAU8825_REG_ADC_DRC_SLOPES 0x3a
65 #define NAU8825_REG_ADC_DRC_ATKDCY 0x3b
66 #define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45
67 #define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46
68 #define NAU8825_REG_DAC_DRC_SLOPES 0x47
69 #define NAU8825_REG_DAC_DRC_ATKDCY 0x48
70 #define NAU8825_REG_IMM_MODE_CTRL 0x4c
71 #define NAU8825_REG_IMM_RMS_L 0x4d
72 #define NAU8825_REG_IMM_RMS_R 0x4e
73 #define NAU8825_REG_CLASSG_CTRL 0x50
74 #define NAU8825_REG_OPT_EFUSE_CTRL 0x51
75 #define NAU8825_REG_MISC_CTRL 0x55
76 #define NAU8825_REG_I2C_DEVICE_ID 0x58
77 #define NAU8825_REG_SARDOUT_RAM_STATUS 0x59
78 #define NAU8825_REG_FLL2_LOWER 0x5a
79 #define NAU8825_REG_FLL2_UPPER 0x5b
80 #define NAU8825_REG_BIAS_ADJ 0x66
81 #define NAU8825_REG_TRIM_SETTINGS 0x68
82 #define NAU8825_REG_ANALOG_CONTROL_1 0x69
83 #define NAU8825_REG_ANALOG_CONTROL_2 0x6a
84 #define NAU8825_REG_ANALOG_ADC_1 0x71
85 #define NAU8825_REG_ANALOG_ADC_2 0x72
86 #define NAU8825_REG_RDAC 0x73
87 #define NAU8825_REG_MIC_BIAS 0x74
88 #define NAU8825_REG_BOOST 0x76
89 #define NAU8825_REG_FEPGA 0x77
90 #define NAU8825_REG_POWER_UP_CONTROL 0x7f
91 #define NAU8825_REG_CHARGE_PUMP 0x80
92 #define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81
93 #define NAU8825_REG_GENERAL_STATUS 0x82
94 #define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS
95 /* 16-bit control register address, and 16-bits control register data */
96 #define NAU8825_REG_ADDR_LEN 16
97 #define NAU8825_REG_DATA_LEN 16
98
99 /* ENA_CTRL (0x1) */
100 #define NAU8825_ENABLE_DACR_SFT 10
101 #define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT)
102 #define NAU8825_ENABLE_DACL_SFT 9
103 #define NAU8825_ENABLE_DACL (1 << NAU8825_ENABLE_DACL_SFT)
104 #define NAU8825_ENABLE_ADC_SFT 8
105 #define NAU8825_ENABLE_ADC (1 << NAU8825_ENABLE_ADC_SFT)
106 #define NAU8825_ENABLE_ADC_CLK_SFT 7
107 #define NAU8825_ENABLE_ADC_CLK (1 << NAU8825_ENABLE_ADC_CLK_SFT)
108 #define NAU8825_ENABLE_DAC_CLK_SFT 6
109 #define NAU8825_ENABLE_DAC_CLK (1 << NAU8825_ENABLE_DAC_CLK_SFT)
110 #define NAU8825_ENABLE_SAR_SFT 1
111
112 /* CLK_DIVIDER (0x3) */
113 #define NAU8825_CLK_SRC_SFT 15
114 #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
115 #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
116 #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
117 #define NAU8825_CLK_ADC_SRC_SFT 6
118 #define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT)
119 #define NAU8825_CLK_DAC_SRC_SFT 4
120 #define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT)
121 #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0)
122
123 /* FLL1 (0x04) */
124 #define NAU8825_ICTRL_LATCH_SFT 10
125 #define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT)
126 #define NAU8825_FLL_RATIO_MASK (0x7f << 0)
127
128 /* FLL3 (0x06) */
129 #define NAU8825_GAIN_ERR_SFT 12
130 #define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT)
131 #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
132 #define NAU8825_FLL_CLK_SRC_SFT 10
133 #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT)
134 #define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT)
135 #define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT)
136 #define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT)
137
138 /* FLL4 (0x07) */
139 #define NAU8825_FLL_REF_DIV_SFT 10
140 #define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT)
141
142 /* FLL5 (0x08) */
143 #define NAU8825_FLL_PDB_DAC_EN (0x1 << 15)
144 #define NAU8825_FLL_LOOP_FTR_EN (0x1 << 14)
145 #define NAU8825_FLL_CLK_SW_MASK (0x1 << 13)
146 #define NAU8825_FLL_CLK_SW_N2 (0x1 << 13)
147 #define NAU8825_FLL_CLK_SW_REF (0x0 << 13)
148 #define NAU8825_FLL_FTR_SW_MASK (0x1 << 12)
149 #define NAU8825_FLL_FTR_SW_ACCU (0x1 << 12)
150 #define NAU8825_FLL_FTR_SW_FILTER (0x0 << 12)
151
152 /* FLL6 (0x9) */
153 #define NAU8825_DCO_EN (0x1 << 15)
154 #define NAU8825_SDM_EN (0x1 << 14)
155 #define NAU8825_CUTOFF500 (0x1 << 13)
156
157 /* HSD_CTRL (0xc) */
158 #define NAU8825_HSD_AUTO_MODE (1 << 6)
159 /* 0 - open, 1 - short to GND */
160 #define NAU8825_SPKR_ENGND1 (1 << 3)
161 #define NAU8825_SPKR_ENGND2 (1 << 2)
162 #define NAU8825_SPKR_DWN1R (1 << 1)
163 #define NAU8825_SPKR_DWN1L (1 << 0)
164
165 /* JACK_DET_CTRL (0xd) */
166 #define NAU8825_JACK_DET_RESTART (1 << 9)
167 #define NAU8825_JACK_DET_DB_BYPASS (1 << 8)
168 #define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5
169 #define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT)
170 #define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2
171 #define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT)
172 #define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */
173
174 /* INTERRUPT_MASK (0xf) */
175 #define NAU8825_IRQ_PIN_PULLUP (1 << 14)
176 #define NAU8825_IRQ_PIN_PULL_EN (1 << 13)
177 #define NAU8825_IRQ_OUTPUT_EN (1 << 11)
178 #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10)
179 #define NAU8825_IRQ_RMS_EN (1 << 8)
180 #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7)
181 #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5)
182 #define NAU8825_IRQ_EJECT_EN (1 << 2)
183 #define NAU8825_IRQ_INSERT_EN (1 << 0)
184
185 /* IRQ_STATUS (0x10) */
186 #define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10)
187 #define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9)
188 #define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8)
189 #define NAU8825_KEY_IRQ_MASK (0x7 << 5)
190 #define NAU8825_KEY_RELEASE_IRQ (1 << 7)
191 #define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6)
192 #define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5)
193 #define NAU8825_MIC_DETECTION_IRQ (1 << 4)
194 #define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2)
195 #define NAU8825_JACK_EJECTION_DETECTED (1 << 2)
196 #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0)
197 #define NAU8825_JACK_INSERTION_DETECTED (1 << 0)
198
199 /* INTERRUPT_DIS_CTRL (0x12) */
200 #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10)
201 #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7)
202 #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5)
203 #define NAU8825_IRQ_EJECT_DIS (1 << 2)
204 #define NAU8825_IRQ_INSERT_DIS (1 << 0)
205
206 /* SAR_CTRL (0x13) */
207 #define NAU8825_SAR_ADC_EN_SFT 12
208 #define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT)
209 #define NAU8825_SAR_INPUT_MASK (1 << 11)
210 #define NAU8825_SAR_INPUT_JKSLV (1 << 11)
211 #define NAU8825_SAR_INPUT_JKR2 (0 << 11)
212 #define NAU8825_SAR_TRACKING_GAIN_SFT 8
213 #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT)
214 #define NAU8825_SAR_HV_SEL_SFT 7
215 #define NAU8825_SAR_HV_SEL_MASK (1 << NAU8825_SAR_HV_SEL_SFT)
216 #define NAU8825_SAR_HV_SEL_MICBIAS (0 << NAU8825_SAR_HV_SEL_SFT)
217 #define NAU8825_SAR_HV_SEL_VDDMIC (1 << NAU8825_SAR_HV_SEL_SFT)
218 #define NAU8825_SAR_RES_SEL_SFT 4
219 #define NAU8825_SAR_RES_SEL_MASK (0x7 << NAU8825_SAR_RES_SEL_SFT)
220 #define NAU8825_SAR_RES_SEL_35K (0 << NAU8825_SAR_RES_SEL_SFT)
221 #define NAU8825_SAR_RES_SEL_70K (1 << NAU8825_SAR_RES_SEL_SFT)
222 #define NAU8825_SAR_RES_SEL_170K (2 << NAU8825_SAR_RES_SEL_SFT)
223 #define NAU8825_SAR_RES_SEL_360K (3 << NAU8825_SAR_RES_SEL_SFT)
224 #define NAU8825_SAR_RES_SEL_SHORTED (4 << NAU8825_SAR_RES_SEL_SFT)
225 #define NAU8825_SAR_COMPARE_TIME_SFT 2
226 #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2)
227 #define NAU8825_SAR_SAMPLING_TIME_SFT 0
228 #define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0)
229
230 /* KEYDET_CTRL (0x14) */
231 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12
232 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT)
233 #define NAU8825_KEYDET_LEVELS_NR_SFT 8
234 #define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8)
235 #define NAU8825_KEYDET_HYSTERESIS_SFT 0
236 #define NAU8825_KEYDET_HYSTERESIS_MASK 0xf
237
238 /* GPIO12_CTRL (0x1a) */
239 #define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */
240 #define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */
241 #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */
242
243 /* TDM_CTRL (0x1b) */
244 #define NAU8825_TDM_MODE (0x1 << 15)
245 #define NAU8825_TDM_OFFSET_EN (0x1 << 14)
246 #define NAU8825_TDM_DACL_RX_SFT 6
247 #define NAU8825_TDM_DACL_RX_MASK (0x3 << NAU8825_TDM_DACL_RX_SFT)
248 #define NAU8825_TDM_DACR_RX_SFT 4
249 #define NAU8825_TDM_DACR_RX_MASK (0x3 << NAU8825_TDM_DACR_RX_SFT)
250 #define NAU8825_TDM_TX_MASK 0x3
251
252 /* I2S_PCM_CTRL1 (0x1c) */
253 #define NAU8825_I2S_BP_SFT 7
254 #define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT)
255 #define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT)
256 #define NAU8825_I2S_PCMB_SFT 6
257 #define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT)
258 #define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT)
259 #define NAU8825_I2S_DL_SFT 2
260 #define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT)
261 #define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT)
262 #define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT)
263 #define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT)
264 #define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT)
265 #define NAU8825_I2S_DF_SFT 0
266 #define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT)
267 #define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT)
268 #define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT)
269 #define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT)
270 #define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT)
271
272 /* I2S_PCM_CTRL2 (0x1d) */
273 #define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
274 #define NAU8825_I2S_LRC_DIV_SFT 12
275 #define NAU8825_I2S_LRC_DIV_MASK (0x3 << NAU8825_I2S_LRC_DIV_SFT)
276 #define NAU8825_I2S_PCM_TS_EN_SFT 10
277 #define NAU8825_I2S_PCM_TS_EN_MASK (1 << NAU8825_I2S_PCM_TS_EN_SFT)
278 #define NAU8825_I2S_PCM_TS_EN (1 << NAU8825_I2S_PCM_TS_EN_SFT)
279 #define NAU8825_I2S_MS_SFT 3
280 #define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT)
281 #define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT)
282 #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT)
283 #define NAU8825_I2S_BLK_DIV_MASK 0x7
284
285 /* LEFT_TIME_SLOT (0x1e) */
286 #define NAU8825_FS_ERR_CMP_SEL_SFT 14
287 #define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT)
288 #define NAU8825_DIS_FS_SHORT_DET (1 << 13)
289 #define NAU8825_TSLOT_L0_MASK 0x3ff
290 #define NAU8825_TSLOT_R0_MASK 0x3ff
291
292 /* BIQ_CTRL (0x20) */
293 #define NAU8825_BIQ_WRT_SFT 4
294 #define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT)
295 #define NAU8825_BIQ_PATH_SFT 0
296 #define NAU8825_BIQ_PATH_MASK (1 << NAU8825_BIQ_PATH_SFT)
297 #define NAU8825_BIQ_PATH_ADC (0 << NAU8825_BIQ_PATH_SFT)
298 #define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT)
299
300 /* ADC_RATE (0x2b) */
301 #define NAU8825_ADC_SINC4_SFT 4
302 #define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT)
303 #define NAU8825_ADC_SYNC_DOWN_SFT 0
304 #define NAU8825_ADC_SYNC_DOWN_MASK 0x3
305 #define NAU8825_ADC_SYNC_DOWN_32 0
306 #define NAU8825_ADC_SYNC_DOWN_64 1
307 #define NAU8825_ADC_SYNC_DOWN_128 2
308 #define NAU8825_ADC_SYNC_DOWN_256 3
309
310 /* DAC_CTRL1 (0x2c) */
311 #define NAU8825_DAC_CLIP_OFF (1 << 7)
312 #define NAU8825_DAC_OVERSAMPLE_SFT 0
313 #define NAU8825_DAC_OVERSAMPLE_MASK 0x7
314 #define NAU8825_DAC_OVERSAMPLE_64 0
315 #define NAU8825_DAC_OVERSAMPLE_256 1
316 #define NAU8825_DAC_OVERSAMPLE_128 2
317 #define NAU8825_DAC_OVERSAMPLE_32 4
318
319 /* ADC_DGAIN_CTRL (0x30) */
320 #define NAU8825_ADC_DIG_VOL_MASK 0xff
321
322 /* MUTE_CTRL (0x31) */
323 #define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9)
324 #define NAU8825_DAC_SOFT_MUTE (1 << 9)
325
326 /* HSVOL_CTRL (0x32) */
327 #define NAU8825_HP_MUTE (1 << 15)
328 #define NAU8825_HP_MUTE_AUTO (1 << 14)
329 #define NAU8825_HPL_MUTE (1 << 13)
330 #define NAU8825_HPR_MUTE (1 << 12)
331 #define NAU8825_HPL_VOL_SFT 6
332 #define NAU8825_HPL_VOL_MASK (0x3f << NAU8825_HPL_VOL_SFT)
333 #define NAU8825_HPR_VOL_SFT 0
334 #define NAU8825_HPR_VOL_MASK (0x3f << NAU8825_HPR_VOL_SFT)
335 #define NAU8825_HP_VOL_MIN 0x36
336
337 /* DACL_CTRL (0x33) */
338 #define NAU8825_DACL_CH_SEL_SFT 9
339 #define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT)
340 #define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT)
341 #define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT)
342 #define NAU8825_DACL_CH_VOL_MASK 0xff
343
344 /* DACR_CTRL (0x34) */
345 #define NAU8825_DACR_CH_SEL_SFT 9
346 #define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT)
347 #define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT)
348 #define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT)
349 #define NAU8825_DACR_CH_VOL_MASK 0xff
350
351 /* IMM_MODE_CTRL (0x4C) */
352 #define NAU8825_IMM_THD_SFT 8
353 #define NAU8825_IMM_THD_MASK (0x3f << NAU8825_IMM_THD_SFT)
354 #define NAU8825_IMM_GEN_VOL_SFT 6
355 #define NAU8825_IMM_GEN_VOL_MASK (0x3 << NAU8825_IMM_GEN_VOL_SFT)
356 #define NAU8825_IMM_GEN_VOL_1_2nd (0x0 << NAU8825_IMM_GEN_VOL_SFT)
357 #define NAU8825_IMM_GEN_VOL_1_4th (0x1 << NAU8825_IMM_GEN_VOL_SFT)
358 #define NAU8825_IMM_GEN_VOL_1_8th (0x2 << NAU8825_IMM_GEN_VOL_SFT)
359 #define NAU8825_IMM_GEN_VOL_1_16th (0x3 << NAU8825_IMM_GEN_VOL_SFT)
360
361 #define NAU8825_IMM_CYC_SFT 4
362 #define NAU8825_IMM_CYC_MASK (0x3 << NAU8825_IMM_CYC_SFT)
363 #define NAU8825_IMM_CYC_1024 (0x0 << NAU8825_IMM_CYC_SFT)
364 #define NAU8825_IMM_CYC_2048 (0x1 << NAU8825_IMM_CYC_SFT)
365 #define NAU8825_IMM_CYC_4096 (0x2 << NAU8825_IMM_CYC_SFT)
366 #define NAU8825_IMM_CYC_8192 (0x3 << NAU8825_IMM_CYC_SFT)
367 #define NAU8825_IMM_EN (1 << 3)
368 #define NAU8825_IMM_DAC_SRC_MASK 0x7
369 #define NAU8825_IMM_DAC_SRC_BIQ 0x0
370 #define NAU8825_IMM_DAC_SRC_DRC 0x1
371 #define NAU8825_IMM_DAC_SRC_MIX 0x2
372 #define NAU8825_IMM_DAC_SRC_SIN 0x3
373
374 /* CLASSG_CTRL (0x50) */
375 #define NAU8825_CLASSG_TIMER_SFT 8
376 #define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT)
377 #define NAU8825_CLASSG_TIMER_1ms (0x1 << NAU8825_CLASSG_TIMER_SFT)
378 #define NAU8825_CLASSG_TIMER_2ms (0x2 << NAU8825_CLASSG_TIMER_SFT)
379 #define NAU8825_CLASSG_TIMER_8ms (0x4 << NAU8825_CLASSG_TIMER_SFT)
380 #define NAU8825_CLASSG_TIMER_16ms (0x8 << NAU8825_CLASSG_TIMER_SFT)
381 #define NAU8825_CLASSG_TIMER_32ms (0x10 << NAU8825_CLASSG_TIMER_SFT)
382 #define NAU8825_CLASSG_TIMER_64ms (0x20 << NAU8825_CLASSG_TIMER_SFT)
383 #define NAU8825_CLASSG_LDAC_EN (0x1 << 2)
384 #define NAU8825_CLASSG_RDAC_EN (0x1 << 1)
385 #define NAU8825_CLASSG_EN (1 << 0)
386
387 /* I2C_DEVICE_ID (0x58) */
388 #define NAU8825_GPIO2JD1 (1 << 7)
389 #define NAU8825_SOFTWARE_ID_MASK 0x3
390 #define NAU8825_SOFTWARE_ID_NAU8825 0x0
391 #define NAU8825_SOFTWARE_ID_NAU8825C 0x1
392
393 /* BIAS_ADJ (0x66) */
394 #define NAU8825_BIAS_HPR_IMP (1 << 15)
395 #define NAU8825_BIAS_HPL_IMP (1 << 14)
396 #define NAU8825_BIAS_TESTDAC_SFT 8
397 #define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT)
398 #define NAU8825_BIAS_TESTDACR_EN (0x2 << NAU8825_BIAS_TESTDAC_SFT)
399 #define NAU8825_BIAS_TESTDACL_EN (0x1 << NAU8825_BIAS_TESTDAC_SFT)
400 #define NAU8825_BIAS_VMID (1 << 6)
401 #define NAU8825_BIAS_VMID_SEL_SFT 4
402 #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT)
403
404 /* ANALOG_CONTROL_1 (0x69) */
405 #define NAU8825_TESTDACIN_SFT 14
406 #define NAU8825_TESTDACIN_MASK (0x3 << NAU8825_TESTDACIN_SFT)
407 #define NAU8825_TESTDACIN_HIGH (1 << NAU8825_TESTDACIN_SFT)
408 #define NAU8825_TESTDACIN_LOW (2 << NAU8825_TESTDACIN_SFT)
409 #define NAU8825_TESTDACIN_GND (3 << NAU8825_TESTDACIN_SFT)
410
411 /* ANALOG_CONTROL_2 (0x6a) */
412 #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12)
413 #define NAU8825_DAC_CAPACITOR_MSB (1 << 1)
414 #define NAU8825_DAC_CAPACITOR_LSB (1 << 0)
415
416 /* ANALOG_ADC_2 (0x72) */
417 #define NAU8825_ADC_VREFSEL_MASK (0x3 << 8)
418 #define NAU8825_ADC_VREFSEL_ANALOG (0 << 8)
419 #define NAU8825_ADC_VREFSEL_VMID (1 << 8)
420 #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8)
421 #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8)
422 #define NAU8825_POWERUP_ADCL (1 << 6)
423
424 /* RDAC (0x73) */
425 #define NAU8825_RDAC_FS_BCLK_ENB (1 << 15)
426 #define NAU8825_RDAC_EN_SFT 12
427 #define NAU8825_RDAC_EN (0x3 << NAU8825_RDAC_EN_SFT)
428 #define NAU8825_RDAC_CLK_EN_SFT 8
429 #define NAU8825_RDAC_CLK_EN (0x3 << NAU8825_RDAC_CLK_EN_SFT)
430 #define NAU8825_RDAC_CLK_DELAY_SFT 4
431 #define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT)
432 #define NAU8825_RDAC_VREF_SFT 2
433 #define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT)
434
435 /* MIC_BIAS (0x74) */
436 #define NAU8825_MICBIAS_JKSLV (1 << 14)
437 #define NAU8825_MICBIAS_JKR2 (1 << 12)
438 #define NAU8825_MICBIAS_LOWNOISE_SFT 10
439 #define NAU8825_MICBIAS_LOWNOISE_MASK (0x1 << NAU8825_MICBIAS_LOWNOISE_SFT)
440 #define NAU8825_MICBIAS_LOWNOISE_EN (0x1 << NAU8825_MICBIAS_LOWNOISE_SFT)
441 #define NAU8825_MICBIAS_POWERUP_SFT 8
442 #define NAU8825_MICBIAS_VOLTAGE_SFT 0
443 #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7
444
445 /* BOOST (0x76) */
446 #define NAU8825_PRECHARGE_DIS (1 << 13)
447 #define NAU8825_GLOBAL_BIAS_EN (1 << 12)
448 #define NAU8825_DISCHRG_EN (1 << 11)
449 #define NAU8825_HP_BOOST_DIS (1 << 9)
450 #define NAU8825_HP_BOOST_G_DIS (1 << 8)
451 #define NAU8825_SHORT_SHUTDOWN_EN (1 << 6)
452
453 /* FEPGA (0x77) */
454 #define NAU8825_ACDC_CTRL_SFT 14
455 #define NAU8825_ACDC_CTRL_MASK (0x3 << NAU8825_ACDC_CTRL_SFT)
456 #define NAU8825_ACDC_VREF_MICP (0x1 << NAU8825_ACDC_CTRL_SFT)
457 #define NAU8825_ACDC_VREF_MICN (0x2 << NAU8825_ACDC_CTRL_SFT)
458
459 /* POWER_UP_CONTROL (0x7f) */
460 #define NAU8825_POWERUP_INTEGR_R (1 << 5)
461 #define NAU8825_POWERUP_INTEGR_L (1 << 4)
462 #define NAU8825_POWERUP_DRV_IN_R (1 << 3)
463 #define NAU8825_POWERUP_DRV_IN_L (1 << 2)
464 #define NAU8825_POWERUP_HP_DRV_R (1 << 1)
465 #define NAU8825_POWERUP_HP_DRV_L (1 << 0)
466
467 /* CHARGE_PUMP (0x80) */
468 #define NAU8825_ADCOUT_DS_SFT 12
469 #define NAU8825_ADCOUT_DS_MASK (1 << NAU8825_ADCOUT_DS_SFT)
470 #define NAU8825_JAMNODCLOW (1 << 10)
471 #define NAU8825_POWER_DOWN_DACR (1 << 9)
472 #define NAU8825_POWER_DOWN_DACL (1 << 8)
473 #define NAU8825_CHANRGE_PUMP_EN (1 << 5)
474
475
476 /* System Clock Source */
477 enum {
478 NAU8825_CLK_DIS = 0,
479 NAU8825_CLK_MCLK,
480 NAU8825_CLK_INTERNAL,
481 NAU8825_CLK_FLL_MCLK,
482 NAU8825_CLK_FLL_BLK,
483 NAU8825_CLK_FLL_FS,
484 };
485
486 /* Cross talk detection state */
487 enum {
488 NAU8825_XTALK_PREPARE = 0,
489 NAU8825_XTALK_HPR_R2L,
490 NAU8825_XTALK_HPL_R2L,
491 NAU8825_XTALK_IMM,
492 NAU8825_XTALK_DONE,
493 };
494
495 struct nau8825 {
496 struct device *dev;
497 struct regmap *regmap;
498 struct snd_soc_dapm_context *dapm;
499 struct snd_soc_jack *jack;
500 struct clk *mclk;
501 struct work_struct xtalk_work;
502 struct semaphore xtalk_sem;
503 int sw_id;
504 int irq;
505 int mclk_freq; /* 0 - mclk is disabled */
506 int button_pressed;
507 int micbias_voltage;
508 int vref_impedance;
509 bool jkdet_enable;
510 bool jkdet_pull_enable;
511 bool jkdet_pull_up;
512 int jkdet_polarity;
513 int sar_threshold_num;
514 int sar_threshold[8];
515 int sar_hysteresis;
516 int sar_voltage;
517 int sar_compare_time;
518 int sar_sampling_time;
519 int key_debounce;
520 int jack_insert_debounce;
521 int jack_eject_debounce;
522 int high_imped;
523 int xtalk_state;
524 int xtalk_event;
525 int xtalk_event_mask;
526 bool xtalk_protect;
527 int imp_rms[NAU8825_XTALK_IMM];
528 int xtalk_enable;
529 bool xtalk_baktab_initialized; /* True if initialized. */
530 bool adcout_ds;
531 int adc_delay;
532 };
533
534 int nau8825_enable_jack_detect(struct snd_soc_component *component,
535 struct snd_soc_jack *jack);
536
537
538 #endif /* __NAU8825_H__ */
539
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