1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * rk3328 ALSA SoC Audio driver
4 *
5 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
6 */
7
8 #ifndef _RK3328_CODEC_H
9 #define _RK3328_CODEC_H
10
11 #include <linux/bitfield.h>
12
13 /* codec register */
14 #define CODEC_RESET (0x00 << 2)
15 #define DAC_INIT_CTRL1 (0x03 << 2)
16 #define DAC_INIT_CTRL2 (0x04 << 2)
17 #define DAC_INIT_CTRL3 (0x05 << 2)
18 #define DAC_PRECHARGE_CTRL (0x22 << 2)
19 #define DAC_PWR_CTRL (0x23 << 2)
20 #define DAC_CLK_CTRL (0x24 << 2)
21 #define HPMIX_CTRL (0x25 << 2)
22 #define DAC_SELECT (0x26 << 2)
23 #define HPOUT_CTRL (0x27 << 2)
24 #define HPOUTL_GAIN_CTRL (0x28 << 2)
25 #define HPOUTR_GAIN_CTRL (0x29 << 2)
26 #define HPOUT_POP_CTRL (0x2a << 2)
27
28 /* REG00: CODEC_RESET */
29 #define PWR_RST_BYPASS_DIS (0x0 << 6)
30 #define PWR_RST_BYPASS_EN (0x1 << 6)
31 #define DIG_CORE_RST (0x0 << 1)
32 #define DIG_CORE_WORK (0x1 << 1)
33 #define SYS_RST (0x0 << 0)
34 #define SYS_WORK (0x1 << 0)
35
36 /* REG03: DAC_INIT_CTRL1 */
37 #define PIN_DIRECTION_MASK BIT(5)
38 #define PIN_DIRECTION_IN (0x0 << 5)
39 #define PIN_DIRECTION_OUT (0x1 << 5)
40 #define DAC_I2S_MODE_MASK BIT(4)
41 #define DAC_I2S_MODE_SLAVE (0x0 << 4)
42 #define DAC_I2S_MODE_MASTER (0x1 << 4)
43
44 /* REG04: DAC_INIT_CTRL2 */
45 #define DAC_I2S_LRP_MASK BIT(7)
46 #define DAC_I2S_LRP_NORMAL (0x0 << 7)
47 #define DAC_I2S_LRP_REVERSAL (0x1 << 7)
48 #define DAC_VDL_MASK GENMASK(6, 5)
49 #define DAC_VDL_16BITS (0x0 << 5)
50 #define DAC_VDL_20BITS (0x1 << 5)
51 #define DAC_VDL_24BITS (0x2 << 5)
52 #define DAC_VDL_32BITS (0x3 << 5)
53 #define DAC_MODE_MASK GENMASK(4, 3)
54 #define DAC_MODE_RJM (0x0 << 3)
55 #define DAC_MODE_LJM (0x1 << 3)
56 #define DAC_MODE_I2S (0x2 << 3)
57 #define DAC_MODE_PCM (0x3 << 3)
58 #define DAC_LR_SWAP_MASK BIT(2)
59 #define DAC_LR_SWAP_DIS (0x0 << 2)
60 #define DAC_LR_SWAP_EN (0x1 << 2)
61
62 /* REG05: DAC_INIT_CTRL3 */
63 #define DAC_WL_MASK GENMASK(3, 2)
64 #define DAC_WL_16BITS (0x0 << 2)
65 #define DAC_WL_20BITS (0x1 << 2)
66 #define DAC_WL_24BITS (0x2 << 2)
67 #define DAC_WL_32BITS (0x3 << 2)
68 #define DAC_RST_MASK BIT(1)
69 #define DAC_RST_EN (0x0 << 1)
70 #define DAC_RST_DIS (0x1 << 1)
71 #define DAC_BCP_MASK BIT(0)
72 #define DAC_BCP_NORMAL (0x0 << 0)
73 #define DAC_BCP_REVERSAL (0x1 << 0)
74
75 /* REG22: DAC_PRECHARGE_CTRL */
76 #define DAC_CHARGE_XCHARGE_MASK BIT(7)
77 #define DAC_CHARGE_DISCHARGE (0x0 << 7)
78 #define DAC_CHARGE_PRECHARGE (0x1 << 7)
79 #define DAC_CHARGE_CURRENT_64I_MASK BIT(6)
80 #define DAC_CHARGE_CURRENT_64I (0x1 << 6)
81 #define DAC_CHARGE_CURRENT_32I_MASK BIT(5)
82 #define DAC_CHARGE_CURRENT_32I (0x1 << 5)
83 #define DAC_CHARGE_CURRENT_16I_MASK BIT(4)
84 #define DAC_CHARGE_CURRENT_16I (0x1 << 4)
85 #define DAC_CHARGE_CURRENT_08I_MASK BIT(3)
86 #define DAC_CHARGE_CURRENT_08I (0x1 << 3)
87 #define DAC_CHARGE_CURRENT_04I_MASK BIT(2)
88 #define DAC_CHARGE_CURRENT_04I (0x1 << 2)
89 #define DAC_CHARGE_CURRENT_02I_MASK BIT(1)
90 #define DAC_CHARGE_CURRENT_02I (0x1 << 1)
91 #define DAC_CHARGE_CURRENT_I_MASK BIT(0)
92 #define DAC_CHARGE_CURRENT_I (0x1 << 0)
93 #define DAC_CHARGE_CURRENT_ALL_MASK GENMASK(6, 0)
94 #define DAC_CHARGE_CURRENT_ALL_OFF 0x00
95 #define DAC_CHARGE_CURRENT_ALL_ON 0x7f
96
97 /* REG23: DAC_PWR_CTRL */
98 #define DAC_PWR_MASK BIT(6)
99 #define DAC_PWR_OFF (0x0 << 6)
100 #define DAC_PWR_ON (0x1 << 6)
101 #define DACL_PATH_REFV_MASK BIT(5)
102 #define DACL_PATH_REFV_OFF (0x0 << 5)
103 #define DACL_PATH_REFV_ON (0x1 << 5)
104 #define HPOUTL_ZERO_CROSSING_MASK BIT(4)
105 #define HPOUTL_ZERO_CROSSING_OFF (0x0 << 4)
106 #define HPOUTL_ZERO_CROSSING_ON (0x1 << 4)
107 #define DACR_PATH_REFV_MASK BIT(1)
108 #define DACR_PATH_REFV_OFF (0x0 << 1)
109 #define DACR_PATH_REFV_ON (0x1 << 1)
110 #define HPOUTR_ZERO_CROSSING_MASK BIT(0)
111 #define HPOUTR_ZERO_CROSSING_OFF (0x0 << 0)
112 #define HPOUTR_ZERO_CROSSING_ON (0x1 << 0)
113
114 /* REG24: DAC_CLK_CTRL */
115 #define DACL_REFV_MASK BIT(7)
116 #define DACL_REFV_OFF (0x0 << 7)
117 #define DACL_REFV_ON (0x1 << 7)
118 #define DACL_CLK_MASK BIT(6)
119 #define DACL_CLK_OFF (0x0 << 6)
120 #define DACL_CLK_ON (0x1 << 6)
121 #define DACL_MASK BIT(5)
122 #define DACL_OFF (0x0 << 5)
123 #define DACL_ON (0x1 << 5)
124 #define DACL_INIT_MASK BIT(4)
125 #define DACL_INIT_OFF (0x0 << 4)
126 #define DACL_INIT_ON (0x1 << 4)
127 #define DACR_REFV_MASK BIT(3)
128 #define DACR_REFV_OFF (0x0 << 3)
129 #define DACR_REFV_ON (0x1 << 3)
130 #define DACR_CLK_MASK BIT(2)
131 #define DACR_CLK_OFF (0x0 << 2)
132 #define DACR_CLK_ON (0x1 << 2)
133 #define DACR_MASK BIT(1)
134 #define DACR_OFF (0x0 << 1)
135 #define DACR_ON (0x1 << 1)
136 #define DACR_INIT_MASK BIT(0)
137 #define DACR_INIT_OFF (0x0 << 0)
138 #define DACR_INIT_ON (0x1 << 0)
139
140 /* REG25: HPMIX_CTRL*/
141 #define HPMIXL_MASK BIT(6)
142 #define HPMIXL_DIS (0x0 << 6)
143 #define HPMIXL_EN (0x1 << 6)
144 #define HPMIXL_INIT_MASK BIT(5)
145 #define HPMIXL_INIT_DIS (0x0 << 5)
146 #define HPMIXL_INIT_EN (0x1 << 5)
147 #define HPMIXL_INIT2_MASK BIT(4)
148 #define HPMIXL_INIT2_DIS (0x0 << 4)
149 #define HPMIXL_INIT2_EN (0x1 << 4)
150 #define HPMIXR_MASK BIT(2)
151 #define HPMIXR_DIS (0x0 << 2)
152 #define HPMIXR_EN (0x1 << 2)
153 #define HPMIXR_INIT_MASK BIT(1)
154 #define HPMIXR_INIT_DIS (0x0 << 1)
155 #define HPMIXR_INIT_EN (0x1 << 1)
156 #define HPMIXR_INIT2_MASK BIT(0)
157 #define HPMIXR_INIT2_DIS (0x0 << 0)
158 #define HPMIXR_INIT2_EN (0x1 << 0)
159
160 /* REG26: DAC_SELECT */
161 #define DACL_SELECT_MASK BIT(4)
162 #define DACL_UNSELECT (0x0 << 4)
163 #define DACL_SELECT (0x1 << 4)
164 #define DACR_SELECT_MASK BIT(0)
165 #define DACR_UNSELECT (0x0 << 0)
166 #define DACR_SELECT (0x1 << 0)
167
168 /* REG27: HPOUT_CTRL */
169 #define HPOUTL_MASK BIT(7)
170 #define HPOUTL_DIS (0x0 << 7)
171 #define HPOUTL_EN (0x1 << 7)
172 #define HPOUTL_INIT_MASK BIT(6)
173 #define HPOUTL_INIT_DIS (0x0 << 6)
174 #define HPOUTL_INIT_EN (0x1 << 6)
175 #define HPOUTL_MUTE_MASK BIT(5)
176 #define HPOUTL_MUTE (0x0 << 5)
177 #define HPOUTL_UNMUTE (0x1 << 5)
178 #define HPOUTR_MASK BIT(4)
179 #define HPOUTR_DIS (0x0 << 4)
180 #define HPOUTR_EN (0x1 << 4)
181 #define HPOUTR_INIT_MASK BIT(3)
182 #define HPOUTR_INIT_DIS (0x0 << 3)
183 #define HPOUTR_INIT_EN (0x1 << 3)
184 #define HPOUTR_MUTE_MASK BIT(2)
185 #define HPOUTR_MUTE (0x0 << 2)
186 #define HPOUTR_UNMUTE (0x1 << 2)
187
188 /* REG28: HPOUTL_GAIN_CTRL */
189 #define HPOUTL_GAIN_MASK GENMASK(4, 0)
190
191 /* REG29: HPOUTR_GAIN_CTRL */
192 #define HPOUTR_GAIN_MASK GENMASK(4, 0)
193
194 /* REG2a: HPOUT_POP_CTRL */
195 #define HPOUTR_POP_MASK GENMASK(5, 4)
196 #define HPOUTR_POP_XCHARGE (0x1 << 4)
197 #define HPOUTR_POP_WORK (0x2 << 4)
198 #define HPOUTL_POP_MASK GENMASK(1, 0)
199 #define HPOUTL_POP_XCHARGE (0x1 << 0)
200 #define HPOUTL_POP_WORK (0x2 << 0)
201
202 #define RK3328_HIFI 0
203
204 struct rk3328_reg_msk_val {
205 unsigned int reg;
206 unsigned int msk;
207 unsigned int val;
208 };
209
210 #endif
211
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