1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // rt1015.h -- RT1015 ALSA SoC audio amplifier driver
4 //
5 // Copyright 2019 Realtek Semiconductor Corp.
6 // Author: Jack Yu <jack.yu@realtek.com>
7 //
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License version 2 as
10 // published by the Free Software Foundation.
11 //
12
13 #ifndef __RT1015_H__
14 #define __RT1015_H__
15 #include <sound/rt1015.h>
16
17 #define RT1015_DEVICE_ID_VAL 0x1011
18 #define RT1015_DEVICE_ID_VAL2 0x1015
19
20 #define RT1015_RESET 0x0000
21 #define RT1015_CLK2 0x0004
22 #define RT1015_CLK3 0x0006
23 #define RT1015_PLL1 0x000a
24 #define RT1015_PLL2 0x000c
25 #define RT1015_DUM_RW1 0x000e
26 #define RT1015_DUM_RW2 0x0010
27 #define RT1015_DUM_RW3 0x0012
28 #define RT1015_DUM_RW4 0x0014
29 #define RT1015_DUM_RW5 0x0016
30 #define RT1015_DUM_RW6 0x0018
31 #define RT1015_CLK_DET 0x0020
32 #define RT1015_SIL_DET 0x0022
33 #define RT1015_CUSTOMER_ID 0x0076
34 #define RT1015_PCODE_FWVER 0x0078
35 #define RT1015_VER_ID 0x007a
36 #define RT1015_VENDOR_ID 0x007c
37 #define RT1015_DEVICE_ID 0x007d
38 #define RT1015_PAD_DRV1 0x00f0
39 #define RT1015_PAD_DRV2 0x00f2
40 #define RT1015_GAT_BOOST 0x00f3
41 #define RT1015_PRO_ALT 0x00f4
42 #define RT1015_OSCK_STA 0x00f6
43 #define RT1015_MAN_I2C 0x0100
44 #define RT1015_DAC1 0x0102
45 #define RT1015_DAC2 0x0104
46 #define RT1015_DAC3 0x0106
47 #define RT1015_ADC1 0x010c
48 #define RT1015_ADC2 0x010e
49 #define RT1015_TDM_MASTER 0x0111
50 #define RT1015_TDM_TCON 0x0112
51 #define RT1015_TDM1_1 0x0114
52 #define RT1015_TDM1_2 0x0116
53 #define RT1015_TDM1_3 0x0118
54 #define RT1015_TDM1_4 0x011a
55 #define RT1015_TDM1_5 0x011c
56 #define RT1015_MIXER1 0x0300
57 #define RT1015_MIXER2 0x0302
58 #define RT1015_ANA_PROTECT1 0x0311
59 #define RT1015_ANA_CTRL_SEQ1 0x0313
60 #define RT1015_ANA_CTRL_SEQ2 0x0314
61 #define RT1015_VBAT_DET_DEB 0x031a
62 #define RT1015_VBAT_VOLT_DET1 0x031c
63 #define RT1015_VBAT_VOLT_DET2 0x031d
64 #define RT1015_VBAT_TEST_OUT1 0x031e
65 #define RT1015_VBAT_TEST_OUT2 0x031f
66 #define RT1015_VBAT_PROT_ATT 0x0320
67 #define RT1015_VBAT_DET_CODE 0x0321
68 #define RT1015_PWR1 0x0322
69 #define RT1015_PWR4 0x0328
70 #define RT1015_PWR5 0x0329
71 #define RT1015_PWR6 0x032a
72 #define RT1015_PWR7 0x032b
73 #define RT1015_PWR8 0x032c
74 #define RT1015_PWR9 0x032d
75 #define RT1015_CLASSD_SEQ 0x032e
76 #define RT1015_SMART_BST_CTRL1 0x0330
77 #define RT1015_SMART_BST_CTRL2 0x0332
78 #define RT1015_ANA_CTRL1 0x0334
79 #define RT1015_ANA_CTRL2 0x0336
80 #define RT1015_PWR_STATE_CTRL 0x0338
81 #define RT1015_MONO_DYNA_CTRL 0x04fa
82 #define RT1015_MONO_DYNA_CTRL1 0x04fc
83 #define RT1015_MONO_DYNA_CTRL2 0x04fe
84 #define RT1015_MONO_DYNA_CTRL3 0x0500
85 #define RT1015_MONO_DYNA_CTRL4 0x0502
86 #define RT1015_MONO_DYNA_CTRL5 0x0504
87 #define RT1015_SPK_VOL 0x0506
88 #define RT1015_SHORT_DETTOP1 0x0508
89 #define RT1015_SHORT_DETTOP2 0x050a
90 #define RT1015_SPK_DC_DETECT1 0x0519
91 #define RT1015_SPK_DC_DETECT2 0x051a
92 #define RT1015_SPK_DC_DETECT3 0x051b
93 #define RT1015_SPK_DC_DETECT4 0x051d
94 #define RT1015_SPK_DC_DETECT5 0x051f
95 #define RT1015_BAT_RPO_STEP1 0x0536
96 #define RT1015_BAT_RPO_STEP2 0x0538
97 #define RT1015_BAT_RPO_STEP3 0x053a
98 #define RT1015_BAT_RPO_STEP4 0x053c
99 #define RT1015_BAT_RPO_STEP5 0x053d
100 #define RT1015_BAT_RPO_STEP6 0x053e
101 #define RT1015_BAT_RPO_STEP7 0x053f
102 #define RT1015_BAT_RPO_STEP8 0x0540
103 #define RT1015_BAT_RPO_STEP9 0x0541
104 #define RT1015_BAT_RPO_STEP10 0x0542
105 #define RT1015_BAT_RPO_STEP11 0x0543
106 #define RT1015_BAT_RPO_STEP12 0x0544
107 #define RT1015_SPREAD_SPEC1 0x0568
108 #define RT1015_SPREAD_SPEC2 0x056a
109 #define RT1015_PAD_STATUS 0x1000
110 #define RT1015_PADS_PULLING_CTRL1 0x1002
111 #define RT1015_PADS_DRIVING 0x1006
112 #define RT1015_SYS_RST1 0x1007
113 #define RT1015_SYS_RST2 0x1009
114 #define RT1015_SYS_GATING1 0x100a
115 #define RT1015_TEST_MODE1 0x100c
116 #define RT1015_TEST_MODE2 0x100d
117 #define RT1015_TIMING_CTRL1 0x100e
118 #define RT1015_PLL_INT 0x1010
119 #define RT1015_TEST_OUT1 0x1020
120 #define RT1015_DC_CALIB_CLSD1 0x1200
121 #define RT1015_DC_CALIB_CLSD2 0x1202
122 #define RT1015_DC_CALIB_CLSD3 0x1204
123 #define RT1015_DC_CALIB_CLSD4 0x1206
124 #define RT1015_DC_CALIB_CLSD5 0x1208
125 #define RT1015_DC_CALIB_CLSD6 0x120a
126 #define RT1015_DC_CALIB_CLSD7 0x120c
127 #define RT1015_DC_CALIB_CLSD8 0x120e
128 #define RT1015_DC_CALIB_CLSD9 0x1210
129 #define RT1015_DC_CALIB_CLSD10 0x1212
130 #define RT1015_CLSD_INTERNAL1 0x1300
131 #define RT1015_CLSD_INTERNAL2 0x1302
132 #define RT1015_CLSD_INTERNAL3 0x1304
133 #define RT1015_CLSD_INTERNAL4 0x1305
134 #define RT1015_CLSD_INTERNAL5 0x1306
135 #define RT1015_CLSD_INTERNAL6 0x1308
136 #define RT1015_CLSD_INTERNAL7 0x130a
137 #define RT1015_CLSD_INTERNAL8 0x130c
138 #define RT1015_CLSD_INTERNAL9 0x130e
139 #define RT1015_CLSD_OCP_CTRL 0x130f
140 #define RT1015_VREF_LV 0x1310
141 #define RT1015_MBIAS1 0x1312
142 #define RT1015_MBIAS2 0x1314
143 #define RT1015_MBIAS3 0x1316
144 #define RT1015_MBIAS4 0x1318
145 #define RT1015_VREF_LV1 0x131a
146 #define RT1015_S_BST_TIMING_INTER1 0x1322
147 #define RT1015_S_BST_TIMING_INTER2 0x1323
148 #define RT1015_S_BST_TIMING_INTER3 0x1324
149 #define RT1015_S_BST_TIMING_INTER4 0x1325
150 #define RT1015_S_BST_TIMING_INTER5 0x1326
151 #define RT1015_S_BST_TIMING_INTER6 0x1327
152 #define RT1015_S_BST_TIMING_INTER7 0x1328
153 #define RT1015_S_BST_TIMING_INTER8 0x1329
154 #define RT1015_S_BST_TIMING_INTER9 0x132a
155 #define RT1015_S_BST_TIMING_INTER10 0x132b
156 #define RT1015_S_BST_TIMING_INTER11 0x1330
157 #define RT1015_S_BST_TIMING_INTER12 0x1331
158 #define RT1015_S_BST_TIMING_INTER13 0x1332
159 #define RT1015_S_BST_TIMING_INTER14 0x1333
160 #define RT1015_S_BST_TIMING_INTER15 0x1334
161 #define RT1015_S_BST_TIMING_INTER16 0x1335
162 #define RT1015_S_BST_TIMING_INTER17 0x1336
163 #define RT1015_S_BST_TIMING_INTER18 0x1337
164 #define RT1015_S_BST_TIMING_INTER19 0x1338
165 #define RT1015_S_BST_TIMING_INTER20 0x1339
166 #define RT1015_S_BST_TIMING_INTER21 0x133a
167 #define RT1015_S_BST_TIMING_INTER22 0x133b
168 #define RT1015_S_BST_TIMING_INTER23 0x133c
169 #define RT1015_S_BST_TIMING_INTER24 0x133d
170 #define RT1015_S_BST_TIMING_INTER25 0x133e
171 #define RT1015_S_BST_TIMING_INTER26 0x133f
172 #define RT1015_S_BST_TIMING_INTER27 0x1340
173 #define RT1015_S_BST_TIMING_INTER28 0x1341
174 #define RT1015_S_BST_TIMING_INTER29 0x1342
175 #define RT1015_S_BST_TIMING_INTER30 0x1343
176 #define RT1015_S_BST_TIMING_INTER31 0x1344
177 #define RT1015_S_BST_TIMING_INTER32 0x1345
178 #define RT1015_S_BST_TIMING_INTER33 0x1346
179 #define RT1015_S_BST_TIMING_INTER34 0x1347
180 #define RT1015_S_BST_TIMING_INTER35 0x1348
181 #define RT1015_S_BST_TIMING_INTER36 0x1349
182
183 /* 0x0004 */
184 #define RT1015_CLK_SYS_PRE_SEL_MASK (0x3 << 14)
185 #define RT1015_CLK_SYS_PRE_SEL_SFT 14
186 #define RT1015_CLK_SYS_PRE_SEL_MCLK (0x0 << 14)
187 #define RT1015_CLK_SYS_PRE_SEL_PLL (0x2 << 14)
188 #define RT1015_PLL_SEL_MASK (0x1 << 13)
189 #define RT1015_PLL_SEL_SFT 13
190 #define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13)
191 #define RT1015_PLL_SEL_BCLK (0x1 << 13)
192 #define RT1015_FS_PD_MASK (0x7 << 4)
193 #define RT1015_FS_PD_SFT 4
194
195 /* 0x000a */
196 #define RT1015_PLL_M_MAX 0xf
197 #define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12)
198 #define RT1015_PLL_M_SFT 12
199 #define RT1015_PLL_M_BP (0x1 << 11)
200 #define RT1015_PLL_M_BP_SFT 11
201 #define RT1015_PLL_N_MAX 0x1ff
202 #define RT1015_PLL_N_MASK (RT1015_PLL_N_MAX << 0)
203 #define RT1015_PLL_N_SFT 0
204
205 /* 0x000c */
206 #define RT1015_PLL_BPK_MASK (0x1 << 5)
207 #define RT1015_PLL_BPK (0x0 << 5)
208 #define RT1015_PLL_K_MAX 0x1f
209 #define RT1015_PLL_K_MASK (RT1015_PLL_K_MAX)
210 #define RT1015_PLL_K_SFT 0
211
212 /* 0x0020 */
213 #define RT1015_EN_BCLK_DET_MASK (0x1 << 15)
214 #define RT1015_EN_BCLK_DET (0x1 << 15)
215 #define RT1015_DIS_BCLK_DET (0x0 << 15)
216
217 /* 0x007a */
218 #define RT1015_ID_MASK 0xff
219 #define RT1015_ID_VERA 0x0
220 #define RT1015_ID_VERB 0x1
221
222 /* 0x00f2 */
223 #define RT1015_MONO_LR_SEL_MASK (0x3 << 4)
224 #define RT1015_MONO_L_CHANNEL (0x0 << 4)
225 #define RT1015_MONO_R_CHANNEL (0x1 << 4)
226 #define RT1015_MONO_LR_MIX_CHANNEL (0x2 << 4)
227
228 /* 0x0102 */
229 #define RT1015_DAC_VOL_MASK (0x7f << 9)
230 #define RT1015_DAC_VOL_SFT 9
231
232 /* 0x0104 */
233 #define RT1015_DAC_CLK (0x1 << 13)
234 #define RT1015_DAC_CLK_BIT 13
235
236 /* 0x0106 */
237 #define RT1015_DAC_MUTE_MASK (0x1 << 15)
238 #define RT1015_DA_MUTE_SFT 15
239 #define RT1015_DVOL_MUTE_FLAG_SFT 12
240
241 /* 0x0111 */
242 #define RT1015_TCON_TDM_MS_MASK (0x1 << 14)
243 #define RT1015_TCON_TDM_MS_SFT 14
244 #define RT1015_TCON_TDM_MS_S (0x0 << 14)
245 #define RT1015_TCON_TDM_MS_M (0x1 << 14)
246 #define RT1015_I2S_DL_MASK (0x7 << 8)
247 #define RT1015_I2S_DL_SFT 8
248 #define RT1015_I2S_DL_16 (0x0 << 8)
249 #define RT1015_I2S_DL_20 (0x1 << 8)
250 #define RT1015_I2S_DL_24 (0x2 << 8)
251 #define RT1015_I2S_DL_8 (0x3 << 8)
252 #define RT1015_I2S_M_DF_MASK (0x7 << 0)
253 #define RT1015_I2S_M_DF_SFT 0
254 #define RT1015_I2S_M_DF_I2S (0x0)
255 #define RT1015_I2S_M_DF_LEFT (0x1)
256 #define RT1015_I2S_M_DF_PCM_A (0x2)
257 #define RT1015_I2S_M_DF_PCM_B (0x3)
258 #define RT1015_I2S_M_DF_PCM_A_N (0x6)
259 #define RT1015_I2S_M_DF_PCM_B_N (0x7)
260
261 /* TDM_tcon Setting (0x0112) */
262 #define RT1015_I2S_TCON_DF_MASK (0x7 << 13)
263 #define RT1015_I2S_TCON_DF_SFT 13
264 #define RT1015_I2S_TCON_DF_I2S (0x0 << 13)
265 #define RT1015_I2S_TCON_DF_LEFT (0x1 << 13)
266 #define RT1015_I2S_TCON_DF_PCM_A (0x2 << 13)
267 #define RT1015_I2S_TCON_DF_PCM_B (0x3 << 13)
268 #define RT1015_I2S_TCON_DF_PCM_A_N (0x6 << 13)
269 #define RT1015_I2S_TCON_DF_PCM_B_N (0x7 << 13)
270 #define RT1015_TCON_BCLK_SEL_MASK (0x3 << 10)
271 #define RT1015_TCON_BCLK_SEL_SFT 10
272 #define RT1015_TCON_BCLK_SEL_32FS (0x0 << 10)
273 #define RT1015_TCON_BCLK_SEL_64FS (0x1 << 10)
274 #define RT1015_TCON_BCLK_SEL_128FS (0x2 << 10)
275 #define RT1015_TCON_BCLK_SEL_256FS (0x3 << 10)
276 #define RT1015_TCON_CH_LEN_MASK (0x3 << 5)
277 #define RT1015_TCON_CH_LEN_SFT 5
278 #define RT1015_TCON_CH_LEN_16B (0x0 << 5)
279 #define RT1015_TCON_CH_LEN_20B (0x1 << 5)
280 #define RT1015_TCON_CH_LEN_24B (0x2 << 5)
281 #define RT1015_TCON_CH_LEN_32B (0x3 << 5)
282 #define RT1015_TCON_BCLK_MST_MASK (0x1 << 4)
283 #define RT1015_TCON_BCLK_MST_SFT 4
284 #define RT1015_TCON_BCLK_MST_INV (0x1 << 4)
285
286 /* TDM1 Setting-1 (0x0114) */
287 #define RT1015_TDM_INV_BCLK_MASK (0x1 << 15)
288 #define RT1015_TDM_INV_BCLK_SFT 15
289 #define RT1015_TDM_INV_BCLK (0x1 << 15)
290 #define RT1015_I2S_CH_TX_MASK (0x3 << 10)
291 #define RT1015_I2S_CH_TX_SFT 10
292 #define RT1015_I2S_TX_2CH (0x0 << 10)
293 #define RT1015_I2S_TX_4CH (0x1 << 10)
294 #define RT1015_I2S_TX_6CH (0x2 << 10)
295 #define RT1015_I2S_TX_8CH (0x3 << 10)
296 #define RT1015_I2S_CH_RX_MASK (0x3 << 8)
297 #define RT1015_I2S_CH_RX_SFT 8
298 #define RT1015_I2S_RX_2CH (0x0 << 8)
299 #define RT1015_I2S_RX_4CH (0x1 << 8)
300 #define RT1015_I2S_RX_6CH (0x2 << 8)
301 #define RT1015_I2S_RX_8CH (0x3 << 8)
302 #define RT1015_I2S_LR_CH_SEL_MASK (0x1 << 7)
303 #define RT1015_I2S_LR_CH_SEL_SFT 7
304 #define RT1015_I2S_LEFT_CH_SEL (0x0 << 7)
305 #define RT1015_I2S_RIGHT_CH_SEL (0x1 << 7)
306 #define RT1015_I2S_CH_TX_LEN_MASK (0x7 << 4)
307 #define RT1015_I2S_CH_TX_LEN_SFT 4
308 #define RT1015_I2S_CH_TX_LEN_16B (0x0 << 4)
309 #define RT1015_I2S_CH_TX_LEN_20B (0x1 << 4)
310 #define RT1015_I2S_CH_TX_LEN_24B (0x2 << 4)
311 #define RT1015_I2S_CH_TX_LEN_32B (0x3 << 4)
312 #define RT1015_I2S_CH_TX_LEN_8B (0x4 << 4)
313 #define RT1015_I2S_CH_RX_LEN_MASK (0x7 << 0)
314 #define RT1015_I2S_CH_RX_LEN_SFT 0
315 #define RT1015_I2S_CH_RX_LEN_16B (0x0 << 0)
316 #define RT1015_I2S_CH_RX_LEN_20B (0x1 << 0)
317 #define RT1015_I2S_CH_RX_LEN_24B (0x2 << 0)
318 #define RT1015_I2S_CH_RX_LEN_32B (0x3 << 0)
319 #define RT1015_I2S_CH_RX_LEN_8B (0x4 << 0)
320
321 /* TDM1 Setting-4 (0x011a) */
322 #define RT1015_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 12)
323 #define RT1015_TDM_I2S_TX_R_DAC1_1_MASK (0x7 << 8)
324 #define RT1015_TDM_I2S_TX_L_DAC1_1_SFT 12
325 #define RT1015_TDM_I2S_TX_R_DAC1_1_SFT 8
326
327 /* 0x0330 */
328 #define RT1015_ABST_AUTO_EN_MASK (0x1 << 13)
329 #define RT1015_ABST_AUTO_MODE (0x1 << 13)
330 #define RT1015_ABST_REG_MODE (0x0 << 13)
331 #define RT1015_ABST_FIX_TGT_MASK (0x1 << 12)
332 #define RT1015_ABST_FIX_TGT_EN (0x1 << 12)
333 #define RT1015_ABST_FIX_TGT_DIS (0x0 << 12)
334 #define RT1015_BYPASS_SWR_REG_MASK (0x1 << 7)
335 #define RT1015_BYPASS_SWRREG_BYPASS (0x1 << 7)
336 #define RT1015_BYPASS_SWRREG_PASS (0x0 << 7)
337
338 /* 0x0322 */
339 #define RT1015_PWR_LDO2 (0x1 << 15)
340 #define RT1015_PWR_LDO2_BIT 15
341 #define RT1015_PWR_DAC (0x1 << 14)
342 #define RT1015_PWR_DAC_BIT 14
343 #define RT1015_PWR_INTCLK (0x1 << 13)
344 #define RT1015_PWR_INTCLK_BIT 13
345 #define RT1015_PWR_ISENSE (0x1 << 12)
346 #define RT1015_PWR_ISENSE_BIT 12
347 #define RT1015_PWR_VSENSE (0x1 << 10)
348 #define RT1015_PWR_VSENSE_BIT 10
349 #define RT1015_PWR_PLL (0x1 << 9)
350 #define RT1015_PWR_PLL_BIT 9
351 #define RT1015_PWR_BG_1_2 (0x1 << 8)
352 #define RT1015_PWR_BG_1_2_BIT 8
353 #define RT1015_PWR_MBIAS_BG (0x1 << 7)
354 #define RT1015_PWR_MBIAS_BG_BIT 7
355 #define RT1015_PWR_VBAT (0x1 << 6)
356 #define RT1015_PWR_VBAT_BIT 6
357 #define RT1015_PWR_MBIAS (0x1 << 4)
358 #define RT1015_PWR_MBIAS_BIT 4
359 #define RT1015_PWR_ADCV (0x1 << 3)
360 #define RT1015_PWR_ADCV_BIT 3
361 #define RT1015_PWR_MIXERV (0x1 << 2)
362 #define RT1015_PWR_MIXERV_BIT 2
363 #define RT1015_PWR_SUMV (0x1 << 1)
364 #define RT1015_PWR_SUMV_BIT 1
365 #define RT1015_PWR_VREFLV (0x1 << 0)
366 #define RT1015_PWR_VREFLV_BIT 0
367
368 /* 0x0324 */
369 #define RT1015_PWR_BASIC (0x1 << 15)
370 #define RT1015_PWR_BASIC_BIT 15
371 #define RT1015_PWR_SD (0x1 << 14)
372 #define RT1015_PWR_SD_BIT 14
373 #define RT1015_PWR_IBIAS (0x1 << 13)
374 #define RT1015_PWR_IBIAS_BIT 13
375 #define RT1015_PWR_VCM (0x1 << 11)
376 #define RT1015_PWR_VCM_BIT 11
377
378 /* 0x0328 */
379 #define RT1015_PWR_SWR (0x1 << 12)
380 #define RT1015_PWR_SWR_BIT 12
381
382 /* 0x0519 */
383 #define RT1015_EN_CLA_D_DC_DET_MASK (0x1 << 12)
384 #define RT1015_EN_CLA_D_DC_DET (0x1 << 12)
385 #define RT1015_DIS_CLA_D_DC_DET (0x0 << 12)
386
387 /* 0x1300 */
388 #define RT1015_PWR_CLSD (0x1 << 12)
389 #define RT1015_PWR_CLSD_BIT 12
390
391 /* 0x007a */
392 #define RT1015_ID_MASK 0xff
393 #define RT1015_ID_VERA 0x0
394 #define RT1015_ID_VERB 0x1
395
396 /* System Clock Source */
397 enum {
398 RT1015_SCLK_S_MCLK,
399 RT1015_SCLK_S_PLL,
400 };
401
402 /* PLL1 Source */
403 enum {
404 RT1015_PLL_S_MCLK,
405 RT1015_PLL_S_BCLK,
406 };
407
408 enum {
409 RT1015_AIF1,
410 RT1015_AIFS,
411 };
412
413 enum {
414 RT1015_VERA,
415 RT1015_VERB,
416 };
417
418 enum {
419 BYPASS,
420 ADAPTIVE,
421 FIXED_ADAPTIVE,
422 };
423
424 enum {
425 RT1015_Enable_Boost = 0,
426 RT1015_Bypass_Boost,
427 };
428
429 enum {
430 RT1015_HW_28 = 0,
431 RT1015_HW_29,
432 };
433
434 struct rt1015_priv {
435 struct snd_soc_component *component;
436 struct rt1015_platform_data pdata;
437 struct regmap *regmap;
438 int sysclk;
439 int sysclk_src;
440 int pll_src;
441 int pll_in;
442 int pll_out;
443 int boost_mode;
444 int bypass_boost;
445 int dac_is_used;
446 int cali_done;
447 };
448
449 #endif /* __RT1015_H__ */
450
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