1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // rt1308.c -- RT1308 ALSA SoC amplifier component driver
4 //
5 // Copyright 2019 Realtek Semiconductor Corp.
6 // Author: Derek Fang <derek.fang@realtek.com>
7 //
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/regmap.h>
16 #include <linux/acpi.h>
17 #include <linux/platform_device.h>
18 #include <linux/firmware.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/initval.h>
25 #include <sound/tlv.h>
26
27 #include "rl6231.h"
28 #include "rt1308.h"
29
30 static const struct reg_sequence init_list[] = {
31
32 { RT1308_I2C_I2S_SDW_SET, 0x01014005 },
33 { RT1308_CLASS_D_SET_2, 0x227f5501 },
34 { RT1308_PADS_1, 0x50150505 },
35 { RT1308_VREF, 0x18100000 },
36 { RT1308_IV_SENSE, 0x87010000 },
37 { RT1308_DUMMY_REG, 0x00000200 },
38 { RT1308_SIL_DET, 0xe1c30000 },
39 { RT1308_DC_CAL_2, 0x00ffff00 },
40 { RT1308_CLK_DET, 0x01000000 },
41 { RT1308_POWER_STATUS, 0x08800000 },
42 { RT1308_DAC_SET, 0xafaf0700 },
43
44 };
45 #define RT1308_INIT_REG_LEN ARRAY_SIZE(init_list)
46
47 struct rt1308_priv {
48 struct snd_soc_component *component;
49 struct regmap *regmap;
50
51 int sysclk;
52 int sysclk_src;
53 int lrck;
54 int bclk;
55 int master;
56
57 int pll_src;
58 int pll_in;
59 int pll_out;
60 };
61
62 static const struct reg_default rt1308_reg[] = {
63
64 { 0x01, 0x1f3f5f00 },
65 { 0x02, 0x07000000 },
66 { 0x03, 0x80003e00 },
67 { 0x04, 0x80800600 },
68 { 0x05, 0x0aaa1a0a },
69 { 0x06, 0x52000000 },
70 { 0x07, 0x00000000 },
71 { 0x08, 0x00600000 },
72 { 0x09, 0xe1030000 },
73 { 0x0a, 0x00000000 },
74 { 0x0b, 0x30000000 },
75 { 0x0c, 0x7fff7000 },
76 { 0x10, 0xffff0700 },
77 { 0x11, 0x0a000000 },
78 { 0x12, 0x60040000 },
79 { 0x13, 0x00000000 },
80 { 0x14, 0x0f300000 },
81 { 0x15, 0x00000022 },
82 { 0x16, 0x02000000 },
83 { 0x17, 0x01004045 },
84 { 0x18, 0x00000000 },
85 { 0x19, 0x00000000 },
86 { 0x1a, 0x80000000 },
87 { 0x1b, 0x10325476 },
88 { 0x1c, 0x1d1d0000 },
89 { 0x20, 0xd2101300 },
90 { 0x21, 0xf3ffff00 },
91 { 0x22, 0x00000000 },
92 { 0x23, 0x00000000 },
93 { 0x24, 0x00000000 },
94 { 0x25, 0x00000000 },
95 { 0x26, 0x00000000 },
96 { 0x27, 0x00000000 },
97 { 0x28, 0x00000000 },
98 { 0x29, 0x00000000 },
99 { 0x2a, 0x00000000 },
100 { 0x2b, 0x00000000 },
101 { 0x2c, 0x00000000 },
102 { 0x2d, 0x00000000 },
103 { 0x2e, 0x00000000 },
104 { 0x2f, 0x00000000 },
105 { 0x30, 0x01000000 },
106 { 0x31, 0x20025501 },
107 { 0x32, 0x00000000 },
108 { 0x33, 0x105a0000 },
109 { 0x34, 0x10100000 },
110 { 0x35, 0x2aaa52aa },
111 { 0x36, 0x00c00000 },
112 { 0x37, 0x20046100 },
113 { 0x50, 0x10022f00 },
114 { 0x51, 0x003c0000 },
115 { 0x54, 0x04000000 },
116 { 0x55, 0x01000000 },
117 { 0x56, 0x02000000 },
118 { 0x57, 0x02000000 },
119 { 0x58, 0x02000000 },
120 { 0x59, 0x02000000 },
121 { 0x5b, 0x02000000 },
122 { 0x5c, 0x00000000 },
123 { 0x5d, 0x00000000 },
124 { 0x5e, 0x00000000 },
125 { 0x5f, 0x00000000 },
126 { 0x60, 0x02000000 },
127 { 0x61, 0x00000000 },
128 { 0x62, 0x00000000 },
129 { 0x63, 0x00000000 },
130 { 0x64, 0x00000000 },
131 { 0x65, 0x02000000 },
132 { 0x66, 0x00000000 },
133 { 0x67, 0x00000000 },
134 { 0x68, 0x00000000 },
135 { 0x69, 0x00000000 },
136 { 0x6a, 0x02000000 },
137 { 0x6c, 0x00000000 },
138 { 0x6d, 0x00000000 },
139 { 0x6e, 0x00000000 },
140 { 0x70, 0x10EC1308 },
141 { 0x71, 0x00000000 },
142 { 0x72, 0x00000000 },
143 { 0x73, 0x00000000 },
144 { 0x74, 0x00000000 },
145 { 0x75, 0x00000000 },
146 { 0x76, 0x00000000 },
147 { 0x77, 0x00000000 },
148 { 0x78, 0x00000000 },
149 { 0x79, 0x00000000 },
150 { 0x7a, 0x00000000 },
151 { 0x7b, 0x00000000 },
152 { 0x7c, 0x00000000 },
153 { 0x7d, 0x00000000 },
154 { 0x7e, 0x00000000 },
155 { 0x7f, 0x00020f00 },
156 { 0x80, 0x00000000 },
157 { 0x81, 0x00000000 },
158 { 0x82, 0x00000000 },
159 { 0x83, 0x00000000 },
160 { 0x84, 0x00000000 },
161 { 0x85, 0x00000000 },
162 { 0x86, 0x00000000 },
163 { 0x87, 0x00000000 },
164 { 0x88, 0x00000000 },
165 { 0x89, 0x00000000 },
166 { 0x8a, 0x00000000 },
167 { 0x8b, 0x00000000 },
168 { 0x8c, 0x00000000 },
169 { 0x8d, 0x00000000 },
170 { 0x8e, 0x00000000 },
171 { 0x90, 0x50250905 },
172 { 0x91, 0x15050000 },
173 { 0xa0, 0x00000000 },
174 { 0xa1, 0x00000000 },
175 { 0xa2, 0x00000000 },
176 { 0xa3, 0x00000000 },
177 { 0xa4, 0x00000000 },
178 { 0xb0, 0x00000000 },
179 { 0xb1, 0x00000000 },
180 { 0xb2, 0x00000000 },
181 { 0xb3, 0x00000000 },
182 { 0xb4, 0x00000000 },
183 { 0xb5, 0x00000000 },
184 { 0xb6, 0x00000000 },
185 { 0xb7, 0x00000000 },
186 { 0xb8, 0x00000000 },
187 { 0xb9, 0x00000000 },
188 { 0xba, 0x00000000 },
189 { 0xbb, 0x00000000 },
190 { 0xc0, 0x01000000 },
191 { 0xc1, 0x00000000 },
192 { 0xf0, 0x00000000 },
193 };
194
195 static int rt1308_reg_init(struct snd_soc_component *component)
196 {
197 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
198
199 return regmap_multi_reg_write(rt1308->regmap, init_list,
200 RT1308_INIT_REG_LEN);
201 }
202
203 static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
204 {
205 switch (reg) {
206 case RT1308_RESET:
207 case RT1308_RESET_N:
208 case RT1308_CLK_2:
209 case RT1308_SIL_DET:
210 case RT1308_CLK_DET:
211 case RT1308_DC_DET:
212 case RT1308_DAC_SET:
213 case RT1308_DAC_BUF:
214 case RT1308_SDW_REG_RDATA:
215 case RT1308_DC_CAL_1:
216 case RT1308_PVDD_OFFSET_CTL:
217 case RT1308_CAL_OFFSET_DAC_PBTL:
218 case RT1308_CAL_OFFSET_DAC_L:
219 case RT1308_CAL_OFFSET_DAC_R:
220 case RT1308_CAL_OFFSET_PWM_L:
221 case RT1308_CAL_OFFSET_PWM_R:
222 case RT1308_CAL_PWM_VOS_ADC_L:
223 case RT1308_CAL_PWM_VOS_ADC_R:
224 case RT1308_MBIAS:
225 case RT1308_POWER_STATUS:
226 case RT1308_POWER_INT:
227 case RT1308_SINE_TONE_GEN_2:
228 case RT1308_BQ_SET:
229 case RT1308_BQ_PARA_UPDATE:
230 case RT1308_VEN_DEV_ID:
231 case RT1308_VERSION_ID:
232 case RT1308_EFUSE_1:
233 case RT1308_EFUSE_READ_PVDD_L:
234 case RT1308_EFUSE_READ_PVDD_R:
235 case RT1308_EFUSE_READ_PVDD_PTBL:
236 case RT1308_EFUSE_READ_DEV:
237 case RT1308_EFUSE_READ_R0:
238 case RT1308_EFUSE_READ_ADC_L:
239 case RT1308_EFUSE_READ_ADC_R:
240 case RT1308_EFUSE_READ_ADC_PBTL:
241 case RT1308_EFUSE_RESERVE:
242 case RT1308_EFUSE_DATA_0_MSB:
243 case RT1308_EFUSE_DATA_0_LSB:
244 case RT1308_EFUSE_DATA_1_MSB:
245 case RT1308_EFUSE_DATA_1_LSB:
246 case RT1308_EFUSE_DATA_2_MSB:
247 case RT1308_EFUSE_DATA_2_LSB:
248 case RT1308_EFUSE_DATA_3_MSB:
249 case RT1308_EFUSE_DATA_3_LSB:
250 case RT1308_EFUSE_STATUS_1:
251 case RT1308_EFUSE_STATUS_2:
252 case RT1308_DUMMY_REG:
253 return true;
254 default:
255 return false;
256 }
257 }
258
259 static bool rt1308_readable_register(struct device *dev, unsigned int reg)
260 {
261 switch (reg) {
262 case RT1308_RESET:
263 case RT1308_RESET_N:
264 case RT1308_CLK_GATING ... RT1308_DC_DET_THRES:
265 case RT1308_DAC_SET ... RT1308_AD_FILTER_SET:
266 case RT1308_DC_CAL_1 ... RT1308_POWER_INT:
267 case RT1308_SINE_TONE_GEN_1:
268 case RT1308_SINE_TONE_GEN_2:
269 case RT1308_BQ_SET:
270 case RT1308_BQ_PARA_UPDATE:
271 case RT1308_BQ_PRE_VOL_L ... RT1308_BQ_POST_VOL_R:
272 case RT1308_BQ1_L_H0 ... RT1308_BQ2_R_A2:
273 case RT1308_VEN_DEV_ID:
274 case RT1308_VERSION_ID:
275 case RT1308_SPK_BOUND:
276 case RT1308_BQ1_EQ_L_1 ... RT1308_BQ2_EQ_R_3:
277 case RT1308_EFUSE_1 ... RT1308_EFUSE_RESERVE:
278 case RT1308_PADS_1:
279 case RT1308_PADS_2:
280 case RT1308_TEST_MODE:
281 case RT1308_TEST_1:
282 case RT1308_TEST_2:
283 case RT1308_TEST_3:
284 case RT1308_TEST_4:
285 case RT1308_EFUSE_DATA_0_MSB ... RT1308_EFUSE_STATUS_2:
286 case RT1308_TCON_1:
287 case RT1308_TCON_2:
288 case RT1308_DUMMY_REG:
289 case RT1308_MAX_REG:
290 return true;
291 default:
292 return false;
293 }
294 }
295
296 static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
297 struct snd_kcontrol *kcontrol, int event)
298 {
299 struct snd_soc_component *component =
300 snd_soc_dapm_to_component(w->dapm);
301
302 switch (event) {
303 case SND_SOC_DAPM_POST_PMU:
304 msleep(30);
305 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
306 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT,
307 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT);
308 msleep(40);
309 break;
310 case SND_SOC_DAPM_PRE_PMD:
311 snd_soc_component_update_bits(component, RT1308_POWER_STATUS,
312 RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0);
313 usleep_range(150000, 200000);
314 break;
315
316 default:
317 break;
318 }
319
320 return 0;
321 }
322
323 static const char * const rt1308_rx_data_ch_select[] = {
324 "LR",
325 "LL",
326 "RL",
327 "RR",
328 };
329
330 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum, RT1308_DATA_PATH, 24,
331 rt1308_rx_data_ch_select);
332
333 static const struct snd_kcontrol_new rt1308_snd_controls[] = {
334
335 /* I2S Data Channel Selection */
336 SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
337 };
338
339 static const struct snd_kcontrol_new rt1308_sto_dac_l =
340 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
341 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
342
343 static const struct snd_kcontrol_new rt1308_sto_dac_r =
344 SOC_DAPM_SINGLE("Switch", RT1308_DAC_SET,
345 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
346
347 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
348 /* Audio Interface */
349 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
350
351 /* Supply Widgets */
352 SND_SOC_DAPM_SUPPLY("MBIAS20U", RT1308_POWER,
353 RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
354 SND_SOC_DAPM_SUPPLY("ALDO", RT1308_POWER,
355 RT1308_POW_ALDO_BIT, 0, NULL, 0),
356 SND_SOC_DAPM_SUPPLY("DBG", RT1308_POWER,
357 RT1308_POW_DBG_BIT, 0, NULL, 0),
358 SND_SOC_DAPM_SUPPLY("DACL", RT1308_POWER,
359 RT1308_POW_DACL_BIT, 0, NULL, 0),
360 SND_SOC_DAPM_SUPPLY("CLK25M", RT1308_POWER,
361 RT1308_POW_CLK25M_BIT, 0, NULL, 0),
362 SND_SOC_DAPM_SUPPLY("ADC_R", RT1308_POWER,
363 RT1308_POW_ADC_R_BIT, 0, NULL, 0),
364 SND_SOC_DAPM_SUPPLY("ADC_L", RT1308_POWER,
365 RT1308_POW_ADC_L_BIT, 0, NULL, 0),
366 SND_SOC_DAPM_SUPPLY("DLDO", RT1308_POWER,
367 RT1308_POW_DLDO_BIT, 0, NULL, 0),
368 SND_SOC_DAPM_SUPPLY("VREF", RT1308_POWER,
369 RT1308_POW_VREF_BIT, 0, NULL, 0),
370 SND_SOC_DAPM_SUPPLY("MIXER_R", RT1308_POWER,
371 RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
372 SND_SOC_DAPM_SUPPLY("MIXER_L", RT1308_POWER,
373 RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
374 SND_SOC_DAPM_SUPPLY("MBIAS4U", RT1308_POWER,
375 RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
376 SND_SOC_DAPM_SUPPLY("PLL2_LDO", RT1308_POWER,
377 RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
378 SND_SOC_DAPM_SUPPLY("PLL2B", RT1308_POWER,
379 RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
380 SND_SOC_DAPM_SUPPLY("PLL2F", RT1308_POWER,
381 RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
382 SND_SOC_DAPM_SUPPLY("PLL2F2", RT1308_POWER,
383 RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
384 SND_SOC_DAPM_SUPPLY("PLL2B2", RT1308_POWER,
385 RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
386
387 /* Digital Interface */
388 SND_SOC_DAPM_SUPPLY("DAC Power", RT1308_POWER,
389 RT1308_POW_DAC1_BIT, 0, NULL, 0),
390 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
391 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
392 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
393
394 /* Output Lines */
395 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
396 rt1308_classd_event,
397 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
398 SND_SOC_DAPM_OUTPUT("SPOL"),
399 SND_SOC_DAPM_OUTPUT("SPOR"),
400 };
401
402 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
403
404 { "DAC", NULL, "AIF1RX" },
405
406 { "DAC", NULL, "MBIAS20U" },
407 { "DAC", NULL, "ALDO" },
408 { "DAC", NULL, "DBG" },
409 { "DAC", NULL, "DACL" },
410 { "DAC", NULL, "CLK25M" },
411 { "DAC", NULL, "ADC_R" },
412 { "DAC", NULL, "ADC_L" },
413 { "DAC", NULL, "DLDO" },
414 { "DAC", NULL, "VREF" },
415 { "DAC", NULL, "MIXER_R" },
416 { "DAC", NULL, "MIXER_L" },
417 { "DAC", NULL, "MBIAS4U" },
418 { "DAC", NULL, "PLL2_LDO" },
419 { "DAC", NULL, "PLL2B" },
420 { "DAC", NULL, "PLL2F" },
421 { "DAC", NULL, "PLL2F2" },
422 { "DAC", NULL, "PLL2B2" },
423
424 { "DAC L", "Switch", "DAC" },
425 { "DAC R", "Switch", "DAC" },
426 { "DAC L", NULL, "DAC Power" },
427 { "DAC R", NULL, "DAC Power" },
428
429 { "CLASS D", NULL, "DAC L" },
430 { "CLASS D", NULL, "DAC R" },
431 { "SPOL", NULL, "CLASS D" },
432 { "SPOR", NULL, "CLASS D" },
433 };
434
435 static int rt1308_get_clk_info(int sclk, int rate)
436 {
437 int i;
438 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
439
440 if (sclk <= 0 || rate <= 0)
441 return -EINVAL;
442
443 rate = rate << 8;
444 for (i = 0; i < ARRAY_SIZE(pd); i++)
445 if (sclk == rate * pd[i])
446 return i;
447
448 return -EINVAL;
449 }
450
451 static int rt1308_hw_params(struct snd_pcm_substream *substream,
452 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
453 {
454 struct snd_soc_component *component = dai->component;
455 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
456 unsigned int val_len = 0, val_clk, mask_clk;
457 int pre_div, bclk_ms, frame_size;
458
459 rt1308->lrck = params_rate(params);
460 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck);
461 if (pre_div < 0) {
462 dev_err(component->dev,
463 "Unsupported clock setting %d\n", rt1308->lrck);
464 return -EINVAL;
465 }
466
467 frame_size = snd_soc_params_to_frame_size(params);
468 if (frame_size < 0) {
469 dev_err(component->dev, "Unsupported frame size: %d\n",
470 frame_size);
471 return -EINVAL;
472 }
473
474 bclk_ms = frame_size > 32;
475 rt1308->bclk = rt1308->lrck * (32 << bclk_ms);
476
477 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
478 bclk_ms, pre_div, dai->id);
479
480 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
481 rt1308->lrck, pre_div, dai->id);
482
483 switch (params_width(params)) {
484 case 16:
485 val_len |= RT1308_I2S_DL_SEL_16B;
486 break;
487 case 20:
488 val_len |= RT1308_I2S_DL_SEL_20B;
489 break;
490 case 24:
491 val_len |= RT1308_I2S_DL_SEL_24B;
492 break;
493 case 8:
494 val_len |= RT1308_I2S_DL_SEL_8B;
495 break;
496 default:
497 return -EINVAL;
498 }
499
500 switch (dai->id) {
501 case RT1308_AIF1:
502 mask_clk = RT1308_DIV_FS_SYS_MASK;
503 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT;
504 snd_soc_component_update_bits(component,
505 RT1308_I2S_SET_2, RT1308_I2S_DL_SEL_MASK,
506 val_len);
507 break;
508 default:
509 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
510 return -EINVAL;
511 }
512
513 snd_soc_component_update_bits(component, RT1308_CLK_1,
514 mask_clk, val_clk);
515
516 return 0;
517 }
518
519 static int rt1308_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
520 {
521 struct snd_soc_component *component = dai->component;
522 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
523 unsigned int reg_val = 0, reg1_val = 0;
524
525 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
526 case SND_SOC_DAIFMT_CBS_CFS:
527 rt1308->master = 0;
528 break;
529 default:
530 return -EINVAL;
531 }
532
533 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
534 case SND_SOC_DAIFMT_I2S:
535 break;
536 case SND_SOC_DAIFMT_LEFT_J:
537 reg_val |= RT1308_I2S_DF_SEL_LEFT;
538 break;
539 case SND_SOC_DAIFMT_DSP_A:
540 reg_val |= RT1308_I2S_DF_SEL_PCM_A;
541 break;
542 case SND_SOC_DAIFMT_DSP_B:
543 reg_val |= RT1308_I2S_DF_SEL_PCM_B;
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
550 case SND_SOC_DAIFMT_NB_NF:
551 break;
552 case SND_SOC_DAIFMT_IB_NF:
553 reg1_val |= RT1308_I2S_BCLK_INV;
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 switch (dai->id) {
560 case RT1308_AIF1:
561 snd_soc_component_update_bits(component,
562 RT1308_I2S_SET_1, RT1308_I2S_DF_SEL_MASK,
563 reg_val);
564 snd_soc_component_update_bits(component,
565 RT1308_I2S_SET_2, RT1308_I2S_BCLK_MASK,
566 reg1_val);
567 break;
568 default:
569 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
570 return -EINVAL;
571 }
572 return 0;
573 }
574
575 static int rt1308_set_component_sysclk(struct snd_soc_component *component,
576 int clk_id, int source, unsigned int freq, int dir)
577 {
578 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
579 unsigned int reg_val = 0;
580
581 if (freq == rt1308->sysclk && clk_id == rt1308->sysclk_src)
582 return 0;
583
584 switch (clk_id) {
585 case RT1308_FS_SYS_S_MCLK:
586 reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK;
587 snd_soc_component_update_bits(component,
588 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
589 RT1308_MCLK_DET_EN);
590 break;
591 case RT1308_FS_SYS_S_BCLK:
592 reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK;
593 break;
594 case RT1308_FS_SYS_S_PLL:
595 reg_val |= RT1308_SEL_FS_SYS_SRC_PLL;
596 break;
597 case RT1308_FS_SYS_S_RCCLK:
598 reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK;
599 break;
600 default:
601 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
602 return -EINVAL;
603 }
604 snd_soc_component_update_bits(component, RT1308_CLK_1,
605 RT1308_SEL_FS_SYS_MASK, reg_val);
606 rt1308->sysclk = freq;
607 rt1308->sysclk_src = clk_id;
608
609 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
610 freq, clk_id);
611
612 return 0;
613 }
614
615 static int rt1308_set_component_pll(struct snd_soc_component *component,
616 int pll_id, int source, unsigned int freq_in,
617 unsigned int freq_out)
618 {
619 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
620 struct rl6231_pll_code pll_code;
621 int ret;
622
623 if (source == rt1308->pll_src && freq_in == rt1308->pll_in &&
624 freq_out == rt1308->pll_out)
625 return 0;
626
627 if (!freq_in || !freq_out) {
628 dev_dbg(component->dev, "PLL disabled\n");
629
630 rt1308->pll_in = 0;
631 rt1308->pll_out = 0;
632 snd_soc_component_update_bits(component,
633 RT1308_CLK_1, RT1308_SEL_FS_SYS_MASK,
634 RT1308_SEL_FS_SYS_SRC_MCLK);
635 return 0;
636 }
637
638 switch (source) {
639 case RT1308_PLL_S_MCLK:
640 snd_soc_component_update_bits(component,
641 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
642 RT1308_SEL_PLL_SRC_MCLK);
643 snd_soc_component_update_bits(component,
644 RT1308_CLK_DET, RT1308_MCLK_DET_EN_MASK,
645 RT1308_MCLK_DET_EN);
646 break;
647 case RT1308_PLL_S_BCLK:
648 snd_soc_component_update_bits(component,
649 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
650 RT1308_SEL_PLL_SRC_BCLK);
651 break;
652 case RT1308_PLL_S_RCCLK:
653 snd_soc_component_update_bits(component,
654 RT1308_CLK_2, RT1308_SEL_PLL_SRC_MASK,
655 RT1308_SEL_PLL_SRC_RCCLK);
656 freq_in = 25000000;
657 break;
658 default:
659 dev_err(component->dev, "Unknown PLL Source %d\n", source);
660 return -EINVAL;
661 }
662
663 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
664 if (ret < 0) {
665 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
666 return ret;
667 }
668
669 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
670 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
671 pll_code.n_code, pll_code.k_code);
672
673 snd_soc_component_write(component, RT1308_PLL_1,
674 (pll_code.k_code << RT1308_PLL1_K_SFT) |
675 (pll_code.m_bp << RT1308_PLL1_M_BYPASS_SFT) |
676 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT) |
677 (pll_code.n_code << RT1308_PLL1_N_SFT));
678
679 rt1308->pll_in = freq_in;
680 rt1308->pll_out = freq_out;
681 rt1308->pll_src = source;
682
683 return 0;
684 }
685
686 static int rt1308_probe(struct snd_soc_component *component)
687 {
688 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
689
690 rt1308->component = component;
691
692 return rt1308_reg_init(component);
693 }
694
695 static void rt1308_remove(struct snd_soc_component *component)
696 {
697 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
698
699 regmap_write(rt1308->regmap, RT1308_RESET, 0);
700 }
701
702 #ifdef CONFIG_PM
703 static int rt1308_suspend(struct snd_soc_component *component)
704 {
705 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
706
707 regcache_cache_only(rt1308->regmap, true);
708 regcache_mark_dirty(rt1308->regmap);
709
710 return 0;
711 }
712
713 static int rt1308_resume(struct snd_soc_component *component)
714 {
715 struct rt1308_priv *rt1308 = snd_soc_component_get_drvdata(component);
716
717 regcache_cache_only(rt1308->regmap, false);
718 regcache_sync(rt1308->regmap);
719
720 return 0;
721 }
722 #else
723 #define rt1308_suspend NULL
724 #define rt1308_resume NULL
725 #endif
726
727 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
728 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
729 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
730 SNDRV_PCM_FMTBIT_S24_LE)
731
732 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
733 .hw_params = rt1308_hw_params,
734 .set_fmt = rt1308_set_dai_fmt,
735 };
736
737 static struct snd_soc_dai_driver rt1308_dai[] = {
738 {
739 .name = "rt1308-aif",
740 .playback = {
741 .stream_name = "AIF1 Playback",
742 .channels_min = 1,
743 .channels_max = 2,
744 .rates = RT1308_STEREO_RATES,
745 .formats = RT1308_FORMATS,
746 },
747 .ops = &rt1308_aif_dai_ops,
748 },
749 };
750
751 static const struct snd_soc_component_driver soc_component_dev_rt1308 = {
752 .probe = rt1308_probe,
753 .remove = rt1308_remove,
754 .suspend = rt1308_suspend,
755 .resume = rt1308_resume,
756 .controls = rt1308_snd_controls,
757 .num_controls = ARRAY_SIZE(rt1308_snd_controls),
758 .dapm_widgets = rt1308_dapm_widgets,
759 .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
760 .dapm_routes = rt1308_dapm_routes,
761 .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
762 .set_sysclk = rt1308_set_component_sysclk,
763 .set_pll = rt1308_set_component_pll,
764 .use_pmdown_time = 1,
765 .endianness = 1,
766 };
767
768 static const struct regmap_config rt1308_regmap = {
769 .reg_bits = 8,
770 .val_bits = 32,
771 .max_register = RT1308_MAX_REG,
772 .volatile_reg = rt1308_volatile_register,
773 .readable_reg = rt1308_readable_register,
774 .cache_type = REGCACHE_MAPLE,
775 .reg_defaults = rt1308_reg,
776 .num_reg_defaults = ARRAY_SIZE(rt1308_reg),
777 .use_single_read = true,
778 .use_single_write = true,
779 };
780
781 #ifdef CONFIG_OF
782 static const struct of_device_id rt1308_of_match[] = {
783 { .compatible = "realtek,rt1308", },
784 { },
785 };
786 MODULE_DEVICE_TABLE(of, rt1308_of_match);
787 #endif
788
789 #ifdef CONFIG_ACPI
790 static const struct acpi_device_id rt1308_acpi_match[] = {
791 { "10EC1308", 0, },
792 { },
793 };
794 MODULE_DEVICE_TABLE(acpi, rt1308_acpi_match);
795 #endif
796
797 static const struct i2c_device_id rt1308_i2c_id[] = {
798 { "rt1308" },
799 { }
800 };
801 MODULE_DEVICE_TABLE(i2c, rt1308_i2c_id);
802
803 static void rt1308_efuse(struct rt1308_priv *rt1308)
804 {
805 regmap_write(rt1308->regmap, RT1308_RESET, 0);
806
807 regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);
808 msleep(100);
809 regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);
810 msleep(20);
811 regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);
812 }
813
814 static int rt1308_i2c_probe(struct i2c_client *i2c)
815 {
816 struct rt1308_priv *rt1308;
817 int ret;
818 unsigned int val;
819
820 rt1308 = devm_kzalloc(&i2c->dev, sizeof(struct rt1308_priv),
821 GFP_KERNEL);
822 if (rt1308 == NULL)
823 return -ENOMEM;
824
825 i2c_set_clientdata(i2c, rt1308);
826
827 rt1308->regmap = devm_regmap_init_i2c(i2c, &rt1308_regmap);
828 if (IS_ERR(rt1308->regmap)) {
829 ret = PTR_ERR(rt1308->regmap);
830 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
831 ret);
832 return ret;
833 }
834
835 regmap_read(rt1308->regmap, RT1308_VEN_DEV_ID, &val);
836 /* ignore last byte difference */
837 if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {
838 dev_err(&i2c->dev,
839 "Device with ID register %x is not rt1308\n", val);
840 return -ENODEV;
841 }
842
843 rt1308_efuse(rt1308);
844
845 return devm_snd_soc_register_component(&i2c->dev,
846 &soc_component_dev_rt1308,
847 rt1308_dai, ARRAY_SIZE(rt1308_dai));
848 }
849
850 static void rt1308_i2c_shutdown(struct i2c_client *client)
851 {
852 struct rt1308_priv *rt1308 = i2c_get_clientdata(client);
853
854 regmap_write(rt1308->regmap, RT1308_RESET, 0);
855 }
856
857 static struct i2c_driver rt1308_i2c_driver = {
858 .driver = {
859 .name = "rt1308",
860 .of_match_table = of_match_ptr(rt1308_of_match),
861 .acpi_match_table = ACPI_PTR(rt1308_acpi_match),
862 },
863 .probe = rt1308_i2c_probe,
864 .shutdown = rt1308_i2c_shutdown,
865 .id_table = rt1308_i2c_id,
866 };
867 module_i2c_driver(rt1308_i2c_driver);
868
869 MODULE_DESCRIPTION("ASoC RT1308 amplifier driver");
870 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
871 MODULE_LICENSE("GPL v2");
872
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