1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1318.c -- RT1318 ALSA SoC audio amplifier driver
4 // Author: Jack Yu <jack.yu@realtek.com>
5 //
6 // Copyright(c) 2024 Realtek Semiconductor Corp.
7 //
8 //
9
10 #include <linux/acpi.h>
11 #include <linux/fs.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/regmap.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/gpio.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt1318.h>
30
31 #include "rt1318.h"
32
33 static struct reg_sequence init_list[] = {
34 { 0x0000C000, 0x01},
35 { 0x0000F20D, 0x00},
36 { 0x0000F212, 0x3E},
37 { 0x0000C001, 0x02},
38 { 0x0000C003, 0x22},
39 { 0x0000C004, 0x44},
40 { 0x0000C005, 0x44},
41 { 0x0000C007, 0x64},
42 { 0x0000C00E, 0xE7},
43 { 0x0000F223, 0x7F},
44 { 0x0000F224, 0xDB},
45 { 0x0000F225, 0xEE},
46 { 0x0000F226, 0x3F},
47 { 0x0000F227, 0x0F},
48 { 0x0000F21A, 0x78},
49 { 0x0000F242, 0x3C},
50 { 0x0000C120, 0x40},
51 { 0x0000C125, 0x03},
52 { 0x0000C321, 0x0A},
53 { 0x0000C200, 0xD8},
54 { 0x0000C201, 0x27},
55 { 0x0000C202, 0x0F},
56 { 0x0000C400, 0x0E},
57 { 0x0000C401, 0x43},
58 { 0x0000C402, 0xE0},
59 { 0x0000C403, 0x00},
60 { 0x0000C404, 0x4C},
61 { 0x0000C406, 0x40},
62 { 0x0000C407, 0x02},
63 { 0x0000C408, 0x3F},
64 { 0x0000C300, 0x01},
65 { 0x0000C125, 0x03},
66 { 0x0000DF00, 0x10},
67 { 0x0000F20B, 0x2A},
68 { 0x0000DF5F, 0x01},
69 { 0x0000DF60, 0xA7},
70 { 0x0000C203, 0x84},
71 { 0x0000C206, 0x78},
72 { 0x0000F10A, 0x09},
73 { 0x0000F10B, 0x4C},
74 { 0x0000F104, 0xF4},
75 { 0x0000F105, 0x03},
76 { 0x0000F109, 0xE0},
77 { 0x0000F10B, 0x5C},
78 { 0x0000F104, 0xF4},
79 { 0x0000F105, 0x04},
80 { 0x0000F109, 0x65},
81 { 0x0000F10B, 0x5C},
82 { 0x0000F104, 0xF4},
83 { 0x0000F105, 0x02},
84 { 0x0000F109, 0x30},
85 { 0x0000F10B, 0x5C},
86 { 0x0000E706, 0x0F},
87 { 0x0000E707, 0x30},
88 { 0x0000E806, 0x0F},
89 { 0x0000E807, 0x30},
90 { 0x0000CE04, 0x03},
91 { 0x0000CE05, 0x5F},
92 { 0x0000CE06, 0xA2},
93 { 0x0000CE07, 0x6B},
94 { 0x0000CF04, 0x03},
95 { 0x0000CF05, 0x5F},
96 { 0x0000CF06, 0xA2},
97 { 0x0000CF07, 0x6B},
98 { 0x0000CE60, 0xE3},
99 { 0x0000C130, 0x51},
100 { 0x0000E000, 0xA8},
101 { 0x0000F102, 0x00},
102 { 0x0000F103, 0x00},
103 { 0x0000F104, 0xF5},
104 { 0x0000F105, 0x23},
105 { 0x0000F109, 0x04},
106 { 0x0000F10A, 0x0B},
107 { 0x0000F10B, 0x4C},
108 { 0x0000F10B, 0x5C},
109 { 0x41001888, 0x00},
110 { 0x0000C121, 0x0B},
111 { 0x0000F102, 0x00},
112 { 0x0000F103, 0x00},
113 { 0x0000F104, 0xF5},
114 { 0x0000F105, 0x23},
115 { 0x0000F109, 0x00},
116 { 0x0000F10A, 0x0B},
117 { 0x0000F10B, 0x4C},
118 { 0x0000F10B, 0x5C},
119 { 0x0000F800, 0x20},
120 { 0x0000CA00, 0x80},
121 { 0x0000CA10, 0x00},
122 { 0x0000CA02, 0x78},
123 { 0x0000CA12, 0x78},
124 { 0x0000ED00, 0x90},
125 { 0x0000E604, 0x00},
126 { 0x0000DB00, 0x0C},
127 { 0x0000DD00, 0x0C},
128 { 0x0000DC19, 0x00},
129 { 0x0000DC1A, 0x6A},
130 { 0x0000DC1B, 0xAA},
131 { 0x0000DC1C, 0xAB},
132 { 0x0000DC1D, 0x00},
133 { 0x0000DC1E, 0x16},
134 { 0x0000DC1F, 0xDB},
135 { 0x0000DC20, 0x6D},
136 { 0x0000DE19, 0x00},
137 { 0x0000DE1A, 0x6A},
138 { 0x0000DE1B, 0xAA},
139 { 0x0000DE1C, 0xAB},
140 { 0x0000DE1D, 0x00},
141 { 0x0000DE1E, 0x16},
142 { 0x0000DE1F, 0xDB},
143 { 0x0000DE20, 0x6D},
144 { 0x0000DB32, 0x00},
145 { 0x0000DD32, 0x00},
146 { 0x0000DB33, 0x0A},
147 { 0x0000DD33, 0x0A},
148 { 0x0000DB34, 0x1A},
149 { 0x0000DD34, 0x1A},
150 { 0x0000DB15, 0xEF},
151 { 0x0000DD15, 0xEF},
152 { 0x0000DB17, 0xEF},
153 { 0x0000DD17, 0xEF},
154 { 0x0000DB94, 0x70},
155 { 0x0000DD94, 0x70},
156 { 0x0000DB19, 0x40},
157 { 0x0000DD19, 0x40},
158 { 0x0000DB12, 0xC0},
159 { 0x0000DD12, 0xC0},
160 { 0x0000DB00, 0x4C},
161 { 0x0000DB04, 0x05},
162 { 0x0000DB05, 0x03},
163 { 0x0000DD04, 0x05},
164 { 0x0000DD05, 0x03},
165 { 0x0000DBBB, 0x09},
166 { 0x0000DBBC, 0x30},
167 { 0x0000DBBD, 0xF0},
168 { 0x0000DBBE, 0xF1},
169 { 0x0000DDBB, 0x09},
170 { 0x0000DDBC, 0x30},
171 { 0x0000DDBD, 0xF0},
172 { 0x0000DDBE, 0xF1},
173 { 0x0000DB01, 0x79},
174 { 0x0000DD01, 0x79},
175 { 0x0000DB08, 0x40},
176 { 0x0000DD08, 0x40},
177 { 0x0000DC52, 0xEF},
178 { 0x0000DE52, 0xEF},
179 { 0x0000DB00, 0xCC},
180 { 0x0000CC2C, 0x00},
181 { 0x0000CC2D, 0x2A},
182 { 0x0000CC2E, 0x83},
183 { 0x0000CC2F, 0xA8},
184 { 0x0000CD2C, 0x00},
185 { 0x0000CD2D, 0x2A},
186 { 0x0000CD2E, 0x83},
187 { 0x0000CD2F, 0xA8},
188 { 0x0000CC24, 0x00},
189 { 0x0000CC25, 0x51},
190 { 0x0000CC26, 0xEB},
191 { 0x0000CC27, 0x85},
192 { 0x0000CD24, 0x00},
193 { 0x0000CD25, 0x51},
194 { 0x0000CD26, 0xEB},
195 { 0x0000CD27, 0x85},
196 { 0x0000CC20, 0x00},
197 { 0x0000CC21, 0x00},
198 { 0x0000CC22, 0x43},
199 { 0x0000CD20, 0x00},
200 { 0x0000CD21, 0x00},
201 { 0x0000CD22, 0x43},
202 { 0x0000CC16, 0x0F},
203 { 0x0000CC17, 0x00},
204 { 0x0000CD16, 0x0F},
205 { 0x0000CD17, 0x00},
206 { 0x0000CC29, 0x5D},
207 { 0x0000CC2A, 0xC0},
208 { 0x0000CD29, 0x5D},
209 { 0x0000CD2A, 0xC0},
210 { 0x0000CC31, 0x20},
211 { 0x0000CC32, 0x00},
212 { 0x0000CC33, 0x00},
213 { 0x0000CC34, 0x00},
214 { 0x0000CD31, 0x20},
215 { 0x0000CD32, 0x00},
216 { 0x0000CD33, 0x00},
217 { 0x0000CD34, 0x00},
218 { 0x0000CC36, 0x79},
219 { 0x0000CC37, 0x99},
220 { 0x0000CC38, 0x99},
221 { 0x0000CC39, 0x99},
222 { 0x0000CD36, 0x79},
223 { 0x0000CD37, 0x99},
224 { 0x0000CD38, 0x99},
225 { 0x0000CD39, 0x99},
226 { 0x0000CC09, 0x00},
227 { 0x0000CC0A, 0x07},
228 { 0x0000CC0B, 0x5F},
229 { 0x0000CC0C, 0x6F},
230 { 0x0000CD09, 0x00},
231 { 0x0000CD0A, 0x07},
232 { 0x0000CD0B, 0x5F},
233 { 0x0000CD0C, 0x6F},
234 { 0x0000CC0E, 0x00},
235 { 0x0000CC0F, 0x03},
236 { 0x0000CC10, 0xAF},
237 { 0x0000CC11, 0xB7},
238 { 0x0000CD0E, 0x00},
239 { 0x0000CD0F, 0x03},
240 { 0x0000CD10, 0xAF},
241 { 0x0000CD11, 0xB7},
242 { 0x0000CCD6, 0x00},
243 { 0x0000CCD7, 0x03},
244 { 0x0000CDD6, 0x00},
245 { 0x0000CDD7, 0x03},
246 { 0x0000CCD8, 0x00},
247 { 0x0000CCD9, 0x03},
248 { 0x0000CDD8, 0x00},
249 { 0x0000CDD9, 0x03},
250 { 0x0000CCDA, 0x00},
251 { 0x0000CCDB, 0x03},
252 { 0x0000CDDA, 0x00},
253 { 0x0000CDDB, 0x03},
254 { 0x0000C320, 0x20},
255 { 0x0000C203, 0x9C},
256 };
257 #define rt1318_INIT_REG_LEN ARRAY_SIZE(init_list)
258
259 static const struct reg_default rt1318_reg[] = {
260 { 0xc000, 0x00 },
261 { 0xc001, 0x43 },
262 { 0xc003, 0x22 },
263 { 0xc004, 0x44 },
264 { 0xc005, 0x44 },
265 { 0xc006, 0x33 },
266 { 0xc007, 0x64 },
267 { 0xc008, 0x05 },
268 { 0xc00a, 0xfc },
269 { 0xc00b, 0x0f },
270 { 0xc00c, 0x0e },
271 { 0xc00d, 0xef },
272 { 0xc00e, 0xe5 },
273 { 0xc00f, 0xff },
274 { 0xc120, 0xc0 },
275 { 0xc121, 0x00 },
276 { 0xc122, 0x00 },
277 { 0xc123, 0x14 },
278 { 0xc125, 0x00 },
279 { 0xc130, 0x59 },
280 { 0xc200, 0x00 },
281 { 0xc201, 0x00 },
282 { 0xc202, 0x00 },
283 { 0xc203, 0x04 },
284 { 0xc204, 0x00 },
285 { 0xc205, 0x00 },
286 { 0xc206, 0x68 },
287 { 0xc207, 0x70 },
288 { 0xc208, 0x00 },
289 { 0xc20a, 0x00 },
290 { 0xc20b, 0x01 },
291 { 0xc20c, 0x7f },
292 { 0xc20d, 0x01 },
293 { 0xc20e, 0x7f },
294 { 0xc300, 0x00 },
295 { 0xc301, 0x00 },
296 { 0xc303, 0x80 },
297 { 0xc320, 0x00 },
298 { 0xc321, 0x09 },
299 { 0xc322, 0x02 },
300 { 0xc400, 0x00 },
301 { 0xc401, 0x00 },
302 { 0xc402, 0x00 },
303 { 0xc403, 0x00 },
304 { 0xc404, 0x00 },
305 { 0xc405, 0x00 },
306 { 0xc406, 0x00 },
307 { 0xc407, 0x00 },
308 { 0xc408, 0x00 },
309 { 0xc410, 0x04 },
310 { 0xc430, 0x00 },
311 { 0xc431, 0x00 },
312 { 0xca00, 0x10 },
313 { 0xca01, 0x00 },
314 { 0xca02, 0x0b },
315 { 0xca10, 0x10 },
316 { 0xca11, 0x00 },
317 { 0xca12, 0x0b },
318 { 0xce04, 0x08 },
319 { 0xce05, 0x00 },
320 { 0xce06, 0x00 },
321 { 0xce07, 0x00 },
322 { 0xce60, 0x63 },
323 { 0xcf04, 0x08 },
324 { 0xcf05, 0x00 },
325 { 0xcf06, 0x00 },
326 { 0xcf07, 0x00 },
327 { 0xdb00, 0x00 },
328 { 0xdb08, 0x40 },
329 { 0xdb12, 0x00 },
330 { 0xdb35, 0x00 },
331 { 0xdbb5, 0x00 },
332 { 0xdbb6, 0x40 },
333 { 0xdbb7, 0x00 },
334 { 0xdbb8, 0x00 },
335 { 0xdbc5, 0x00 },
336 { 0xdbc6, 0x00 },
337 { 0xdbc7, 0x00 },
338 { 0xdbc8, 0x00 },
339 { 0xdd08, 0x40 },
340 { 0xdd12, 0x00 },
341 { 0xdd35, 0x00 },
342 { 0xddb5, 0x00 },
343 { 0xddb6, 0x40 },
344 { 0xddb7, 0x00 },
345 { 0xddb8, 0x00 },
346 { 0xddc5, 0x00 },
347 { 0xddc6, 0x00 },
348 { 0xddc7, 0x00 },
349 { 0xddc8, 0x00 },
350 { 0xdd93, 0x00 },
351 { 0xdd94, 0x64 },
352 { 0xdf00, 0x00 },
353 { 0xdf5f, 0x00 },
354 { 0xdf60, 0x00 },
355 { 0xe000, 0x08 },
356 { 0xe300, 0xa0 },
357 { 0xe400, 0x22 },
358 { 0xe706, 0x2f },
359 { 0xe707, 0x2f },
360 { 0xe806, 0x2f },
361 { 0xe807, 0x2f },
362 { 0xea00, 0x43 },
363 { 0xed00, 0x80 },
364 { 0xed01, 0x0f },
365 { 0xed02, 0xff },
366 { 0xed03, 0x00 },
367 { 0xed04, 0x00 },
368 { 0xed05, 0x0f },
369 { 0xed06, 0xff },
370 { 0xf010, 0x10 },
371 { 0xf011, 0xec },
372 { 0xf012, 0x68 },
373 { 0xf013, 0x21 },
374 { 0xf102, 0x00 },
375 { 0xf103, 0x00 },
376 { 0xf104, 0x00 },
377 { 0xf105, 0x00 },
378 { 0xf106, 0x00 },
379 { 0xf107, 0x00 },
380 { 0xf108, 0x00 },
381 { 0xf109, 0x00 },
382 { 0xf10a, 0x03 },
383 { 0xf10b, 0x40 },
384 { 0xf20b, 0x28 },
385 { 0xf20d, 0x00 },
386 { 0xf212, 0x00 },
387 { 0xf21a, 0x00 },
388 { 0xf223, 0x40 },
389 { 0xf224, 0x00 },
390 { 0xf225, 0x00 },
391 { 0xf226, 0x00 },
392 { 0xf227, 0x00 },
393 { 0xf242, 0x0c },
394 { 0xf800, 0x00 },
395 { 0xf801, 0x12 },
396 { 0xf802, 0xe0 },
397 { 0xf803, 0x2f },
398 { 0xf804, 0x00 },
399 { 0xf805, 0x00 },
400 { 0xf806, 0x07 },
401 { 0xf807, 0xff },
402 };
403
404 static bool rt1318_volatile_register(struct device *dev, unsigned int reg)
405 {
406 switch (reg) {
407 case 0xc000:
408 case 0xc301:
409 case 0xc410:
410 case 0xc430 ... 0xc431:
411 case 0xdb06:
412 case 0xdb12:
413 case 0xdb1d ... 0xdb1f:
414 case 0xdb35:
415 case 0xdb37:
416 case 0xdb8a ... 0xdb92:
417 case 0xdbc5 ... 0xdbc8:
418 case 0xdc2b ... 0xdc49:
419 case 0xdd0b:
420 case 0xdd12:
421 case 0xdd1d ... 0xdd1f:
422 case 0xdd35:
423 case 0xdd8a ... 0xdd92:
424 case 0xddc5 ... 0xddc8:
425 case 0xde2b ... 0xde44:
426 case 0xdf4a ... 0xdf55:
427 case 0xe224 ... 0xe23b:
428 case 0xea01:
429 case 0xebc5:
430 case 0xebc8:
431 case 0xebcb ... 0xebcc:
432 case 0xed03 ... 0xed06:
433 case 0xf010 ... 0xf014:
434 return true;
435
436 default:
437 return false;
438 }
439 }
440
441 static bool rt1318_readable_register(struct device *dev, unsigned int reg)
442 {
443 switch (reg) {
444 case 0xc000 ... 0xc00f:
445 case 0xc120 ... 0xc130:
446 case 0xc200 ... 0xc20e:
447 case 0xc300 ... 0xc303:
448 case 0xc320 ... 0xc322:
449 case 0xc400 ... 0xc408:
450 case 0xc430 ... 0xc431:
451 case 0xca00 ... 0xca02:
452 case 0xca10 ... 0xca12:
453 case 0xcb00 ... 0xcb0b:
454 case 0xcc00 ... 0xcce5:
455 case 0xcd00 ... 0xcde5:
456 case 0xce00 ... 0xce6a:
457 case 0xcf00 ... 0xcf53:
458 case 0xd000 ... 0xd0cc:
459 case 0xd100 ... 0xd1b9:
460 case 0xdb00 ... 0xdc53:
461 case 0xdd00 ... 0xde53:
462 case 0xdf00 ... 0xdf6b:
463 case 0xe000:
464 case 0xe300:
465 case 0xe400:
466 case 0xe706 ... 0xe707:
467 case 0xe806 ... 0xe807:
468 case 0xea00:
469 case 0xeb00 ... 0xebcc:
470 case 0xec00 ... 0xecb9:
471 case 0xed00 ... 0xed06:
472 case 0xf010 ... 0xf014:
473 case 0xf102 ... 0xf10b:
474 case 0xf20b:
475 case 0xf20d ... 0xf242:
476 case 0xf800 ... 0xf807:
477 return true;
478 default:
479 return false;
480 }
481 }
482
483 static int rt1318_dac_event(struct snd_soc_dapm_widget *w,
484 struct snd_kcontrol *kcontrol, int event)
485 {
486 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
487 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
488
489 switch (event) {
490 case SND_SOC_DAPM_PRE_PMU:
491 regmap_update_bits(rt1318->regmap, RT1318_PWR_STA1,
492 RT1318_PDB_CTRL_MASK, RT1318_PDB_CTRL_HIGH);
493 break;
494
495 case SND_SOC_DAPM_POST_PMD:
496 regmap_update_bits(rt1318->regmap, RT1318_PWR_STA1,
497 RT1318_PDB_CTRL_MASK, RT1318_PDB_CTRL_LOW);
498 break;
499
500 default:
501 break;
502 }
503 return 0;
504 }
505
506 static int rt1318_dvol_put(struct snd_kcontrol *kcontrol,
507 struct snd_ctl_elem_value *ucontrol)
508 {
509 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
510 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
511
512 rt1318->rt1318_dvol = ucontrol->value.integer.value[0];
513
514 if (rt1318->rt1318_dvol <= RT1318_DVOL_STEP && rt1318->rt1318_dvol >= 0) {
515 regmap_write(rt1318->regmap, RT1318_DA_VOL_L_8,
516 rt1318->rt1318_dvol >> 8);
517 regmap_write(rt1318->regmap, RT1318_DA_VOL_L_1_7,
518 rt1318->rt1318_dvol & 0xff);
519 regmap_write(rt1318->regmap, RT1318_DA_VOL_R_8,
520 rt1318->rt1318_dvol >> 8);
521 regmap_write(rt1318->regmap, RT1318_DA_VOL_R_1_7,
522 rt1318->rt1318_dvol & 0xff);
523 return 1;
524 }
525
526 return 0;
527 }
528
529 static int rt1318_dvol_get(struct snd_kcontrol *kcontrol,
530 struct snd_ctl_elem_value *ucontrol)
531 {
532 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
533 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
534
535 ucontrol->value.integer.value[0] = rt1318->rt1318_dvol;
536
537 return 0;
538 }
539
540 static const struct snd_kcontrol_new rt1318_snd_controls[] = {
541 SOC_SINGLE_EXT("Amp Playback Volume", SND_SOC_NOPM, 0, 383, 0,
542 rt1318_dvol_get, rt1318_dvol_put),
543 };
544
545 static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = {
546 /* Audio Interface */
547 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
548 /* DACs */
549 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
550 rt1318_dac_event, SND_SOC_DAPM_PRE_PMU |
551 SND_SOC_DAPM_POST_PMD),
552 /* Output Lines */
553 SND_SOC_DAPM_OUTPUT("Amp"),
554 };
555
556 static const struct snd_soc_dapm_route rt1318_dapm_routes[] = {
557 {"DAC", NULL, "AIF1RX"},
558 {"Amp", NULL, "DAC"},
559 };
560
561 static int rt1318_get_clk_info(int sclk, int rate)
562 {
563 int i, pd[] = {1, 2, 4, 8, 16, 24};
564
565 if (sclk <= 0 || rate <= 0)
566 return -EINVAL;
567
568 rate = rate << 8;
569 for (i = 0; i < ARRAY_SIZE(pd); i++)
570 if (sclk == rate * pd[i])
571 return i;
572
573 return -EINVAL;
574 }
575
576 static int rt1318_clk_ip_info(struct snd_soc_component *component, int lrclk)
577 {
578 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
579
580 switch (lrclk) {
581 case RT1318_LRCLK_48000:
582 case RT1318_LRCLK_44100:
583 case RT1318_LRCLK_16000:
584 regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
585 RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
586 RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON4);
587 break;
588 case RT1318_LRCLK_96000:
589 regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
590 RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
591 RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON2);
592 break;
593 case RT1318_LRCLK_192000:
594 regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
595 RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
596 RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON1);
597 break;
598 default:
599 dev_err(component->dev, "Unsupported clock rate.\n");
600 return -EINVAL;
601 }
602
603 return 0;
604 }
605
606 static int rt1318_hw_params(struct snd_pcm_substream *substream,
607 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
608 {
609 struct snd_soc_component *component = dai->component;
610 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
611 int data_len = 0, ch_len = 0;
612 int pre_div, ret;
613
614 rt1318->lrck = params_rate(params);
615 pre_div = rt1318_get_clk_info(rt1318->sysclk, rt1318->lrck);
616 if (pre_div < 0) {
617 dev_err(component->dev, "Unsupported clock setting\n");
618 return -EINVAL;
619 }
620 ret = rt1318_clk_ip_info(component, rt1318->lrck);
621 if (ret < 0) {
622 dev_err(component->dev, "Unsupported clock setting\n");
623 return -EINVAL;
624 }
625
626 switch (params_width(params)) {
627 case 16:
628 break;
629 case 20:
630 data_len = RT1318_I2S_DL_20;
631 ch_len = RT1318_I2S_DL_20;
632 break;
633 case 24:
634 data_len = RT1318_I2S_DL_24;
635 ch_len = RT1318_I2S_DL_24;
636 break;
637 case 32:
638 data_len = RT1318_I2S_DL_32;
639 ch_len = RT1318_I2S_DL_32;
640 break;
641 case 8:
642 data_len = RT1318_I2S_DL_8;
643 ch_len = RT1318_I2S_DL_8;
644 break;
645 default:
646 return -EINVAL;
647 }
648
649 regmap_update_bits(rt1318->regmap, RT1318_CLK2,
650 RT1318_DIV_AP_MASK | RT1318_DIV_DAMOD_MASK,
651 pre_div << RT1318_DIV_AP_SFT |
652 pre_div << RT1318_DIV_DAMOD_SFT);
653 regmap_update_bits(rt1318->regmap, RT1318_CLK3,
654 RT1318_AD_STO1_MASK | RT1318_AD_STO2_MASK,
655 pre_div << RT1318_AD_STO1_SFT |
656 pre_div << RT1318_AD_STO2_SFT);
657 regmap_update_bits(rt1318->regmap, RT1318_CLK4,
658 RT1318_AD_ANA_STO1_MASK | RT1318_AD_ANA_STO2_MASK,
659 pre_div << RT1318_AD_ANA_STO1_SFT |
660 pre_div << RT1318_AD_ANA_STO2_SFT);
661 regmap_update_bits(rt1318->regmap, RT1318_CLK5,
662 RT1318_DIV_FIFO_IN_MASK | RT1318_DIV_FIFO_OUT_MASK,
663 pre_div << RT1318_DIV_FIFO_IN_SFT |
664 pre_div << RT1318_DIV_FIFO_OUT_SFT);
665 regmap_update_bits(rt1318->regmap, RT1318_CLK6,
666 RT1318_DIV_NLMS_MASK | RT1318_DIV_AD_MONO_MASK |
667 RT1318_DIV_POST_G_MASK, pre_div << RT1318_DIV_NLMS_SFT |
668 pre_div << RT1318_DIV_AD_MONO_SFT |
669 pre_div << RT1318_DIV_POST_G_SFT);
670
671 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL2,
672 RT1318_I2S_DL_MASK, data_len << RT1318_I2S_DL_SFT);
673 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL3,
674 RT1318_I2S_TX_CHL_MASK | RT1318_I2S_RX_CHL_MASK,
675 ch_len << RT1318_I2S_TX_CHL_SFT |
676 ch_len << RT1318_I2S_RX_CHL_SFT);
677
678 return 0;
679 }
680
681 static int rt1318_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
682 {
683 struct snd_soc_component *component = dai->component;
684 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
685 unsigned int reg_val = 0, reg_val2 = 0;
686
687 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
688 case SND_SOC_DAIFMT_NB_NF:
689 break;
690 case SND_SOC_DAIFMT_IB_NF:
691 reg_val2 |= RT1318_TDM_BCLK_INV;
692 break;
693 default:
694 return -EINVAL;
695 }
696
697 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
698 case SND_SOC_DAIFMT_I2S:
699 break;
700
701 case SND_SOC_DAIFMT_LEFT_J:
702 reg_val |= RT1318_FMT_LEFT_J;
703 break;
704
705 case SND_SOC_DAIFMT_DSP_A:
706 reg_val |= RT1318_FMT_PCM_A_R;
707 break;
708
709 case SND_SOC_DAIFMT_DSP_B:
710 reg_val |= RT1318_FMT_PCM_B_R;
711 break;
712
713 default:
714 return -EINVAL;
715 }
716
717 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL1,
718 RT1318_I2S_FMT_MASK, reg_val);
719 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL1,
720 RT1318_TDM_BCLK_MASK, reg_val2);
721
722 return 0;
723 }
724
725 static int rt1318_set_dai_sysclk(struct snd_soc_dai *dai,
726 int clk_id, unsigned int freq, int dir)
727 {
728 struct snd_soc_component *component = dai->component;
729 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
730 int reg_val = 0;
731
732 if (freq == rt1318->sysclk && clk_id == rt1318->sysclk_src)
733 return 0;
734
735 switch (clk_id) {
736 case RT1318_SCLK_S_BCLK:
737 reg_val |= RT1318_SYSCLK_BCLK;
738 break;
739 case RT1318_SCLK_S_SDW:
740 reg_val |= RT1318_SYSCLK_SDW;
741 break;
742 case RT1318_SCLK_S_PLL2F:
743 reg_val |= RT1318_SYSCLK_PLL2F;
744 break;
745 case RT1318_SCLK_S_PLL2B:
746 reg_val |= RT1318_SYSCLK_PLL2B;
747 break;
748 case RT1318_SCLK_S_MCLK:
749 reg_val |= RT1318_SYSCLK_MCLK;
750 break;
751 case RT1318_SCLK_S_RC0:
752 reg_val |= RT1318_SYSCLK_RC1;
753 break;
754 case RT1318_SCLK_S_RC1:
755 reg_val |= RT1318_SYSCLK_RC2;
756 break;
757 case RT1318_SCLK_S_RC2:
758 reg_val |= RT1318_SYSCLK_RC3;
759 break;
760 default:
761 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
762 return -EINVAL;
763 }
764
765 rt1318->sysclk = freq;
766 rt1318->sysclk_src = clk_id;
767 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
768 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
769 RT1318_SYSCLK_SEL_MASK, reg_val);
770
771 return 0;
772 }
773
774 static const struct pll_calc_map pll_preset_table[] = {
775 {512000, 4096000, 22, 190, 0, true, false},
776 {1024000, 4096000, 22, 94, 0, true, false},
777 {1024000, 16384000, 4, 190, 0, true, false},
778 {1411200, 11289600, 6, 62, 0, true, false},
779 {1536000, 12288000, 6, 62, 0, true, false},
780 {2822400, 11289600, 6, 62, 0, true, false},
781 {2822400, 45158400, 0, 62, 0, true, false},
782 {2822400, 49152000, 0, 62, 0, true, false},
783 {3072000, 12288000, 6, 62, 0, true, false},
784 {3072000, 24576000, 2, 62, 0, true, false},
785 {3072000, 49152000, 0, 62, 0, true, false},
786 {6144000, 24576000, 2, 94, 4, false, false},
787 {6144000, 49152000, 0, 30, 0, true, false},
788 {6144000, 98304000, 0, 94, 4, false, true},
789 {12288000, 49152000, 0, 62, 6, false, false},
790 };
791
792 static int rt1318_pll_calc(const unsigned int freq_in,
793 const unsigned int freq_out, struct rt1318_pll_code *pll_code)
794 {
795 int max_n = RT1318_PLL_N_MAX, max_m = RT1318_PLL_M_MAX;
796 int i, k, red, n_t, pll_out, in_t, out_t;
797 int n = 0, m = 0, m_t = 0;
798 int red_t = abs(freq_out - freq_in);
799 bool m_bypass = false, k_bypass = false;
800
801 if (RT1318_PLL_INP_MAX < freq_in || RT1318_PLL_INP_MIN > freq_in)
802 return -EINVAL;
803
804 for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
805 if (freq_in == pll_preset_table[i].pll_in &&
806 freq_out == pll_preset_table[i].pll_out) {
807 k = pll_preset_table[i].k;
808 m = pll_preset_table[i].m;
809 n = pll_preset_table[i].n;
810 m_bypass = pll_preset_table[i].m_bp;
811 k_bypass = pll_preset_table[i].k_bp;
812 goto code_find;
813 }
814 }
815
816 k = 100000000 / freq_out - 2;
817 if (k > RT1318_PLL_K_MAX)
818 k = RT1318_PLL_K_MAX;
819 if (k < 0) {
820 k = 0;
821 k_bypass = true;
822 }
823 for (n_t = 0; n_t <= max_n; n_t++) {
824 in_t = freq_in / (k_bypass ? 1 : (k + 2));
825 pll_out = freq_out / (n_t + 2);
826 if (in_t < 0)
827 continue;
828 if (in_t == pll_out) {
829 m_bypass = true;
830 n = n_t;
831 goto code_find;
832 }
833 red = abs(in_t - pll_out);
834 if (red < red_t) {
835 m_bypass = true;
836 n = n_t;
837 m = m_t;
838 if (red == 0)
839 goto code_find;
840 red_t = red;
841 }
842 for (m_t = 0; m_t <= max_m; m_t++) {
843 out_t = in_t / (m_t + 2);
844 red = abs(out_t - pll_out);
845 if (red < red_t) {
846 m_bypass = false;
847 n = n_t;
848 m = m_t;
849 if (red == 0)
850 goto code_find;
851 red_t = red;
852 }
853 }
854 }
855 pr_debug("Only get approximation about PLL\n");
856
857 code_find:
858
859 pll_code->m_bp = m_bypass;
860 pll_code->k_bp = k_bypass;
861 pll_code->m_code = m;
862 pll_code->n_code = n;
863 pll_code->k_code = k;
864 return 0;
865 }
866
867 static int rt1318_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
868 unsigned int freq_in, unsigned int freq_out)
869 {
870 struct snd_soc_component *component = dai->component;
871 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
872 struct rt1318_pll_code pll_code;
873 int ret;
874
875 if (!freq_in || !freq_out) {
876 dev_dbg(component->dev, "PLL disabled\n");
877 rt1318->pll_in = 0;
878 rt1318->pll_out = 0;
879 return 0;
880 }
881
882 if (source == rt1318->pll_src && freq_in == rt1318->pll_in &&
883 freq_out == rt1318->pll_out)
884 return 0;
885
886 switch (source) {
887 case RT1318_PLL_S_BCLK0:
888 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
889 RT1318_PLLIN_MASK, RT1318_PLLIN_BCLK0);
890 break;
891 case RT1318_PLL_S_BCLK1:
892 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
893 RT1318_PLLIN_MASK, RT1318_PLLIN_BCLK1);
894 break;
895 case RT1318_PLL_S_RC:
896 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
897 RT1318_PLLIN_MASK, RT1318_PLLIN_RC);
898 break;
899 case RT1318_PLL_S_MCLK:
900 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
901 RT1318_PLLIN_MASK, RT1318_PLLIN_MCLK);
902 break;
903 case RT1318_PLL_S_SDW_IN_PLL:
904 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
905 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW1);
906 break;
907 case RT1318_PLL_S_SDW_0:
908 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
909 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW2);
910 break;
911 case RT1318_PLL_S_SDW_1:
912 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
913 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW3);
914 break;
915 case RT1318_PLL_S_SDW_2:
916 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
917 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW4);
918 break;
919 default:
920 dev_err(component->dev, "Unknown PLL source %d\n", source);
921 return -EINVAL;
922 }
923
924 ret = rt1318_pll_calc(freq_in, freq_out, &pll_code);
925 if (ret < 0) {
926 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
927 return ret;
928 }
929
930 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
931 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
932 pll_code.n_code, pll_code.k_code);
933
934 regmap_update_bits(rt1318->regmap, RT1318_PLL1_K,
935 RT1318_K_PLL1_MASK, pll_code.k_code);
936 regmap_update_bits(rt1318->regmap, RT1318_PLL1_M,
937 RT1318_M_PLL1_MASK, (pll_code.m_bp ? 0 : pll_code.m_code));
938 regmap_update_bits(rt1318->regmap, RT1318_PLL1_N_8,
939 RT1318_N_8_PLL1_MASK, pll_code.n_code >> 8);
940 regmap_update_bits(rt1318->regmap, RT1318_PLL1_N_7_0,
941 RT1318_N_7_0_PLL1_MASK, pll_code.n_code);
942
943 rt1318->pll_in = freq_in;
944 rt1318->pll_out = freq_out;
945 rt1318->pll_src = source;
946
947 return 0;
948 }
949
950 static int rt1318_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
951 unsigned int rx_mask, int slots, int slot_width)
952 {
953 struct snd_soc_component *component = dai->component;
954 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
955 unsigned int cn = 0, cl = 0, rx_slotnum;
956 int ret = 0, first_bit;
957
958 switch (slots) {
959 case 4:
960 cn |= RT1318_I2S_CH_TX_4CH;
961 cn |= RT1318_I2S_CH_RX_4CH;
962 break;
963 case 6:
964 cn |= RT1318_I2S_CH_TX_6CH;
965 cn |= RT1318_I2S_CH_RX_6CH;
966 break;
967 case 8:
968 cn |= RT1318_I2S_CH_TX_8CH;
969 cn |= RT1318_I2S_CH_RX_8CH;
970 break;
971 case 2:
972 break;
973 default:
974 return -EINVAL;
975 }
976
977 switch (slot_width) {
978 case 20:
979 cl |= RT1318_I2S_TX_CHL_20;
980 cl |= RT1318_I2S_RX_CHL_20;
981 break;
982 case 24:
983 cl |= RT1318_I2S_TX_CHL_24;
984 cl |= RT1318_I2S_RX_CHL_24;
985 break;
986 case 32:
987 cl |= RT1318_I2S_TX_CHL_32;
988 cl |= RT1318_I2S_RX_CHL_32;
989 break;
990 case 8:
991 cl |= RT1318_I2S_TX_CHL_8;
992 cl |= RT1318_I2S_RX_CHL_8;
993 break;
994 case 16:
995 break;
996 default:
997 return -EINVAL;
998 }
999
1000 /* Rx slot configuration */
1001 rx_slotnum = hweight_long(rx_mask);
1002 if (rx_slotnum != 1) {
1003 ret = -EINVAL;
1004 dev_err(component->dev, "too many rx slots or zero slot\n");
1005 goto _set_tdm_err_;
1006 }
1007
1008 first_bit = __ffs(rx_mask);
1009 switch (first_bit) {
1010 case 0:
1011 case 2:
1012 case 4:
1013 case 6:
1014 regmap_update_bits(rt1318->regmap,
1015 RT1318_TDM_CTRL9,
1016 RT1318_TDM_I2S_TX_L_DAC1_1_MASK |
1017 RT1318_TDM_I2S_TX_R_DAC1_1_MASK,
1018 (first_bit << RT1318_TDM_I2S_TX_L_DAC1_1_SFT) |
1019 ((first_bit + 1) << RT1318_TDM_I2S_TX_R_DAC1_1_SFT));
1020 break;
1021 case 1:
1022 case 3:
1023 case 5:
1024 case 7:
1025 regmap_update_bits(rt1318->regmap,
1026 RT1318_TDM_CTRL9,
1027 RT1318_TDM_I2S_TX_L_DAC1_1_MASK |
1028 RT1318_TDM_I2S_TX_R_DAC1_1_MASK,
1029 ((first_bit - 1) << RT1318_TDM_I2S_TX_L_DAC1_1_SFT) |
1030 (first_bit << RT1318_TDM_I2S_TX_R_DAC1_1_SFT));
1031 break;
1032 default:
1033 ret = -EINVAL;
1034 goto _set_tdm_err_;
1035 }
1036
1037 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL2,
1038 RT1318_I2S_CH_TX_MASK | RT1318_I2S_CH_RX_MASK, cn);
1039 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL3,
1040 RT1318_I2S_TX_CHL_MASK | RT1318_I2S_RX_CHL_MASK, cl);
1041
1042 _set_tdm_err_:
1043 return ret;
1044 }
1045
1046 static int rt1318_probe(struct snd_soc_component *component)
1047 {
1048 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1049
1050 rt1318->component = component;
1051
1052 schedule_work(&rt1318->cali_work);
1053 rt1318->rt1318_dvol = RT1318_DVOL_STEP;
1054
1055 return 0;
1056 }
1057
1058 static void rt1318_remove(struct snd_soc_component *component)
1059 {
1060 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1061
1062 cancel_work_sync(&rt1318->cali_work);
1063 }
1064
1065 #ifdef CONFIG_PM
1066 static int rt1318_suspend(struct snd_soc_component *component)
1067 {
1068 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1069
1070 regcache_cache_only(rt1318->regmap, true);
1071 regcache_mark_dirty(rt1318->regmap);
1072 return 0;
1073 }
1074
1075 static int rt1318_resume(struct snd_soc_component *component)
1076 {
1077 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1078
1079 regcache_cache_only(rt1318->regmap, false);
1080 regcache_sync(rt1318->regmap);
1081 return 0;
1082 }
1083 #else
1084 #define rt1318_suspend NULL
1085 #define rt1318_resume NULL
1086 #endif
1087
1088 #define RT1318_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1089 #define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1090 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1091
1092 static const struct snd_soc_dai_ops rt1318_aif_dai_ops = {
1093 .hw_params = rt1318_hw_params,
1094 .set_fmt = rt1318_set_dai_fmt,
1095 .set_sysclk = rt1318_set_dai_sysclk,
1096 .set_pll = rt1318_set_dai_pll,
1097 .set_tdm_slot = rt1318_set_tdm_slot,
1098 };
1099
1100 static struct snd_soc_dai_driver rt1318_dai[] = {
1101 {
1102 .name = "rt1318-aif",
1103 .id = 0,
1104 .playback = {
1105 .stream_name = "AIF1 Playback",
1106 .channels_min = 1,
1107 .channels_max = 2,
1108 .rates = RT1318_STEREO_RATES,
1109 .formats = RT1318_FORMATS,
1110 },
1111 .ops = &rt1318_aif_dai_ops,
1112 }
1113 };
1114
1115 static const struct snd_soc_component_driver soc_component_dev_rt1318 = {
1116 .probe = rt1318_probe,
1117 .remove = rt1318_remove,
1118 .suspend = rt1318_suspend,
1119 .resume = rt1318_resume,
1120 .controls = rt1318_snd_controls,
1121 .num_controls = ARRAY_SIZE(rt1318_snd_controls),
1122 .dapm_widgets = rt1318_dapm_widgets,
1123 .num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets),
1124 .dapm_routes = rt1318_dapm_routes,
1125 .num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes),
1126 .use_pmdown_time = 1,
1127 .endianness = 1,
1128 };
1129
1130 static const struct regmap_config rt1318_regmap = {
1131 .reg_bits = 32,
1132 .val_bits = 8,
1133 .readable_reg = rt1318_readable_register,
1134 .volatile_reg = rt1318_volatile_register,
1135 .max_register = 0x41001888,
1136 .reg_defaults = rt1318_reg,
1137 .num_reg_defaults = ARRAY_SIZE(rt1318_reg),
1138 .cache_type = REGCACHE_RBTREE,
1139 .use_single_read = true,
1140 .use_single_write = true,
1141 };
1142
1143 static const struct i2c_device_id rt1318_i2c_id[] = {
1144 { "rt1318" },
1145 { }
1146 };
1147 MODULE_DEVICE_TABLE(i2c, rt1318_i2c_id);
1148
1149 static const struct of_device_id rt1318_of_match[] = {
1150 { .compatible = "realtek,rt1318", },
1151 {},
1152 };
1153 MODULE_DEVICE_TABLE(of, rt1318_of_match);
1154
1155 #ifdef CONFIG_ACPI
1156 static const struct acpi_device_id rt1318_acpi_match[] = {
1157 { "10EC1318", 0},
1158 { },
1159 };
1160 MODULE_DEVICE_TABLE(acpi, rt1318_acpi_match);
1161 #endif
1162
1163 static int rt1318_parse_dt(struct rt1318_priv *rt1318, struct device *dev)
1164 {
1165 device_property_read_u32(dev, "realtek,r0_l",
1166 &rt1318->pdata.init_r0_l);
1167 device_property_read_u32(dev, "realtek,r0_r",
1168 &rt1318->pdata.init_r0_r);
1169
1170 return 0;
1171 }
1172
1173 static void rt1318_calibration_sequence(struct rt1318_priv *rt1318)
1174 {
1175 regmap_write(rt1318->regmap, RT1318_CLK1, 0x22);
1176 regmap_write(rt1318->regmap, RT1318_PLL1_N_7_0, 0x06);
1177 regmap_write(rt1318->regmap, RT1318_STP_TEMP_L, 0xCC);
1178 regmap_write(rt1318->regmap, RT1318_STP_SEL_L, 0x40);
1179 regmap_write(rt1318->regmap, RT1318_STP_SEL_R, 0x40);
1180 regmap_write(rt1318->regmap, RT1318_SINE_GEN0, 0x20);
1181 regmap_write(rt1318->regmap, RT1318_SPK_VOL_TH, 0x00);
1182 regmap_write(rt1318->regmap, RT1318_FEEDBACK_PATH, 0x0B);
1183 regmap_write(rt1318->regmap, RT1318_TCON, 0x1C);
1184 regmap_write(rt1318->regmap, RT1318_TCON_RELATE, 0x58);
1185 regmap_write(rt1318->regmap, RT1318_TCON_RELATE, 0x78);
1186 regmap_write(rt1318->regmap, RT1318_STP_R0_EN_L, 0xC2);
1187 }
1188
1189 static void rt1318_r0_calculate(struct rt1318_priv *rt1318)
1190 {
1191 unsigned int r0_l, r0_l_byte0, r0_l_byte1, r0_l_byte2, r0_l_byte3;
1192 unsigned int r0_r, r0_r_byte0, r0_r_byte1, r0_r_byte2, r0_r_byte3;
1193 unsigned int r0_l_integer, r0_l_factor, r0_r_integer, r0_r_factor;
1194 unsigned int format = 16777216; /* 2^24 */
1195
1196 regmap_read(rt1318->regmap, RT1318_R0_L_24, &r0_l_byte0);
1197 regmap_read(rt1318->regmap, RT1318_R0_L_23_16, &r0_l_byte1);
1198 regmap_read(rt1318->regmap, RT1318_R0_L_15_8, &r0_l_byte2);
1199 regmap_read(rt1318->regmap, RT1318_R0_L_7_0, &r0_l_byte3);
1200 r0_l = r0_l_byte0 << 24 | r0_l_byte1 << 16 | r0_l_byte2 << 8 | r0_l_byte3;
1201 r0_l_integer = format / r0_l;
1202 r0_l_factor = (format * 10) / r0_l - r0_l_integer * 10;
1203
1204 regmap_read(rt1318->regmap, RT1318_R0_R_24, &r0_r_byte0);
1205 regmap_read(rt1318->regmap, RT1318_R0_R_23_16, &r0_r_byte1);
1206 regmap_read(rt1318->regmap, RT1318_R0_R_15_8, &r0_r_byte2);
1207 regmap_read(rt1318->regmap, RT1318_R0_R_7_0, &r0_r_byte3);
1208 r0_r = r0_r_byte0 << 24 | r0_r_byte1 << 16 | r0_r_byte2 << 8 | r0_r_byte3;
1209 r0_r_integer = format / r0_r;
1210 r0_r_factor = (format * 10) / r0_r - r0_r_integer * 10;
1211
1212 dev_dbg(rt1318->component->dev, "r0_l_ch:%d.%d ohm\n", r0_l_integer, r0_l_factor);
1213 dev_dbg(rt1318->component->dev, "r0_r_ch:%d.%d ohm\n", r0_r_integer, r0_r_factor);
1214 }
1215
1216 static void rt1318_r0_restore(struct rt1318_priv *rt1318)
1217 {
1218 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_24,
1219 (rt1318->pdata.init_r0_l >> 24) & 0xff);
1220 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_23_16,
1221 (rt1318->pdata.init_r0_l >> 16) & 0xff);
1222 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_15_8,
1223 (rt1318->pdata.init_r0_l >> 8) & 0xff);
1224 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_7_0,
1225 (rt1318->pdata.init_r0_l >> 0) & 0xff);
1226 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_24,
1227 (rt1318->pdata.init_r0_r >> 24) & 0xff);
1228 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_23_16,
1229 (rt1318->pdata.init_r0_r >> 16) & 0xff);
1230 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_15_8,
1231 (rt1318->pdata.init_r0_r >> 8) & 0xff);
1232 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_7_0,
1233 (rt1318->pdata.init_r0_r >> 0) & 0xff);
1234 regmap_write(rt1318->regmap, RT1318_STP_SEL_L, 0x80);
1235 regmap_write(rt1318->regmap, RT1318_STP_SEL_R, 0x80);
1236 regmap_write(rt1318->regmap, RT1318_R0_CMP_L_FLAG, 0xc0);
1237 regmap_write(rt1318->regmap, RT1318_R0_CMP_R_FLAG, 0xc0);
1238 regmap_write(rt1318->regmap, RT1318_STP_R0_EN_L, 0xc0);
1239 regmap_write(rt1318->regmap, RT1318_STP_R0_EN_R, 0xc0);
1240 regmap_write(rt1318->regmap, RT1318_STP_TEMP_L, 0xcc);
1241 regmap_write(rt1318->regmap, RT1318_TCON, 0x9c);
1242 }
1243
1244 static int rt1318_calibrate(struct rt1318_priv *rt1318)
1245 {
1246 int chk_cnt = 30, count = 0;
1247 int val, val2;
1248
1249 regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x1);
1250 usleep_range(0, 10000);
1251 rt1318_calibration_sequence(rt1318);
1252
1253 while (count < chk_cnt) {
1254 msleep(100);
1255 regmap_read(rt1318->regmap, RT1318_R0_CMP_L_FLAG, &val);
1256 regmap_read(rt1318->regmap, RT1318_R0_CMP_R_FLAG, &val2);
1257 val = (val >> 1) & 0x1;
1258 val2 = (val2 >> 1) & 0x1;
1259 if (val & val2) {
1260 dev_dbg(rt1318->component->dev, "Calibration done.\n");
1261 break;
1262 }
1263 count++;
1264 if (count == chk_cnt) {
1265 regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x0);
1266 return RT1318_R0_CALIB_NOT_DONE;
1267 }
1268 }
1269 regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x0);
1270 regmap_read(rt1318->regmap, RT1318_R0_CMP_L_FLAG, &val);
1271 regmap_read(rt1318->regmap, RT1318_R0_CMP_R_FLAG, &val2);
1272 if ((val & 0x1) & (val2 & 0x1))
1273 return RT1318_R0_IN_RANGE;
1274 else
1275 return RT1318_R0_OUT_OF_RANGE;
1276 }
1277
1278 static void rt1318_calibration_work(struct work_struct *work)
1279 {
1280 struct rt1318_priv *rt1318 =
1281 container_of(work, struct rt1318_priv, cali_work);
1282 int ret;
1283
1284 if (rt1318->pdata.init_r0_l && rt1318->pdata.init_r0_r)
1285 rt1318_r0_restore(rt1318);
1286 else {
1287 ret = rt1318_calibrate(rt1318);
1288 if (ret == RT1318_R0_IN_RANGE)
1289 rt1318_r0_calculate(rt1318);
1290 dev_dbg(rt1318->component->dev, "Calibrate R0 result:%d\n", ret);
1291 }
1292 }
1293
1294 static int rt1318_i2c_probe(struct i2c_client *i2c)
1295 {
1296 struct rt1318_platform_data *pdata = dev_get_platdata(&i2c->dev);
1297 struct rt1318_priv *rt1318;
1298 int ret, val, val2, dev_id;
1299
1300 rt1318 = devm_kzalloc(&i2c->dev, sizeof(struct rt1318_priv),
1301 GFP_KERNEL);
1302 if (!rt1318)
1303 return -ENOMEM;
1304
1305 i2c_set_clientdata(i2c, rt1318);
1306
1307 if (pdata)
1308 rt1318->pdata = *pdata;
1309 else
1310 rt1318_parse_dt(rt1318, &i2c->dev);
1311
1312 rt1318->regmap = devm_regmap_init_i2c(i2c, &rt1318_regmap);
1313 if (IS_ERR(rt1318->regmap)) {
1314 ret = PTR_ERR(rt1318->regmap);
1315 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1316 ret);
1317 return ret;
1318 }
1319
1320 regmap_read(rt1318->regmap, RT1318_DEV_ID1, &val);
1321 regmap_read(rt1318->regmap, RT1318_DEV_ID2, &val2);
1322 dev_id = (val << 8) | val2;
1323 if (dev_id != 0x6821) {
1324 dev_err(&i2c->dev,
1325 "Device with ID register %#x is not rt1318\n",
1326 dev_id);
1327 return -ENODEV;
1328 }
1329
1330 ret = regmap_register_patch(rt1318->regmap, init_list,
1331 ARRAY_SIZE(init_list));
1332 if (ret != 0)
1333 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1334
1335 INIT_WORK(&rt1318->cali_work, rt1318_calibration_work);
1336
1337 return devm_snd_soc_register_component(&i2c->dev,
1338 &soc_component_dev_rt1318, rt1318_dai, ARRAY_SIZE(rt1318_dai));
1339 }
1340
1341 static struct i2c_driver rt1318_i2c_driver = {
1342 .driver = {
1343 .name = "rt1318",
1344 .of_match_table = of_match_ptr(rt1318_of_match),
1345 .acpi_match_table = ACPI_PTR(rt1318_acpi_match),
1346 },
1347 .probe = rt1318_i2c_probe,
1348 .id_table = rt1318_i2c_id,
1349 };
1350 module_i2c_driver(rt1318_i2c_driver);
1351
1352 MODULE_DESCRIPTION("ASoC RT1318 driver");
1353 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1354 MODULE_LICENSE("GPL");
1355
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