1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver
4 *
5 * Copyright 2018 Realtek Microelectronics
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #ifndef __RT5682_H__
10 #define __RT5682_H__
11
12 #include <sound/rt5682.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/clk-provider.h>
18 #include <linux/soundwire/sdw.h>
19 #include <linux/soundwire/sdw_type.h>
20
21 #define DEVICE_ID 0x6530
22
23 /* Info */
24 #define RT5682_RESET 0x0000
25 #define RT5682_VERSION_ID 0x00fd
26 #define RT5682_VENDOR_ID 0x00fe
27 #define RT5682_DEVICE_ID 0x00ff
28 /* I/O - Output */
29 #define RT5682_HP_CTRL_1 0x0002
30 #define RT5682_HP_CTRL_2 0x0003
31 #define RT5682_HPL_GAIN 0x0005
32 #define RT5682_HPR_GAIN 0x0006
33
34 #define RT5682_I2C_CTRL 0x0008
35
36 /* I/O - Input */
37 #define RT5682_CBJ_BST_CTRL 0x000b
38 #define RT5682_CBJ_CTRL_1 0x0010
39 #define RT5682_CBJ_CTRL_2 0x0011
40 #define RT5682_CBJ_CTRL_3 0x0012
41 #define RT5682_CBJ_CTRL_4 0x0013
42 #define RT5682_CBJ_CTRL_5 0x0014
43 #define RT5682_CBJ_CTRL_6 0x0015
44 #define RT5682_CBJ_CTRL_7 0x0016
45 /* I/O - ADC/DAC/DMIC */
46 #define RT5682_DAC1_DIG_VOL 0x0019
47 #define RT5682_STO1_ADC_DIG_VOL 0x001c
48 #define RT5682_STO1_ADC_BOOST 0x001f
49 #define RT5682_HP_IMP_GAIN_1 0x0022
50 #define RT5682_HP_IMP_GAIN_2 0x0023
51 /* Mixer - D-D */
52 #define RT5682_SIDETONE_CTRL 0x0024
53 #define RT5682_STO1_ADC_MIXER 0x0026
54 #define RT5682_AD_DA_MIXER 0x0029
55 #define RT5682_STO1_DAC_MIXER 0x002a
56 #define RT5682_A_DAC1_MUX 0x002b
57 #define RT5682_DIG_INF2_DATA 0x0030
58 /* Mixer - ADC */
59 #define RT5682_REC_MIXER 0x003c
60 #define RT5682_CAL_REC 0x0044
61 #define RT5682_ALC_BACK_GAIN 0x0049
62 /* Power */
63 #define RT5682_PWR_DIG_1 0x0061
64 #define RT5682_PWR_DIG_2 0x0062
65 #define RT5682_PWR_ANLG_1 0x0063
66 #define RT5682_PWR_ANLG_2 0x0064
67 #define RT5682_PWR_ANLG_3 0x0065
68 #define RT5682_PWR_MIXER 0x0066
69 #define RT5682_PWR_VOL 0x0067
70 /* Clock Detect */
71 #define RT5682_CLK_DET 0x006b
72 /* Filter Auto Reset */
73 #define RT5682_RESET_LPF_CTRL 0x006c
74 #define RT5682_RESET_HPF_CTRL 0x006d
75 /* DMIC */
76 #define RT5682_DMIC_CTRL_1 0x006e
77 /* Format - ADC/DAC */
78 #define RT5682_I2S1_SDP 0x0070
79 #define RT5682_I2S2_SDP 0x0071
80 #define RT5682_ADDA_CLK_1 0x0073
81 #define RT5682_ADDA_CLK_2 0x0074
82 #define RT5682_I2S1_F_DIV_CTRL_1 0x0075
83 #define RT5682_I2S1_F_DIV_CTRL_2 0x0076
84 /* Format - TDM Control */
85 #define RT5682_TDM_CTRL 0x0079
86 #define RT5682_TDM_ADDA_CTRL_1 0x007a
87 #define RT5682_TDM_ADDA_CTRL_2 0x007b
88 #define RT5682_DATA_SEL_CTRL_1 0x007c
89 #define RT5682_TDM_TCON_CTRL 0x007e
90 /* Function - Analog */
91 #define RT5682_GLB_CLK 0x0080
92 #define RT5682_PLL_CTRL_1 0x0081
93 #define RT5682_PLL_CTRL_2 0x0082
94 #define RT5682_PLL_TRACK_1 0x0083
95 #define RT5682_PLL_TRACK_2 0x0084
96 #define RT5682_PLL_TRACK_3 0x0085
97 #define RT5682_PLL_TRACK_4 0x0086
98 #define RT5682_PLL_TRACK_5 0x0087
99 #define RT5682_PLL_TRACK_6 0x0088
100 #define RT5682_PLL_TRACK_11 0x008c
101 #define RT5682_SDW_REF_CLK 0x008d
102 #define RT5682_DEPOP_1 0x008e
103 #define RT5682_DEPOP_2 0x008f
104 #define RT5682_HP_CHARGE_PUMP_1 0x0091
105 #define RT5682_HP_CHARGE_PUMP_2 0x0092
106 #define RT5682_MICBIAS_1 0x0093
107 #define RT5682_MICBIAS_2 0x0094
108 #define RT5682_PLL_TRACK_12 0x0098
109 #define RT5682_PLL_TRACK_14 0x009a
110 #define RT5682_PLL2_CTRL_1 0x009b
111 #define RT5682_PLL2_CTRL_2 0x009c
112 #define RT5682_PLL2_CTRL_3 0x009d
113 #define RT5682_PLL2_CTRL_4 0x009e
114 #define RT5682_RC_CLK_CTRL 0x009f
115 #define RT5682_I2S_M_CLK_CTRL_1 0x00a0
116 #define RT5682_I2S2_F_DIV_CTRL_1 0x00a3
117 #define RT5682_I2S2_F_DIV_CTRL_2 0x00a4
118 /* Function - Digital */
119 #define RT5682_EQ_CTRL_1 0x00ae
120 #define RT5682_EQ_CTRL_2 0x00af
121 #define RT5682_IRQ_CTRL_1 0x00b6
122 #define RT5682_IRQ_CTRL_2 0x00b7
123 #define RT5682_IRQ_CTRL_3 0x00b8
124 #define RT5682_IRQ_CTRL_4 0x00b9
125 #define RT5682_INT_ST_1 0x00be
126 #define RT5682_GPIO_CTRL_1 0x00c0
127 #define RT5682_GPIO_CTRL_2 0x00c1
128 #define RT5682_GPIO_CTRL_3 0x00c2
129 #define RT5682_HP_AMP_DET_CTRL_1 0x00d0
130 #define RT5682_HP_AMP_DET_CTRL_2 0x00d1
131 #define RT5682_MID_HP_AMP_DET 0x00d2
132 #define RT5682_LOW_HP_AMP_DET 0x00d3
133 #define RT5682_DELAY_BUF_CTRL 0x00d4
134 #define RT5682_SV_ZCD_1 0x00d9
135 #define RT5682_SV_ZCD_2 0x00da
136 #define RT5682_IL_CMD_1 0x00db
137 #define RT5682_IL_CMD_2 0x00dc
138 #define RT5682_IL_CMD_3 0x00dd
139 #define RT5682_IL_CMD_4 0x00de
140 #define RT5682_IL_CMD_5 0x00df
141 #define RT5682_IL_CMD_6 0x00e0
142 #define RT5682_4BTN_IL_CMD_1 0x00e2
143 #define RT5682_4BTN_IL_CMD_2 0x00e3
144 #define RT5682_4BTN_IL_CMD_3 0x00e4
145 #define RT5682_4BTN_IL_CMD_4 0x00e5
146 #define RT5682_4BTN_IL_CMD_5 0x00e6
147 #define RT5682_4BTN_IL_CMD_6 0x00e7
148 #define RT5682_4BTN_IL_CMD_7 0x00e8
149
150 #define RT5682_ADC_STO1_HP_CTRL_1 0x00ea
151 #define RT5682_ADC_STO1_HP_CTRL_2 0x00eb
152 #define RT5682_AJD1_CTRL 0x00f0
153 #define RT5682_JD1_THD 0x00f1
154 #define RT5682_JD2_THD 0x00f2
155 #define RT5682_JD_CTRL_1 0x00f6
156 /* General Control */
157 #define RT5682_DUMMY_1 0x00fa
158 #define RT5682_DUMMY_2 0x00fb
159 #define RT5682_DUMMY_3 0x00fc
160
161 #define RT5682_DAC_ADC_DIG_VOL1 0x0100
162 #define RT5682_BIAS_CUR_CTRL_2 0x010b
163 #define RT5682_BIAS_CUR_CTRL_3 0x010c
164 #define RT5682_BIAS_CUR_CTRL_4 0x010d
165 #define RT5682_BIAS_CUR_CTRL_5 0x010e
166 #define RT5682_BIAS_CUR_CTRL_6 0x010f
167 #define RT5682_BIAS_CUR_CTRL_7 0x0110
168 #define RT5682_BIAS_CUR_CTRL_8 0x0111
169 #define RT5682_BIAS_CUR_CTRL_9 0x0112
170 #define RT5682_BIAS_CUR_CTRL_10 0x0113
171 #define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117
172 #define RT5682_CHARGE_PUMP_1 0x0125
173 #define RT5682_DIG_IN_CTRL_1 0x0132
174 #define RT5682_PAD_DRIVING_CTRL 0x0136
175 #define RT5682_SOFT_RAMP_DEPOP 0x0138
176 #define RT5682_CHOP_DAC 0x013a
177 #define RT5682_CHOP_ADC 0x013b
178 #define RT5682_CALIB_ADC_CTRL 0x013c
179 #define RT5682_VOL_TEST 0x013f
180 #define RT5682_SPKVDD_DET_STA 0x0142
181 #define RT5682_TEST_MODE_CTRL_1 0x0145
182 #define RT5682_TEST_MODE_CTRL_2 0x0146
183 #define RT5682_TEST_MODE_CTRL_3 0x0147
184 #define RT5682_TEST_MODE_CTRL_4 0x0148
185 #define RT5682_TEST_MODE_CTRL_5 0x0149
186 #define RT5682_PLL1_INTERNAL 0x0150
187 #define RT5682_PLL2_INTERNAL 0x0156
188 #define RT5682_STO_NG2_CTRL_1 0x0160
189 #define RT5682_STO_NG2_CTRL_2 0x0161
190 #define RT5682_STO_NG2_CTRL_3 0x0162
191 #define RT5682_STO_NG2_CTRL_4 0x0163
192 #define RT5682_STO_NG2_CTRL_5 0x0164
193 #define RT5682_STO_NG2_CTRL_6 0x0165
194 #define RT5682_STO_NG2_CTRL_7 0x0166
195 #define RT5682_STO_NG2_CTRL_8 0x0167
196 #define RT5682_STO_NG2_CTRL_9 0x0168
197 #define RT5682_STO_NG2_CTRL_10 0x0169
198 #define RT5682_STO1_DAC_SIL_DET 0x0190
199 #define RT5682_SIL_PSV_CTRL1 0x0194
200 #define RT5682_SIL_PSV_CTRL2 0x0195
201 #define RT5682_SIL_PSV_CTRL3 0x0197
202 #define RT5682_SIL_PSV_CTRL4 0x0198
203 #define RT5682_SIL_PSV_CTRL5 0x0199
204 #define RT5682_HP_IMP_SENS_CTRL_01 0x01af
205 #define RT5682_HP_IMP_SENS_CTRL_02 0x01b0
206 #define RT5682_HP_IMP_SENS_CTRL_03 0x01b1
207 #define RT5682_HP_IMP_SENS_CTRL_04 0x01b2
208 #define RT5682_HP_IMP_SENS_CTRL_05 0x01b3
209 #define RT5682_HP_IMP_SENS_CTRL_06 0x01b4
210 #define RT5682_HP_IMP_SENS_CTRL_07 0x01b5
211 #define RT5682_HP_IMP_SENS_CTRL_08 0x01b6
212 #define RT5682_HP_IMP_SENS_CTRL_09 0x01b7
213 #define RT5682_HP_IMP_SENS_CTRL_10 0x01b8
214 #define RT5682_HP_IMP_SENS_CTRL_11 0x01b9
215 #define RT5682_HP_IMP_SENS_CTRL_12 0x01ba
216 #define RT5682_HP_IMP_SENS_CTRL_13 0x01bb
217 #define RT5682_HP_IMP_SENS_CTRL_14 0x01bc
218 #define RT5682_HP_IMP_SENS_CTRL_15 0x01bd
219 #define RT5682_HP_IMP_SENS_CTRL_16 0x01be
220 #define RT5682_HP_IMP_SENS_CTRL_17 0x01bf
221 #define RT5682_HP_IMP_SENS_CTRL_18 0x01c0
222 #define RT5682_HP_IMP_SENS_CTRL_19 0x01c1
223 #define RT5682_HP_IMP_SENS_CTRL_20 0x01c2
224 #define RT5682_HP_IMP_SENS_CTRL_21 0x01c3
225 #define RT5682_HP_IMP_SENS_CTRL_22 0x01c4
226 #define RT5682_HP_IMP_SENS_CTRL_23 0x01c5
227 #define RT5682_HP_IMP_SENS_CTRL_24 0x01c6
228 #define RT5682_HP_IMP_SENS_CTRL_25 0x01c7
229 #define RT5682_HP_IMP_SENS_CTRL_26 0x01c8
230 #define RT5682_HP_IMP_SENS_CTRL_27 0x01c9
231 #define RT5682_HP_IMP_SENS_CTRL_28 0x01ca
232 #define RT5682_HP_IMP_SENS_CTRL_29 0x01cb
233 #define RT5682_HP_IMP_SENS_CTRL_30 0x01cc
234 #define RT5682_HP_IMP_SENS_CTRL_31 0x01cd
235 #define RT5682_HP_IMP_SENS_CTRL_32 0x01ce
236 #define RT5682_HP_IMP_SENS_CTRL_33 0x01cf
237 #define RT5682_HP_IMP_SENS_CTRL_34 0x01d0
238 #define RT5682_HP_IMP_SENS_CTRL_35 0x01d1
239 #define RT5682_HP_IMP_SENS_CTRL_36 0x01d2
240 #define RT5682_HP_IMP_SENS_CTRL_37 0x01d3
241 #define RT5682_HP_IMP_SENS_CTRL_38 0x01d4
242 #define RT5682_HP_IMP_SENS_CTRL_39 0x01d5
243 #define RT5682_HP_IMP_SENS_CTRL_40 0x01d6
244 #define RT5682_HP_IMP_SENS_CTRL_41 0x01d7
245 #define RT5682_HP_IMP_SENS_CTRL_42 0x01d8
246 #define RT5682_HP_IMP_SENS_CTRL_43 0x01d9
247 #define RT5682_HP_LOGIC_CTRL_1 0x01da
248 #define RT5682_HP_LOGIC_CTRL_2 0x01db
249 #define RT5682_HP_LOGIC_CTRL_3 0x01dc
250 #define RT5682_HP_CALIB_CTRL_1 0x01de
251 #define RT5682_HP_CALIB_CTRL_2 0x01df
252 #define RT5682_HP_CALIB_CTRL_3 0x01e0
253 #define RT5682_HP_CALIB_CTRL_4 0x01e1
254 #define RT5682_HP_CALIB_CTRL_5 0x01e2
255 #define RT5682_HP_CALIB_CTRL_6 0x01e3
256 #define RT5682_HP_CALIB_CTRL_7 0x01e4
257 #define RT5682_HP_CALIB_CTRL_9 0x01e6
258 #define RT5682_HP_CALIB_CTRL_10 0x01e7
259 #define RT5682_HP_CALIB_CTRL_11 0x01e8
260 #define RT5682_HP_CALIB_STA_1 0x01ea
261 #define RT5682_HP_CALIB_STA_2 0x01eb
262 #define RT5682_HP_CALIB_STA_3 0x01ec
263 #define RT5682_HP_CALIB_STA_4 0x01ed
264 #define RT5682_HP_CALIB_STA_5 0x01ee
265 #define RT5682_HP_CALIB_STA_6 0x01ef
266 #define RT5682_HP_CALIB_STA_7 0x01f0
267 #define RT5682_HP_CALIB_STA_8 0x01f1
268 #define RT5682_HP_CALIB_STA_9 0x01f2
269 #define RT5682_HP_CALIB_STA_10 0x01f3
270 #define RT5682_HP_CALIB_STA_11 0x01f4
271 #define RT5682_SAR_IL_CMD_1 0x0210
272 #define RT5682_SAR_IL_CMD_2 0x0211
273 #define RT5682_SAR_IL_CMD_3 0x0212
274 #define RT5682_SAR_IL_CMD_4 0x0213
275 #define RT5682_SAR_IL_CMD_5 0x0214
276 #define RT5682_SAR_IL_CMD_6 0x0215
277 #define RT5682_SAR_IL_CMD_7 0x0216
278 #define RT5682_SAR_IL_CMD_8 0x0217
279 #define RT5682_SAR_IL_CMD_9 0x0218
280 #define RT5682_SAR_IL_CMD_10 0x0219
281 #define RT5682_SAR_IL_CMD_11 0x021a
282 #define RT5682_SAR_IL_CMD_12 0x021b
283 #define RT5682_SAR_IL_CMD_13 0x021c
284 #define RT5682_EFUSE_CTRL_1 0x0250
285 #define RT5682_EFUSE_CTRL_2 0x0251
286 #define RT5682_EFUSE_CTRL_3 0x0252
287 #define RT5682_EFUSE_CTRL_4 0x0253
288 #define RT5682_EFUSE_CTRL_5 0x0254
289 #define RT5682_EFUSE_CTRL_6 0x0255
290 #define RT5682_EFUSE_CTRL_7 0x0256
291 #define RT5682_EFUSE_CTRL_8 0x0257
292 #define RT5682_EFUSE_CTRL_9 0x0258
293 #define RT5682_EFUSE_CTRL_10 0x0259
294 #define RT5682_EFUSE_CTRL_11 0x025a
295 #define RT5682_JD_TOP_VC_VTRL 0x0270
296 #define RT5682_DRC1_CTRL_0 0x02ff
297 #define RT5682_DRC1_CTRL_1 0x0300
298 #define RT5682_DRC1_CTRL_2 0x0301
299 #define RT5682_DRC1_CTRL_3 0x0302
300 #define RT5682_DRC1_CTRL_4 0x0303
301 #define RT5682_DRC1_CTRL_5 0x0304
302 #define RT5682_DRC1_CTRL_6 0x0305
303 #define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306
304 #define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307
305 #define RT5682_DRC1_PRIV_1 0x0310
306 #define RT5682_DRC1_PRIV_2 0x0311
307 #define RT5682_DRC1_PRIV_3 0x0312
308 #define RT5682_DRC1_PRIV_4 0x0313
309 #define RT5682_DRC1_PRIV_5 0x0314
310 #define RT5682_DRC1_PRIV_6 0x0315
311 #define RT5682_DRC1_PRIV_7 0x0316
312 #define RT5682_DRC1_PRIV_8 0x0317
313 #define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0
314 #define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1
315 #define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2
316 #define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3
317 #define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4
318 #define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5
319 #define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6
320 #define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7
321 #define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8
322 #define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9
323 #define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca
324 #define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb
325 #define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc
326 #define RT5682_ADC_L_EQ_LPF1_A1 0x03d0
327 #define RT5682_R_EQ_LPF1_A1 0x03d1
328 #define RT5682_L_EQ_LPF1_H0 0x03d2
329 #define RT5682_R_EQ_LPF1_H0 0x03d3
330 #define RT5682_L_EQ_BPF1_A1 0x03d4
331 #define RT5682_R_EQ_BPF1_A1 0x03d5
332 #define RT5682_L_EQ_BPF1_A2 0x03d6
333 #define RT5682_R_EQ_BPF1_A2 0x03d7
334 #define RT5682_L_EQ_BPF1_H0 0x03d8
335 #define RT5682_R_EQ_BPF1_H0 0x03d9
336 #define RT5682_L_EQ_BPF2_A1 0x03da
337 #define RT5682_R_EQ_BPF2_A1 0x03db
338 #define RT5682_L_EQ_BPF2_A2 0x03dc
339 #define RT5682_R_EQ_BPF2_A2 0x03dd
340 #define RT5682_L_EQ_BPF2_H0 0x03de
341 #define RT5682_R_EQ_BPF2_H0 0x03df
342 #define RT5682_L_EQ_BPF3_A1 0x03e0
343 #define RT5682_R_EQ_BPF3_A1 0x03e1
344 #define RT5682_L_EQ_BPF3_A2 0x03e2
345 #define RT5682_R_EQ_BPF3_A2 0x03e3
346 #define RT5682_L_EQ_BPF3_H0 0x03e4
347 #define RT5682_R_EQ_BPF3_H0 0x03e5
348 #define RT5682_L_EQ_BPF4_A1 0x03e6
349 #define RT5682_R_EQ_BPF4_A1 0x03e7
350 #define RT5682_L_EQ_BPF4_A2 0x03e8
351 #define RT5682_R_EQ_BPF4_A2 0x03e9
352 #define RT5682_L_EQ_BPF4_H0 0x03ea
353 #define RT5682_R_EQ_BPF4_H0 0x03eb
354 #define RT5682_L_EQ_HPF1_A1 0x03ec
355 #define RT5682_R_EQ_HPF1_A1 0x03ed
356 #define RT5682_L_EQ_HPF1_H0 0x03ee
357 #define RT5682_R_EQ_HPF1_H0 0x03ef
358 #define RT5682_L_EQ_PRE_VOL 0x03f0
359 #define RT5682_R_EQ_PRE_VOL 0x03f1
360 #define RT5682_L_EQ_POST_VOL 0x03f2
361 #define RT5682_R_EQ_POST_VOL 0x03f3
362 #define RT5682_I2C_MODE 0xffff
363
364
365 /* global definition */
366 #define RT5682_L_MUTE (0x1 << 15)
367 #define RT5682_L_MUTE_SFT 15
368 #define RT5682_VOL_L_MUTE (0x1 << 14)
369 #define RT5682_VOL_L_SFT 14
370 #define RT5682_R_MUTE (0x1 << 7)
371 #define RT5682_R_MUTE_SFT 7
372 #define RT5682_VOL_R_MUTE (0x1 << 6)
373 #define RT5682_VOL_R_SFT 6
374 #define RT5682_L_VOL_MASK (0x3f << 8)
375 #define RT5682_L_VOL_SFT 8
376 #define RT5682_R_VOL_MASK (0x3f)
377 #define RT5682_R_VOL_SFT 0
378
379 /* Headphone Amp Control 2 (0x0003) */
380 #define RT5682_HP_C2_DAC_AMP_MUTE_SFT 15
381 #define RT5682_HP_C2_DAC_AMP_MUTE (0x1 << 15)
382 #define RT5682_HP_C2_DAC_L_EN_SFT 14
383 #define RT5682_HP_C2_DAC_L_EN (0x1 << 14)
384 #define RT5682_HP_C2_DAC_R_EN_SFT 13
385 #define RT5682_HP_C2_DAC_R_EN (0x1 << 13)
386
387 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
388 #define RT5682_G_HP (0xf << 8)
389 #define RT5682_G_HP_SFT 8
390 #define RT5682_G_STO_DA_DMIX (0xf)
391 #define RT5682_G_STO_DA_SFT 0
392
393 /* CBJ Control (0x000b) */
394 #define RT5682_BST_CBJ_MASK (0xf << 8)
395 #define RT5682_BST_CBJ_SFT 8
396
397 /* Embeeded Jack and Type Detection Control 1 (0x0010) */
398 #define RT5682_EMB_JD_EN (0x1 << 15)
399 #define RT5682_EMB_JD_EN_SFT 15
400 #define RT5682_EMB_JD_RST (0x1 << 14)
401 #define RT5682_JD_MODE (0x1 << 13)
402 #define RT5682_JD_MODE_SFT 13
403 #define RT5682_DET_TYPE (0x1 << 12)
404 #define RT5682_DET_TYPE_SFT 12
405 #define RT5682_POLA_EXT_JD_MASK (0x1 << 11)
406 #define RT5682_POLA_EXT_JD_LOW (0x1 << 11)
407 #define RT5682_POLA_EXT_JD_HIGH (0x0 << 11)
408 #define RT5682_EXT_JD_DIG (0x1 << 9)
409 #define RT5682_POL_FAST_OFF_MASK (0x1 << 8)
410 #define RT5682_POL_FAST_OFF_HIGH (0x1 << 8)
411 #define RT5682_POL_FAST_OFF_LOW (0x0 << 8)
412 #define RT5682_FAST_OFF_MASK (0x1 << 7)
413 #define RT5682_FAST_OFF_EN (0x1 << 7)
414 #define RT5682_FAST_OFF_DIS (0x0 << 7)
415 #define RT5682_VREF_POW_MASK (0x1 << 6)
416 #define RT5682_VREF_POW_FSM (0x0 << 6)
417 #define RT5682_VREF_POW_REG (0x1 << 6)
418 #define RT5682_MB1_PATH_MASK (0x1 << 5)
419 #define RT5682_CTRL_MB1_REG (0x1 << 5)
420 #define RT5682_CTRL_MB1_FSM (0x0 << 5)
421 #define RT5682_MB2_PATH_MASK (0x1 << 4)
422 #define RT5682_CTRL_MB2_REG (0x1 << 4)
423 #define RT5682_CTRL_MB2_FSM (0x0 << 4)
424 #define RT5682_TRIG_JD_MASK (0x1 << 3)
425 #define RT5682_TRIG_JD_HIGH (0x1 << 3)
426 #define RT5682_TRIG_JD_LOW (0x0 << 3)
427 #define RT5682_MIC_CAP_MASK (0x1 << 1)
428 #define RT5682_MIC_CAP_HS (0x1 << 1)
429 #define RT5682_MIC_CAP_HP (0x0 << 1)
430 #define RT5682_MIC_CAP_SRC_MASK (0x1)
431 #define RT5682_MIC_CAP_SRC_REG (0x1)
432 #define RT5682_MIC_CAP_SRC_ANA (0x0)
433
434 /* Embeeded Jack and Type Detection Control 2 (0x0011) */
435 #define RT5682_EXT_JD_SRC (0x7 << 4)
436 #define RT5682_EXT_JD_SRC_SFT 4
437 #define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
438 #define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
439 #define RT5682_EXT_JD_SRC_JDH (0x2 << 4)
440 #define RT5682_EXT_JD_SRC_JDL (0x3 << 4)
441 #define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4)
442 #define RT5682_JACK_TYPE_MASK (0x3)
443
444 /* Combo Jack and Type Detection Control 3 (0x0012) */
445 #define RT5682_CBJ_IN_BUF_EN (0x1 << 7)
446
447 /* Combo Jack and Type Detection Control 4 (0x0013) */
448 #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12)
449 #define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12)
450 #define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12)
451 #define RT5682_CBJ_JD_TEST_MASK (0x1 << 6)
452 #define RT5682_CBJ_JD_TEST_NORM (0x0 << 6)
453 #define RT5682_CBJ_JD_TEST_MODE (0x1 << 6)
454
455 /* DAC1 Digital Volume (0x0019) */
456 #define RT5682_DAC_L1_VOL_MASK (0xff << 8)
457 #define RT5682_DAC_L1_VOL_SFT 8
458 #define RT5682_DAC_R1_VOL_MASK (0xff)
459 #define RT5682_DAC_R1_VOL_SFT 0
460
461 /* ADC Digital Volume Control (0x001c) */
462 #define RT5682_ADC_L_VOL_MASK (0x7f << 8)
463 #define RT5682_ADC_L_VOL_SFT 8
464 #define RT5682_ADC_R_VOL_MASK (0x7f)
465 #define RT5682_ADC_R_VOL_SFT 0
466
467 /* Stereo1 ADC Boost Gain Control (0x001f) */
468 #define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14)
469 #define RT5682_STO1_ADC_L_BST_SFT 14
470 #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12)
471 #define RT5682_STO1_ADC_R_BST_SFT 12
472
473 /* Sidetone Control (0x0024) */
474 #define RT5682_ST_SRC_SEL (0x1 << 8)
475 #define RT5682_ST_SRC_SFT 8
476 #define RT5682_ST_EN_MASK (0x1 << 6)
477 #define RT5682_ST_DIS (0x0 << 6)
478 #define RT5682_ST_EN (0x1 << 6)
479 #define RT5682_ST_EN_SFT 6
480
481 /* Stereo1 ADC Mixer Control (0x0026) */
482 #define RT5682_M_STO1_ADC_L1 (0x1 << 15)
483 #define RT5682_M_STO1_ADC_L1_SFT 15
484 #define RT5682_M_STO1_ADC_L2 (0x1 << 14)
485 #define RT5682_M_STO1_ADC_L2_SFT 14
486 #define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13)
487 #define RT5682_STO1_ADC1L_SRC_SFT 13
488 #define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13)
489 #define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13)
490 #define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12)
491 #define RT5682_STO1_ADC2L_SRC_SFT 12
492 #define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10)
493 #define RT5682_STO1_ADCL_SRC_SFT 10
494 #define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9)
495 #define RT5682_STO1_DD_L_SRC_SFT 9
496 #define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8)
497 #define RT5682_STO1_DMIC_SRC_SFT 8
498 #define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
499 #define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
500 #define RT5682_M_STO1_ADC_R1 (0x1 << 7)
501 #define RT5682_M_STO1_ADC_R1_SFT 7
502 #define RT5682_M_STO1_ADC_R2 (0x1 << 6)
503 #define RT5682_M_STO1_ADC_R2_SFT 6
504 #define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5)
505 #define RT5682_STO1_ADC1R_SRC_SFT 5
506 #define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4)
507 #define RT5682_STO1_ADC2R_SRC_SFT 4
508 #define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2)
509 #define RT5682_STO1_ADCR_SRC_SFT 2
510
511 /* ADC Mixer to DAC Mixer Control (0x0029) */
512 #define RT5682_M_ADCMIX_L (0x1 << 15)
513 #define RT5682_M_ADCMIX_L_SFT 15
514 #define RT5682_M_DAC1_L (0x1 << 14)
515 #define RT5682_M_DAC1_L_SFT 14
516 #define RT5682_DAC1_R_SEL_MASK (0x1 << 10)
517 #define RT5682_DAC1_R_SEL_SFT 10
518 #define RT5682_DAC1_L_SEL_MASK (0x1 << 8)
519 #define RT5682_DAC1_L_SEL_SFT 8
520 #define RT5682_M_ADCMIX_R (0x1 << 7)
521 #define RT5682_M_ADCMIX_R_SFT 7
522 #define RT5682_M_DAC1_R (0x1 << 6)
523 #define RT5682_M_DAC1_R_SFT 6
524
525 /* Stereo1 DAC Mixer Control (0x002a) */
526 #define RT5682_M_DAC_L1_STO_L (0x1 << 15)
527 #define RT5682_M_DAC_L1_STO_L_SFT 15
528 #define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14)
529 #define RT5682_G_DAC_L1_STO_L_SFT 14
530 #define RT5682_M_DAC_R1_STO_L (0x1 << 13)
531 #define RT5682_M_DAC_R1_STO_L_SFT 13
532 #define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12)
533 #define RT5682_G_DAC_R1_STO_L_SFT 12
534 #define RT5682_M_DAC_L1_STO_R (0x1 << 7)
535 #define RT5682_M_DAC_L1_STO_R_SFT 7
536 #define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6)
537 #define RT5682_G_DAC_L1_STO_R_SFT 6
538 #define RT5682_M_DAC_R1_STO_R (0x1 << 5)
539 #define RT5682_M_DAC_R1_STO_R_SFT 5
540 #define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4)
541 #define RT5682_G_DAC_R1_STO_R_SFT 4
542
543 /* Analog DAC1 Input Source Control (0x002b) */
544 #define RT5682_M_ST_STO_L (0x1 << 9)
545 #define RT5682_M_ST_STO_L_SFT 9
546 #define RT5682_M_ST_STO_R (0x1 << 8)
547 #define RT5682_M_ST_STO_R_SFT 8
548 #define RT5682_DAC_L1_SRC_MASK (0x3 << 4)
549 #define RT5682_A_DACL1_SFT 4
550 #define RT5682_DAC_R1_SRC_MASK (0x3)
551 #define RT5682_A_DACR1_SFT 0
552
553 /* Digital Interface Data Control (0x0030) */
554 #define RT5682_IF2_ADC_SEL_MASK (0x3 << 0)
555 #define RT5682_IF2_ADC_SEL_SFT 0
556
557 /* REC Left Mixer Control 2 (0x003c) */
558 #define RT5682_G_CBJ_RM1_L (0x7 << 10)
559 #define RT5682_G_CBJ_RM1_L_SFT 10
560 #define RT5682_M_CBJ_RM1_L (0x1 << 7)
561 #define RT5682_M_CBJ_RM1_L_SFT 7
562
563 /* Power Management for Digital 1 (0x0061) */
564 #define RT5682_PWR_I2S1 (0x1 << 15)
565 #define RT5682_PWR_I2S1_BIT 15
566 #define RT5682_PWR_I2S2 (0x1 << 14)
567 #define RT5682_PWR_I2S2_BIT 14
568 #define RT5682_PWR_DAC_L1 (0x1 << 11)
569 #define RT5682_PWR_DAC_L1_BIT 11
570 #define RT5682_PWR_DAC_R1 (0x1 << 10)
571 #define RT5682_PWR_DAC_R1_BIT 10
572 #define RT5682_PWR_LDO (0x1 << 8)
573 #define RT5682_PWR_LDO_BIT 8
574 #define RT5682_PWR_ADC_L1 (0x1 << 4)
575 #define RT5682_PWR_ADC_L1_BIT 4
576 #define RT5682_PWR_ADC_R1 (0x1 << 3)
577 #define RT5682_PWR_ADC_R1_BIT 3
578 #define RT5682_DIG_GATE_CTRL (0x1 << 0)
579 #define RT5682_DIG_GATE_CTRL_SFT 0
580
581
582 /* Power Management for Digital 2 (0x0062) */
583 #define RT5682_PWR_ADC_S1F (0x1 << 15)
584 #define RT5682_PWR_ADC_S1F_BIT 15
585 #define RT5682_PWR_DAC_S1F (0x1 << 10)
586 #define RT5682_PWR_DAC_S1F_BIT 10
587
588 /* Power Management for Analog 1 (0x0063) */
589 #define RT5682_PWR_VREF1 (0x1 << 15)
590 #define RT5682_PWR_VREF1_BIT 15
591 #define RT5682_PWR_FV1 (0x1 << 14)
592 #define RT5682_PWR_FV1_BIT 14
593 #define RT5682_PWR_VREF2 (0x1 << 13)
594 #define RT5682_PWR_VREF2_BIT 13
595 #define RT5682_PWR_FV2 (0x1 << 12)
596 #define RT5682_PWR_FV2_BIT 12
597 #define RT5682_LDO1_DBG_MASK (0x3 << 10)
598 #define RT5682_PWR_MB (0x1 << 9)
599 #define RT5682_PWR_MB_BIT 9
600 #define RT5682_PWR_BG (0x1 << 7)
601 #define RT5682_PWR_BG_BIT 7
602 #define RT5682_LDO1_BYPASS_MASK (0x1 << 6)
603 #define RT5682_LDO1_BYPASS (0x1 << 6)
604 #define RT5682_LDO1_NOT_BYPASS (0x0 << 6)
605 #define RT5682_PWR_MA_BIT 6
606 #define RT5682_LDO1_DVO_MASK (0x3 << 4)
607 #define RT5682_LDO1_DVO_09 (0x0 << 4)
608 #define RT5682_LDO1_DVO_10 (0x1 << 4)
609 #define RT5682_LDO1_DVO_12 (0x2 << 4)
610 #define RT5682_LDO1_DVO_14 (0x3 << 4)
611 #define RT5682_HP_DRIVER_MASK (0x3 << 2)
612 #define RT5682_HP_DRIVER_1X (0x0 << 2)
613 #define RT5682_HP_DRIVER_3X (0x1 << 2)
614 #define RT5682_HP_DRIVER_5X (0x3 << 2)
615 #define RT5682_PWR_HA_L (0x1 << 1)
616 #define RT5682_PWR_HA_L_BIT 1
617 #define RT5682_PWR_HA_R (0x1 << 0)
618 #define RT5682_PWR_HA_R_BIT 0
619
620 /* Power Management for Analog 2 (0x0064) */
621 #define RT5682_PWR_MB1 (0x1 << 11)
622 #define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11)
623 #define RT5682_PWR_MB1_BIT 11
624 #define RT5682_PWR_MB2 (0x1 << 10)
625 #define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10)
626 #define RT5682_PWR_MB2_BIT 10
627 #define RT5682_PWR_JDH (0x1 << 3)
628 #define RT5682_PWR_JDH_BIT 3
629 #define RT5682_PWR_JDL (0x1 << 2)
630 #define RT5682_PWR_JDL_BIT 2
631 #define RT5682_PWR_RM1_L (0x1 << 1)
632 #define RT5682_PWR_RM1_L_BIT 1
633
634 /* Power Management for Analog 3 (0x0065) */
635 #define RT5682_PWR_CBJ (0x1 << 9)
636 #define RT5682_PWR_CBJ_BIT 9
637 #define RT5682_PWR_PLL (0x1 << 6)
638 #define RT5682_PWR_PLL_BIT 6
639 #define RT5682_PWR_PLL2B (0x1 << 5)
640 #define RT5682_PWR_PLL2B_BIT 5
641 #define RT5682_PWR_PLL2F (0x1 << 4)
642 #define RT5682_PWR_PLL2F_BIT 4
643 #define RT5682_PWR_LDO2 (0x1 << 2)
644 #define RT5682_PWR_LDO2_BIT 2
645 #define RT5682_PWR_DET_SPKVDD (0x1 << 1)
646 #define RT5682_PWR_DET_SPKVDD_BIT 1
647
648 /* Power Management for Mixer (0x0066) */
649 #define RT5682_PWR_STO1_DAC_L (0x1 << 5)
650 #define RT5682_PWR_STO1_DAC_L_BIT 5
651 #define RT5682_PWR_STO1_DAC_R (0x1 << 4)
652 #define RT5682_PWR_STO1_DAC_R_BIT 4
653
654 /* MCLK and System Clock Detection Control (0x006b) */
655 #define RT5682_SYS_CLK_DET (0x1 << 15)
656 #define RT5682_SYS_CLK_DET_SFT 15
657 #define RT5682_PLL1_CLK_DET (0x1 << 14)
658 #define RT5682_PLL1_CLK_DET_SFT 14
659 #define RT5682_PLL2_CLK_DET (0x1 << 13)
660 #define RT5682_PLL2_CLK_DET_SFT 13
661 #define RT5682_POW_CLK_DET2_SFT 8
662 #define RT5682_POW_CLK_DET_SFT 0
663
664 /* Digital Microphone Control 1 (0x006e) */
665 #define RT5682_DMIC_1_EN_MASK (0x1 << 15)
666 #define RT5682_DMIC_1_EN_SFT 15
667 #define RT5682_DMIC_1_DIS (0x0 << 15)
668 #define RT5682_DMIC_1_EN (0x1 << 15)
669 #define RT5682_FIFO_CLK_DIV_MASK (0x7 << 12)
670 #define RT5682_FIFO_CLK_DIV_2 (0x1 << 12)
671 #define RT5682_DMIC_1_DP_MASK (0x3 << 4)
672 #define RT5682_DMIC_1_DP_SFT 4
673 #define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4)
674 #define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4)
675 #define RT5682_DMIC_CLK_MASK (0xf << 0)
676 #define RT5682_DMIC_CLK_SFT 0
677
678 /* I2S1 Audio Serial Data Port Control (0x0070) */
679 #define RT5682_SEL_ADCDAT_MASK (0x1 << 15)
680 #define RT5682_SEL_ADCDAT_OUT (0x0 << 15)
681 #define RT5682_SEL_ADCDAT_IN (0x1 << 15)
682 #define RT5682_SEL_ADCDAT_SFT 15
683 #define RT5682_I2S1_TX_CHL_MASK (0x7 << 12)
684 #define RT5682_I2S1_TX_CHL_SFT 12
685 #define RT5682_I2S1_TX_CHL_16 (0x0 << 12)
686 #define RT5682_I2S1_TX_CHL_20 (0x1 << 12)
687 #define RT5682_I2S1_TX_CHL_24 (0x2 << 12)
688 #define RT5682_I2S1_TX_CHL_32 (0x3 << 12)
689 #define RT5682_I2S1_TX_CHL_8 (0x4 << 12)
690 #define RT5682_I2S1_RX_CHL_MASK (0x7 << 8)
691 #define RT5682_I2S1_RX_CHL_SFT 8
692 #define RT5682_I2S1_RX_CHL_16 (0x0 << 8)
693 #define RT5682_I2S1_RX_CHL_20 (0x1 << 8)
694 #define RT5682_I2S1_RX_CHL_24 (0x2 << 8)
695 #define RT5682_I2S1_RX_CHL_32 (0x3 << 8)
696 #define RT5682_I2S1_RX_CHL_8 (0x4 << 8)
697 #define RT5682_I2S1_MONO_MASK (0x1 << 7)
698 #define RT5682_I2S1_MONO_EN (0x1 << 7)
699 #define RT5682_I2S1_MONO_DIS (0x0 << 7)
700 #define RT5682_I2S2_MONO_MASK (0x1 << 6)
701 #define RT5682_I2S2_MONO_EN (0x1 << 6)
702 #define RT5682_I2S2_MONO_DIS (0x0 << 6)
703 #define RT5682_I2S1_DL_MASK (0x7 << 4)
704 #define RT5682_I2S1_DL_SFT 4
705 #define RT5682_I2S1_DL_16 (0x0 << 4)
706 #define RT5682_I2S1_DL_20 (0x1 << 4)
707 #define RT5682_I2S1_DL_24 (0x2 << 4)
708 #define RT5682_I2S1_DL_32 (0x3 << 4)
709 #define RT5682_I2S1_DL_8 (0x4 << 4)
710
711 /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */
712 #define RT5682_I2S2_MS_MASK (0x1 << 15)
713 #define RT5682_I2S2_MS_SFT 15
714 #define RT5682_I2S2_MS_M (0x0 << 15)
715 #define RT5682_I2S2_MS_S (0x1 << 15)
716 #define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14)
717 #define RT5682_I2S2_PIN_CFG_SFT 14
718 #define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11)
719 #define RT5682_I2S2_CLK_SEL_SFT 11
720 #define RT5682_I2S2_OUT_MASK (0x1 << 9)
721 #define RT5682_I2S2_OUT_SFT 9
722 #define RT5682_I2S2_OUT_UM (0x0 << 9)
723 #define RT5682_I2S2_OUT_M (0x1 << 9)
724 #define RT5682_I2S_BP_MASK (0x1 << 8)
725 #define RT5682_I2S_BP_SFT 8
726 #define RT5682_I2S_BP_NOR (0x0 << 8)
727 #define RT5682_I2S_BP_INV (0x1 << 8)
728 #define RT5682_I2S2_MONO_EN (0x1 << 6)
729 #define RT5682_I2S2_MONO_DIS (0x0 << 6)
730 #define RT5682_I2S2_DL_MASK (0x3 << 4)
731 #define RT5682_I2S2_DL_SFT 4
732 #define RT5682_I2S2_DL_16 (0x0 << 4)
733 #define RT5682_I2S2_DL_20 (0x1 << 4)
734 #define RT5682_I2S2_DL_24 (0x2 << 4)
735 #define RT5682_I2S2_DL_8 (0x3 << 4)
736 #define RT5682_I2S_DF_MASK (0x7)
737 #define RT5682_I2S_DF_SFT 0
738 #define RT5682_I2S_DF_I2S (0x0)
739 #define RT5682_I2S_DF_LEFT (0x1)
740 #define RT5682_I2S_DF_PCM_A (0x2)
741 #define RT5682_I2S_DF_PCM_B (0x3)
742 #define RT5682_I2S_DF_PCM_A_N (0x6)
743 #define RT5682_I2S_DF_PCM_B_N (0x7)
744
745 /* ADC/DAC Clock Control 1 (0x0073) */
746 #define RT5682_ADC_OSR_MASK (0xf << 12)
747 #define RT5682_ADC_OSR_SFT 12
748 #define RT5682_ADC_OSR_D_1 (0x0 << 12)
749 #define RT5682_ADC_OSR_D_2 (0x1 << 12)
750 #define RT5682_ADC_OSR_D_4 (0x2 << 12)
751 #define RT5682_ADC_OSR_D_6 (0x3 << 12)
752 #define RT5682_ADC_OSR_D_8 (0x4 << 12)
753 #define RT5682_ADC_OSR_D_12 (0x5 << 12)
754 #define RT5682_ADC_OSR_D_16 (0x6 << 12)
755 #define RT5682_ADC_OSR_D_24 (0x7 << 12)
756 #define RT5682_ADC_OSR_D_32 (0x8 << 12)
757 #define RT5682_ADC_OSR_D_48 (0x9 << 12)
758 #define RT5682_I2S_M_DIV_MASK (0xf << 8)
759 #define RT5682_I2S_M_DIV_SFT 8
760 #define RT5682_I2S_M_D_1 (0x0 << 8)
761 #define RT5682_I2S_M_D_2 (0x1 << 8)
762 #define RT5682_I2S_M_D_3 (0x2 << 8)
763 #define RT5682_I2S_M_D_4 (0x3 << 8)
764 #define RT5682_I2S_M_D_6 (0x4 << 8)
765 #define RT5682_I2S_M_D_8 (0x5 << 8)
766 #define RT5682_I2S_M_D_12 (0x6 << 8)
767 #define RT5682_I2S_M_D_16 (0x7 << 8)
768 #define RT5682_I2S_M_D_24 (0x8 << 8)
769 #define RT5682_I2S_M_D_32 (0x9 << 8)
770 #define RT5682_I2S_M_D_48 (0x10 << 8)
771 #define RT5682_I2S_CLK_SRC_MASK (0x7 << 4)
772 #define RT5682_I2S_CLK_SRC_SFT 4
773 #define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4)
774 #define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4)
775 #define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4)
776 #define RT5682_I2S_CLK_SRC_SDW (0x3 << 4)
777 #define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */
778 #define RT5682_DAC_OSR_MASK (0xf << 0)
779 #define RT5682_DAC_OSR_SFT 0
780 #define RT5682_DAC_OSR_D_1 (0x0 << 0)
781 #define RT5682_DAC_OSR_D_2 (0x1 << 0)
782 #define RT5682_DAC_OSR_D_4 (0x2 << 0)
783 #define RT5682_DAC_OSR_D_6 (0x3 << 0)
784 #define RT5682_DAC_OSR_D_8 (0x4 << 0)
785 #define RT5682_DAC_OSR_D_12 (0x5 << 0)
786 #define RT5682_DAC_OSR_D_16 (0x6 << 0)
787 #define RT5682_DAC_OSR_D_24 (0x7 << 0)
788 #define RT5682_DAC_OSR_D_32 (0x8 << 0)
789 #define RT5682_DAC_OSR_D_48 (0x9 << 0)
790
791 /* ADC/DAC Clock Control 2 (0x0074) */
792 #define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11)
793 #define RT5682_I2S2_BCLK_MS2_SFT 11
794 #define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11)
795 #define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11)
796
797
798 /* TDM control 1 (0x0079) */
799 #define RT5682_TDM_TX_CH_MASK (0x3 << 12)
800 #define RT5682_TDM_TX_CH_2 (0x0 << 12)
801 #define RT5682_TDM_TX_CH_4 (0x1 << 12)
802 #define RT5682_TDM_TX_CH_6 (0x2 << 12)
803 #define RT5682_TDM_TX_CH_8 (0x3 << 12)
804 #define RT5682_TDM_RX_CH_MASK (0x3 << 8)
805 #define RT5682_TDM_RX_CH_2 (0x0 << 8)
806 #define RT5682_TDM_RX_CH_4 (0x1 << 8)
807 #define RT5682_TDM_RX_CH_6 (0x2 << 8)
808 #define RT5682_TDM_RX_CH_8 (0x3 << 8)
809 #define RT5682_TDM_ADC_LCA_MASK (0xf << 4)
810 #define RT5682_TDM_ADC_LCA_SFT 4
811 #define RT5682_TDM_ADC_DL_SFT 0
812
813 /* TDM control 2 (0x007a) */
814 #define RT5682_IF1_ADC1_SEL_SFT 14
815 #define RT5682_IF1_ADC2_SEL_SFT 12
816 #define RT5682_IF1_ADC3_SEL_SFT 10
817 #define RT5682_IF1_ADC4_SEL_SFT 8
818 #define RT5682_TDM_ADC_SEL_SFT 4
819
820 /* TDM control 3 (0x007b) */
821 #define RT5682_TDM_EN (0x1 << 7)
822
823 /* TDM/I2S control (0x007e) */
824 #define RT5682_TDM_S_BP_MASK (0x1 << 15)
825 #define RT5682_TDM_S_BP_SFT 15
826 #define RT5682_TDM_S_BP_NOR (0x0 << 15)
827 #define RT5682_TDM_S_BP_INV (0x1 << 15)
828 #define RT5682_TDM_S_LP_MASK (0x1 << 14)
829 #define RT5682_TDM_S_LP_SFT 14
830 #define RT5682_TDM_S_LP_NOR (0x0 << 14)
831 #define RT5682_TDM_S_LP_INV (0x1 << 14)
832 #define RT5682_TDM_DF_MASK (0x7 << 11)
833 #define RT5682_TDM_DF_SFT 11
834 #define RT5682_TDM_DF_I2S (0x0 << 11)
835 #define RT5682_TDM_DF_LEFT (0x1 << 11)
836 #define RT5682_TDM_DF_PCM_A (0x2 << 11)
837 #define RT5682_TDM_DF_PCM_B (0x3 << 11)
838 #define RT5682_TDM_DF_PCM_A_N (0x6 << 11)
839 #define RT5682_TDM_DF_PCM_B_N (0x7 << 11)
840 #define RT5682_TDM_BCLK_MS1_MASK (0x3 << 9)
841 #define RT5682_TDM_BCLK_MS1_SFT 9
842 #define RT5682_TDM_BCLK_MS1_32 (0x0 << 9)
843 #define RT5682_TDM_BCLK_MS1_64 (0x1 << 9)
844 #define RT5682_TDM_BCLK_MS1_128 (0x2 << 9)
845 #define RT5682_TDM_BCLK_MS1_256 (0x3 << 9)
846 #define RT5682_TDM_CL_MASK (0x3 << 4)
847 #define RT5682_TDM_CL_16 (0x0 << 4)
848 #define RT5682_TDM_CL_20 (0x1 << 4)
849 #define RT5682_TDM_CL_24 (0x2 << 4)
850 #define RT5682_TDM_CL_32 (0x3 << 4)
851 #define RT5682_TDM_M_BP_MASK (0x1 << 2)
852 #define RT5682_TDM_M_BP_SFT 2
853 #define RT5682_TDM_M_BP_NOR (0x0 << 2)
854 #define RT5682_TDM_M_BP_INV (0x1 << 2)
855 #define RT5682_TDM_M_LP_MASK (0x1 << 1)
856 #define RT5682_TDM_M_LP_SFT 1
857 #define RT5682_TDM_M_LP_NOR (0x0 << 1)
858 #define RT5682_TDM_M_LP_INV (0x1 << 1)
859 #define RT5682_TDM_MS_MASK (0x1 << 0)
860 #define RT5682_TDM_MS_SFT 0
861 #define RT5682_TDM_MS_S (0x0 << 0)
862 #define RT5682_TDM_MS_M (0x1 << 0)
863
864 /* Global Clock Control (0x0080) */
865 #define RT5682_SCLK_SRC_MASK (0x7 << 13)
866 #define RT5682_SCLK_SRC_SFT 13
867 #define RT5682_SCLK_SRC_MCLK (0x0 << 13)
868 #define RT5682_SCLK_SRC_PLL1 (0x1 << 13)
869 #define RT5682_SCLK_SRC_PLL2 (0x2 << 13)
870 #define RT5682_SCLK_SRC_SDW (0x3 << 13)
871 #define RT5682_SCLK_SRC_RCCLK (0x4 << 13)
872 #define RT5682_PLL2_SRC_MASK (0x3 << 10)
873 #define RT5682_PLL2_SRC_SFT 10
874 #define RT5682_PLL2_SRC_MCLK (0x0 << 10)
875 #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10)
876 #define RT5682_PLL2_SRC_SDW (0x2 << 10)
877 #define RT5682_PLL2_SRC_RC (0x3 << 10)
878 #define RT5682_PLL1_SRC_MASK (0x3 << 8)
879 #define RT5682_PLL1_SRC_SFT 8
880 #define RT5682_PLL1_SRC_MCLK (0x0 << 8)
881 #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8)
882 #define RT5682_PLL1_SRC_SDW (0x2 << 8)
883 #define RT5682_PLL1_SRC_RC (0x3 << 8)
884
885
886
887 #define RT5682_PLL_INP_MAX 40000000
888 #define RT5682_PLL_INP_MIN 256000
889 /* PLL M/N/K Code Control 1 (0x0081) */
890 #define RT5682_PLL_N_MAX 0x001ff
891 #define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7)
892 #define RT5682_PLL_N_SFT 7
893 #define RT5682_PLL_K_MAX 0x001f
894 #define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX)
895 #define RT5682_PLL_K_SFT 0
896
897 /* PLL M/N/K Code Control 2 (0x0082) */
898 #define RT5682_PLL_M_MAX 0x00f
899 #define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12)
900 #define RT5682_PLL_M_SFT 12
901 #define RT5682_PLL_M_BP (0x1 << 11)
902 #define RT5682_PLL_M_BP_SFT 11
903 #define RT5682_PLL_K_BP (0x1 << 10)
904 #define RT5682_PLL_K_BP_SFT 10
905 #define RT5682_PLL_RST (0x1 << 1)
906
907 /* PLL tracking mode 1 (0x0083) */
908 #define RT5682_DA_ASRC_MASK (0x1 << 13)
909 #define RT5682_DA_ASRC_SFT 13
910 #define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12)
911 #define RT5682_DAC_STO1_ASRC_SFT 12
912 #define RT5682_AD_ASRC_MASK (0x1 << 8)
913 #define RT5682_AD_ASRC_SFT 8
914 #define RT5682_AD_ASRC_SEL_MASK (0x1 << 4)
915 #define RT5682_AD_ASRC_SEL_SFT 4
916 #define RT5682_DMIC_ASRC_MASK (0x1 << 3)
917 #define RT5682_DMIC_ASRC_SFT 3
918 #define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2)
919 #define RT5682_ADC_STO1_ASRC_SFT 2
920 #define RT5682_DA_ASRC_SEL_MASK (0x1 << 0)
921 #define RT5682_DA_ASRC_SEL_SFT 0
922
923 /* PLL tracking mode 2 3 (0x0084)(0x0085)*/
924 #define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12)
925 #define RT5682_FILTER_CLK_SEL_SFT 12
926 #define RT5682_FILTER_CLK_DIV_MASK (0xf << 8)
927 #define RT5682_FILTER_CLK_DIV_SFT 8
928
929 /* ASRC Control 4 (0x0086) */
930 #define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14)
931 #define RT5682_ASRCIN_FTK_N1_SFT 14
932 #define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12)
933 #define RT5682_ASRCIN_FTK_N2_SFT 12
934 #define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8)
935 #define RT5682_ASRCIN_FTK_M1_SFT 8
936 #define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4)
937 #define RT5682_ASRCIN_FTK_M2_SFT 4
938
939 /* SoundWire reference clk (0x008d) */
940 #define RT5682_PLL2_OUT_MASK (0x1 << 8)
941 #define RT5682_PLL2_OUT_98M (0x0 << 8)
942 #define RT5682_PLL2_OUT_49M (0x1 << 8)
943 #define RT5682_SDW_REF_2_MASK (0xf << 4)
944 #define RT5682_SDW_REF_2_SFT 4
945 #define RT5682_SDW_REF_2_48K (0x0 << 4)
946 #define RT5682_SDW_REF_2_96K (0x1 << 4)
947 #define RT5682_SDW_REF_2_192K (0x2 << 4)
948 #define RT5682_SDW_REF_2_32K (0x3 << 4)
949 #define RT5682_SDW_REF_2_24K (0x4 << 4)
950 #define RT5682_SDW_REF_2_16K (0x5 << 4)
951 #define RT5682_SDW_REF_2_12K (0x6 << 4)
952 #define RT5682_SDW_REF_2_8K (0x7 << 4)
953 #define RT5682_SDW_REF_2_44K (0x8 << 4)
954 #define RT5682_SDW_REF_2_88K (0x9 << 4)
955 #define RT5682_SDW_REF_2_176K (0xa << 4)
956 #define RT5682_SDW_REF_2_353K (0xb << 4)
957 #define RT5682_SDW_REF_2_22K (0xc << 4)
958 #define RT5682_SDW_REF_2_384K (0xd << 4)
959 #define RT5682_SDW_REF_2_11K (0xe << 4)
960 #define RT5682_SDW_REF_1_MASK (0xf << 0)
961 #define RT5682_SDW_REF_1_SFT 0
962 #define RT5682_SDW_REF_1_48K (0x0 << 0)
963 #define RT5682_SDW_REF_1_96K (0x1 << 0)
964 #define RT5682_SDW_REF_1_192K (0x2 << 0)
965 #define RT5682_SDW_REF_1_32K (0x3 << 0)
966 #define RT5682_SDW_REF_1_24K (0x4 << 0)
967 #define RT5682_SDW_REF_1_16K (0x5 << 0)
968 #define RT5682_SDW_REF_1_12K (0x6 << 0)
969 #define RT5682_SDW_REF_1_8K (0x7 << 0)
970 #define RT5682_SDW_REF_1_44K (0x8 << 0)
971 #define RT5682_SDW_REF_1_88K (0x9 << 0)
972 #define RT5682_SDW_REF_1_176K (0xa << 0)
973 #define RT5682_SDW_REF_1_353K (0xb << 0)
974 #define RT5682_SDW_REF_1_22K (0xc << 0)
975 #define RT5682_SDW_REF_1_384K (0xd << 0)
976 #define RT5682_SDW_REF_1_11K (0xe << 0)
977
978 /* Depop Mode Control 1 (0x008e) */
979 #define RT5682_PUMP_EN (0x1 << 3)
980 #define RT5682_PUMP_EN_SFT 3
981 #define RT5682_CAPLESS_EN (0x1 << 0)
982 #define RT5682_CAPLESS_EN_SFT 0
983
984 /* Depop Mode Control 2 (0x8f) */
985 #define RT5682_RAMP_MASK (0x1 << 12)
986 #define RT5682_RAMP_SFT 12
987 #define RT5682_RAMP_DIS (0x0 << 12)
988 #define RT5682_RAMP_EN (0x1 << 12)
989 #define RT5682_BPS_MASK (0x1 << 11)
990 #define RT5682_BPS_SFT 11
991 #define RT5682_BPS_DIS (0x0 << 11)
992 #define RT5682_BPS_EN (0x1 << 11)
993 #define RT5682_FAST_UPDN_MASK (0x1 << 10)
994 #define RT5682_FAST_UPDN_SFT 10
995 #define RT5682_FAST_UPDN_DIS (0x0 << 10)
996 #define RT5682_FAST_UPDN_EN (0x1 << 10)
997 #define RT5682_VLO_MASK (0x1 << 7)
998 #define RT5682_VLO_SFT 7
999 #define RT5682_VLO_3V (0x0 << 7)
1000 #define RT5682_VLO_33V (0x1 << 7)
1001
1002 /* HPOUT charge pump 1 (0x0091) */
1003 #define RT5682_OSW_L_MASK (0x1 << 11)
1004 #define RT5682_OSW_L_SFT 11
1005 #define RT5682_OSW_L_DIS (0x0 << 11)
1006 #define RT5682_OSW_L_EN (0x1 << 11)
1007 #define RT5682_OSW_R_MASK (0x1 << 10)
1008 #define RT5682_OSW_R_SFT 10
1009 #define RT5682_OSW_R_DIS (0x0 << 10)
1010 #define RT5682_OSW_R_EN (0x1 << 10)
1011 #define RT5682_PM_HP_MASK (0x3 << 8)
1012 #define RT5682_PM_HP_SFT 8
1013 #define RT5682_PM_HP_LV (0x0 << 8)
1014 #define RT5682_PM_HP_MV (0x1 << 8)
1015 #define RT5682_PM_HP_HV (0x2 << 8)
1016 #define RT5682_IB_HP_MASK (0x3 << 6)
1017 #define RT5682_IB_HP_SFT 6
1018 #define RT5682_IB_HP_125IL (0x0 << 6)
1019 #define RT5682_IB_HP_25IL (0x1 << 6)
1020 #define RT5682_IB_HP_5IL (0x2 << 6)
1021 #define RT5682_IB_HP_1IL (0x3 << 6)
1022
1023 /* Micbias Control1 (0x93) */
1024 #define RT5682_MIC1_OV_MASK (0x3 << 14)
1025 #define RT5682_MIC1_OV_SFT 14
1026 #define RT5682_MIC1_OV_2V7 (0x0 << 14)
1027 #define RT5682_MIC1_OV_2V4 (0x1 << 14)
1028 #define RT5682_MIC1_OV_2V25 (0x3 << 14)
1029 #define RT5682_MIC1_OV_1V8 (0x4 << 14)
1030 #define RT5682_MIC1_CLK_MASK (0x1 << 13)
1031 #define RT5682_MIC1_CLK_SFT 13
1032 #define RT5682_MIC1_CLK_DIS (0x0 << 13)
1033 #define RT5682_MIC1_CLK_EN (0x1 << 13)
1034 #define RT5682_MIC1_OVCD_MASK (0x1 << 12)
1035 #define RT5682_MIC1_OVCD_SFT 12
1036 #define RT5682_MIC1_OVCD_DIS (0x0 << 12)
1037 #define RT5682_MIC1_OVCD_EN (0x1 << 12)
1038 #define RT5682_MIC1_OVTH_MASK (0x3 << 10)
1039 #define RT5682_MIC1_OVTH_SFT 10
1040 #define RT5682_MIC1_OVTH_768UA (0x0 << 10)
1041 #define RT5682_MIC1_OVTH_960UA (0x1 << 10)
1042 #define RT5682_MIC1_OVTH_1152UA (0x2 << 10)
1043 #define RT5682_MIC1_OVTH_1960UA (0x3 << 10)
1044 #define RT5682_MIC2_OV_MASK (0x3 << 8)
1045 #define RT5682_MIC2_OV_SFT 8
1046 #define RT5682_MIC2_OV_2V7 (0x0 << 8)
1047 #define RT5682_MIC2_OV_2V4 (0x1 << 8)
1048 #define RT5682_MIC2_OV_2V25 (0x3 << 8)
1049 #define RT5682_MIC2_OV_1V8 (0x4 << 8)
1050 #define RT5682_MIC2_CLK_MASK (0x1 << 7)
1051 #define RT5682_MIC2_CLK_SFT 7
1052 #define RT5682_MIC2_CLK_DIS (0x0 << 7)
1053 #define RT5682_MIC2_CLK_EN (0x1 << 7)
1054 #define RT5682_MIC2_OVTH_MASK (0x3 << 4)
1055 #define RT5682_MIC2_OVTH_SFT 4
1056 #define RT5682_MIC2_OVTH_768UA (0x0 << 4)
1057 #define RT5682_MIC2_OVTH_960UA (0x1 << 4)
1058 #define RT5682_MIC2_OVTH_1152UA (0x2 << 4)
1059 #define RT5682_MIC2_OVTH_1960UA (0x3 << 4)
1060 #define RT5682_PWR_MB_MASK (0x1 << 3)
1061 #define RT5682_PWR_MB_SFT 3
1062 #define RT5682_PWR_MB_PD (0x0 << 3)
1063 #define RT5682_PWR_MB_PU (0x1 << 3)
1064
1065 /* Micbias Control2 (0x0094) */
1066 #define RT5682_PWR_CLK25M_MASK (0x1 << 9)
1067 #define RT5682_PWR_CLK25M_SFT 9
1068 #define RT5682_PWR_CLK25M_PD (0x0 << 9)
1069 #define RT5682_PWR_CLK25M_PU (0x1 << 9)
1070 #define RT5682_PWR_CLK1M_MASK (0x1 << 8)
1071 #define RT5682_PWR_CLK1M_SFT 8
1072 #define RT5682_PWR_CLK1M_PD (0x0 << 8)
1073 #define RT5682_PWR_CLK1M_PU (0x1 << 8)
1074
1075 /* PLL2 M/N/K Code Control 1 (0x009b) */
1076 #define RT5682_PLL2F_K_MASK (0x1f << 8)
1077 #define RT5682_PLL2F_K_SFT 8
1078 #define RT5682_PLL2B_K_MASK (0xf << 4)
1079 #define RT5682_PLL2B_K_SFT 4
1080 #define RT5682_PLL2B_M_MASK (0xf << 0)
1081
1082 /* PLL2 M/N/K Code Control 2 (0x009c) */
1083 #define RT5682_PLL2F_M_MASK (0x3f << 8)
1084 #define RT5682_PLL2F_M_SFT 8
1085 #define RT5682_PLL2B_N_MASK (0x3f << 0)
1086
1087 /* PLL2 M/N/K Code Control 2 (0x009d) */
1088 #define RT5682_PLL2F_N_MASK (0x7f << 8)
1089 #define RT5682_PLL2F_N_SFT 8
1090
1091 /* PLL2 M/N/K Code Control 2 (0x009e) */
1092 #define RT5682_PLL2B_SEL_PS_MASK (0x1 << 13)
1093 #define RT5682_PLL2B_SEL_PS_SFT 13
1094 #define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12)
1095 #define RT5682_PLL2B_PS_BYP_SFT 12
1096 #define RT5682_PLL2B_M_BP_MASK (0x1 << 11)
1097 #define RT5682_PLL2B_M_BP_SFT 11
1098 #define RT5682_PLL2F_M_BP_MASK (0x1 << 7)
1099 #define RT5682_PLL2F_M_BP_SFT 7
1100
1101 /* RC Clock Control (0x009f) */
1102 #define RT5682_POW_IRQ (0x1 << 15)
1103 #define RT5682_POW_JDH (0x1 << 14)
1104 #define RT5682_POW_JDL (0x1 << 13)
1105 #define RT5682_POW_ANA (0x1 << 12)
1106
1107 /* I2S Master Mode Clock Control 1 (0x00a0) */
1108 #define RT5682_CLK_SRC_MCLK (0x0)
1109 #define RT5682_CLK_SRC_PLL1 (0x1)
1110 #define RT5682_CLK_SRC_PLL2 (0x2)
1111 #define RT5682_CLK_SRC_SDW (0x3)
1112 #define RT5682_CLK_SRC_RCCLK (0x4)
1113 #define RT5682_I2S_PD_1 (0x0)
1114 #define RT5682_I2S_PD_2 (0x1)
1115 #define RT5682_I2S_PD_3 (0x2)
1116 #define RT5682_I2S_PD_4 (0x3)
1117 #define RT5682_I2S_PD_6 (0x4)
1118 #define RT5682_I2S_PD_8 (0x5)
1119 #define RT5682_I2S_PD_12 (0x6)
1120 #define RT5682_I2S_PD_16 (0x7)
1121 #define RT5682_I2S_PD_24 (0x8)
1122 #define RT5682_I2S_PD_32 (0x9)
1123 #define RT5682_I2S_PD_48 (0xa)
1124 #define RT5682_I2S2_SRC_MASK (0x3 << 4)
1125 #define RT5682_I2S2_SRC_SFT 4
1126 #define RT5682_I2S2_M_PD_MASK (0xf << 0)
1127 #define RT5682_I2S2_M_PD_SFT 0
1128
1129 /* IRQ Control 1 (0x00b6) */
1130 #define RT5682_JD1_PULSE_EN_MASK (0x1 << 10)
1131 #define RT5682_JD1_PULSE_EN_SFT 10
1132 #define RT5682_JD1_PULSE_DIS (0x0 << 10)
1133 #define RT5682_JD1_PULSE_EN (0x1 << 10)
1134
1135 /* IRQ Control 2 (0x00b7) */
1136 #define RT5682_JD1_EN_MASK (0x1 << 15)
1137 #define RT5682_JD1_EN_SFT 15
1138 #define RT5682_JD1_DIS (0x0 << 15)
1139 #define RT5682_JD1_EN (0x1 << 15)
1140 #define RT5682_JD1_POL_MASK (0x1 << 13)
1141 #define RT5682_JD1_POL_NOR (0x0 << 13)
1142 #define RT5682_JD1_POL_INV (0x1 << 13)
1143 #define RT5682_JD1_IRQ_MASK (0x1 << 10)
1144 #define RT5682_JD1_IRQ_LEV (0x0 << 10)
1145 #define RT5682_JD1_IRQ_PUL (0x1 << 10)
1146
1147 /* IRQ Control 3 (0x00b8) */
1148 #define RT5682_IL_IRQ_MASK (0x1 << 7)
1149 #define RT5682_IL_IRQ_DIS (0x0 << 7)
1150 #define RT5682_IL_IRQ_EN (0x1 << 7)
1151 #define RT5682_IL_IRQ_TYPE_MASK (0x1 << 4)
1152 #define RT5682_IL_IRQ_LEV (0x0 << 4)
1153 #define RT5682_IL_IRQ_PUL (0x1 << 4)
1154
1155 /* GPIO Control 1 (0x00c0) */
1156 #define RT5682_GP1_PIN_MASK (0x3 << 14)
1157 #define RT5682_GP1_PIN_SFT 14
1158 #define RT5682_GP1_PIN_GPIO1 (0x0 << 14)
1159 #define RT5682_GP1_PIN_IRQ (0x1 << 14)
1160 #define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14)
1161 #define RT5682_GP2_PIN_MASK (0x3 << 12)
1162 #define RT5682_GP2_PIN_SFT 12
1163 #define RT5682_GP2_PIN_GPIO2 (0x0 << 12)
1164 #define RT5682_GP2_PIN_LRCK2 (0x1 << 12)
1165 #define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12)
1166 #define RT5682_GP3_PIN_MASK (0x3 << 10)
1167 #define RT5682_GP3_PIN_SFT 10
1168 #define RT5682_GP3_PIN_GPIO3 (0x0 << 10)
1169 #define RT5682_GP3_PIN_BCLK2 (0x1 << 10)
1170 #define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10)
1171 #define RT5682_GP4_PIN_MASK (0x3 << 8)
1172 #define RT5682_GP4_PIN_SFT 8
1173 #define RT5682_GP4_PIN_GPIO4 (0x0 << 8)
1174 #define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8)
1175 #define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8)
1176 #define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8)
1177 #define RT5682_GP5_PIN_MASK (0x3 << 6)
1178 #define RT5682_GP5_PIN_SFT 6
1179 #define RT5682_GP5_PIN_GPIO5 (0x0 << 6)
1180 #define RT5682_GP5_PIN_DACDAT1 (0x1 << 6)
1181 #define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6)
1182 #define RT5682_GP6_PIN_MASK (0x1 << 5)
1183 #define RT5682_GP6_PIN_SFT 5
1184 #define RT5682_GP6_PIN_GPIO6 (0x0 << 5)
1185 #define RT5682_GP6_PIN_LRCK1 (0x1 << 5)
1186
1187 /* GPIO Control 2 (0x00c1)*/
1188 #define RT5682_GP1_PF_MASK (0x1 << 15)
1189 #define RT5682_GP1_PF_IN (0x0 << 15)
1190 #define RT5682_GP1_PF_OUT (0x1 << 15)
1191 #define RT5682_GP1_OUT_MASK (0x1 << 14)
1192 #define RT5682_GP1_OUT_L (0x0 << 14)
1193 #define RT5682_GP1_OUT_H (0x1 << 14)
1194 #define RT5682_GP2_PF_MASK (0x1 << 13)
1195 #define RT5682_GP2_PF_IN (0x0 << 13)
1196 #define RT5682_GP2_PF_OUT (0x1 << 13)
1197 #define RT5682_GP2_OUT_MASK (0x1 << 12)
1198 #define RT5682_GP2_OUT_L (0x0 << 12)
1199 #define RT5682_GP2_OUT_H (0x1 << 12)
1200 #define RT5682_GP3_PF_MASK (0x1 << 11)
1201 #define RT5682_GP3_PF_IN (0x0 << 11)
1202 #define RT5682_GP3_PF_OUT (0x1 << 11)
1203 #define RT5682_GP3_OUT_MASK (0x1 << 10)
1204 #define RT5682_GP3_OUT_L (0x0 << 10)
1205 #define RT5682_GP3_OUT_H (0x1 << 10)
1206 #define RT5682_GP4_PF_MASK (0x1 << 9)
1207 #define RT5682_GP4_PF_IN (0x0 << 9)
1208 #define RT5682_GP4_PF_OUT (0x1 << 9)
1209 #define RT5682_GP4_OUT_MASK (0x1 << 8)
1210 #define RT5682_GP4_OUT_L (0x0 << 8)
1211 #define RT5682_GP4_OUT_H (0x1 << 8)
1212 #define RT5682_GP5_PF_MASK (0x1 << 7)
1213 #define RT5682_GP5_PF_IN (0x0 << 7)
1214 #define RT5682_GP5_PF_OUT (0x1 << 7)
1215 #define RT5682_GP5_OUT_MASK (0x1 << 6)
1216 #define RT5682_GP5_OUT_L (0x0 << 6)
1217 #define RT5682_GP5_OUT_H (0x1 << 6)
1218 #define RT5682_GP6_PF_MASK (0x1 << 5)
1219 #define RT5682_GP6_PF_IN (0x0 << 5)
1220 #define RT5682_GP6_PF_OUT (0x1 << 5)
1221 #define RT5682_GP6_OUT_MASK (0x1 << 4)
1222 #define RT5682_GP6_OUT_L (0x0 << 4)
1223 #define RT5682_GP6_OUT_H (0x1 << 4)
1224
1225
1226 /* GPIO Status (0x00c2) */
1227 #define RT5682_GP6_STA (0x1 << 6)
1228 #define RT5682_GP5_STA (0x1 << 5)
1229 #define RT5682_GP4_STA (0x1 << 4)
1230 #define RT5682_GP3_STA (0x1 << 3)
1231 #define RT5682_GP2_STA (0x1 << 2)
1232 #define RT5682_GP1_STA (0x1 << 1)
1233
1234 /* Soft volume and zero cross control 1 (0x00d9) */
1235 #define RT5682_SV_MASK (0x1 << 15)
1236 #define RT5682_SV_SFT 15
1237 #define RT5682_SV_DIS (0x0 << 15)
1238 #define RT5682_SV_EN (0x1 << 15)
1239 #define RT5682_ZCD_MASK (0x1 << 10)
1240 #define RT5682_ZCD_SFT 10
1241 #define RT5682_ZCD_PD (0x0 << 10)
1242 #define RT5682_ZCD_PU (0x1 << 10)
1243 #define RT5682_SV_DLY_MASK (0xf)
1244 #define RT5682_SV_DLY_SFT 0
1245
1246 /* Soft volume and zero cross control 2 (0x00da) */
1247 #define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7)
1248 #define RT5682_ZCD_BST1_CBJ_SFT 7
1249 #define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7)
1250 #define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7)
1251 #define RT5682_ZCD_RECMIX_MASK (0x1)
1252 #define RT5682_ZCD_RECMIX_SFT 0
1253 #define RT5682_ZCD_RECMIX_DIS (0x0)
1254 #define RT5682_ZCD_RECMIX_EN (0x1)
1255
1256 /* 4 Button Inline Command Control 2 (0x00e3) */
1257 #define RT5682_4BTN_IL_MASK (0x1 << 15)
1258 #define RT5682_4BTN_IL_EN (0x1 << 15)
1259 #define RT5682_4BTN_IL_DIS (0x0 << 15)
1260 #define RT5682_4BTN_IL_RST_MASK (0x1 << 14)
1261 #define RT5682_4BTN_IL_NOR (0x1 << 14)
1262 #define RT5682_4BTN_IL_RST (0x0 << 14)
1263
1264 /* Analog JD Control (0x00f0) */
1265 #define RT5682_JDH_RS_MASK (0x1 << 4)
1266 #define RT5682_JDH_NO_PLUG (0x1 << 4)
1267 #define RT5682_JDH_PLUG (0x0 << 4)
1268
1269 /* Bias current control 8 (0x0111) */
1270 #define RT5682_HPA_CP_BIAS_CTRL_MASK (0x3 << 2)
1271 #define RT5682_HPA_CP_BIAS_2UA (0x0 << 2)
1272 #define RT5682_HPA_CP_BIAS_3UA (0x1 << 2)
1273 #define RT5682_HPA_CP_BIAS_4UA (0x2 << 2)
1274 #define RT5682_HPA_CP_BIAS_6UA (0x3 << 2)
1275
1276 /* Charge Pump Internal Register1 (0x0125) */
1277 #define RT5682_CP_SW_SIZE_MASK (0x7 << 8)
1278 #define RT5682_CP_SW_SIZE_L (0x4 << 8)
1279 #define RT5682_CP_SW_SIZE_M (0x2 << 8)
1280 #define RT5682_CP_SW_SIZE_S (0x1 << 8)
1281 #define RT5682_CP_CLK_HP_MASK (0x3 << 4)
1282 #define RT5682_CP_CLK_HP_100KHZ (0x0 << 4)
1283 #define RT5682_CP_CLK_HP_200KHZ (0x1 << 4)
1284 #define RT5682_CP_CLK_HP_300KHZ (0x2 << 4)
1285 #define RT5682_CP_CLK_HP_600KHZ (0x3 << 4)
1286
1287 /* Pad Driving Control (0x0136) */
1288 #define RT5682_PAD_DRV_GP1_MASK (0x3 << 14)
1289 #define RT5682_PAD_DRV_GP1_SFT 14
1290 #define RT5682_PAD_DRV_GP2_MASK (0x3 << 12)
1291 #define RT5682_PAD_DRV_GP2_SFT 12
1292 #define RT5682_PAD_DRV_GP3_MASK (0x3 << 10)
1293 #define RT5682_PAD_DRV_GP3_SFT 10
1294 #define RT5682_PAD_DRV_GP4_MASK (0x3 << 8)
1295 #define RT5682_PAD_DRV_GP4_SFT 8
1296 #define RT5682_PAD_DRV_GP5_MASK (0x3 << 6)
1297 #define RT5682_PAD_DRV_GP5_SFT 6
1298 #define RT5682_PAD_DRV_GP6_MASK (0x3 << 4)
1299 #define RT5682_PAD_DRV_GP6_SFT 4
1300
1301 /* Chopper and Clock control for DAC (0x013a)*/
1302 #define RT5682_CKXEN_DAC1_MASK (0x1 << 13)
1303 #define RT5682_CKXEN_DAC1_SFT 13
1304 #define RT5682_CKGEN_DAC1_MASK (0x1 << 12)
1305 #define RT5682_CKGEN_DAC1_SFT 12
1306
1307 /* Chopper and Clock control for ADC (0x013b)*/
1308 #define RT5682_CKXEN_ADC1_MASK (0x1 << 13)
1309 #define RT5682_CKXEN_ADC1_SFT 13
1310 #define RT5682_CKGEN_ADC1_MASK (0x1 << 12)
1311 #define RT5682_CKGEN_ADC1_SFT 12
1312
1313 /* Volume test (0x013f)*/
1314 #define RT5682_SEL_CLK_VOL_MASK (0x1 << 15)
1315 #define RT5682_SEL_CLK_VOL_EN (0x1 << 15)
1316 #define RT5682_SEL_CLK_VOL_DIS (0x0 << 15)
1317
1318 /* Test Mode Control 1 (0x0145) */
1319 #define RT5682_AD2DA_LB_MASK (0x1 << 10)
1320 #define RT5682_AD2DA_LB_SFT 10
1321
1322 /* Stereo Noise Gate Control 1 (0x0160) */
1323 #define RT5682_NG2_EN_MASK (0x1 << 15)
1324 #define RT5682_NG2_EN (0x1 << 15)
1325 #define RT5682_NG2_DIS (0x0 << 15)
1326
1327 /* Stereo1 DAC Silence Detection Control (0x0190) */
1328 #define RT5682_DEB_STO_DAC_MASK (0x7 << 4)
1329 #define RT5682_DEB_80_MS (0x0 << 4)
1330
1331 /* HP Behavior Logic Control 2 (0x01db) */
1332 #define RT5682_HP_LC2_SIG_SOUR2_MASK (0x1 << 4)
1333 #define RT5682_HP_LC2_SIG_SOUR2_REG (0x1 << 4)
1334 #define RT5682_HP_LC2_SIG_SOUR2_DC_CAL (0x0 << 4)
1335 #define RT5682_HP_LC2_SIG_SOUR1_MASK (0x7)
1336 #define RT5682_HP_LC2_SIG_SOUR1_1BIT (0x7)
1337 #define RT5682_HP_LC2_SIG_SOUR1_LEGA (0x2)
1338
1339 /* SAR ADC Inline Command Control 1 (0x0210) */
1340 #define RT5682_SAR_BUTT_DET_MASK (0x1 << 15)
1341 #define RT5682_SAR_BUTT_DET_EN (0x1 << 15)
1342 #define RT5682_SAR_BUTT_DET_DIS (0x0 << 15)
1343 #define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14)
1344 #define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14)
1345 #define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14)
1346 #define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13)
1347 #define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1348 #define RT5682_SAR_BUTDET_RST (0x0 << 13)
1349 #define RT5682_SAR_POW_MASK (0x1 << 12)
1350 #define RT5682_SAR_POW_EN (0x1 << 12)
1351 #define RT5682_SAR_POW_DIS (0x0 << 12)
1352 #define RT5682_SAR_RST_MASK (0x1 << 11)
1353 #define RT5682_SAR_RST_NORMAL (0x1 << 11)
1354 #define RT5682_SAR_RST (0x0 << 11)
1355 #define RT5682_SAR_BYPASS_MASK (0x1 << 10)
1356 #define RT5682_SAR_BYPASS_EN (0x1 << 10)
1357 #define RT5682_SAR_BYPASS_DIS (0x0 << 10)
1358 #define RT5682_SAR_SEL_MB1_MASK (0x1 << 9)
1359 #define RT5682_SAR_SEL_MB1_SEL (0x1 << 9)
1360 #define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9)
1361 #define RT5682_SAR_SEL_MB2_MASK (0x1 << 8)
1362 #define RT5682_SAR_SEL_MB2_SEL (0x1 << 8)
1363 #define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8)
1364 #define RT5682_SAR_SEL_MODE_MASK (0x1 << 7)
1365 #define RT5682_SAR_SEL_MODE_CMP (0x1 << 7)
1366 #define RT5682_SAR_SEL_MODE_ADC (0x0 << 7)
1367 #define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
1368 #define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
1369 #define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
1370 #define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1371 #define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1372 #define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1373
1374 /* SAR ADC Inline Command Control 13 (0x021c) */
1375 #define RT5682_SAR_SOUR_MASK (0x3f)
1376 #define RT5682_SAR_SOUR_BTN (0x3f)
1377 #define RT5682_SAR_SOUR_TYPE (0x0)
1378
1379 /* soundwire timeout */
1380 #define RT5682_PROBE_TIMEOUT 5000
1381
1382
1383 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1384 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1385 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1386
1387 /* System Clock Source */
1388 enum {
1389 RT5682_SCLK_S_MCLK,
1390 RT5682_SCLK_S_PLL1,
1391 RT5682_SCLK_S_PLL2,
1392 RT5682_SCLK_S_RCCLK,
1393 };
1394
1395 /* PLL Source */
1396 enum {
1397 RT5682_PLL1_S_MCLK,
1398 RT5682_PLL1_S_BCLK1,
1399 RT5682_PLL1_S_RCCLK,
1400 RT5682_PLL2_S_MCLK,
1401 };
1402
1403 enum {
1404 RT5682_PLL1,
1405 RT5682_PLL2,
1406 RT5682_PLLS,
1407 };
1408
1409 enum {
1410 RT5682_AIF1,
1411 RT5682_AIF2,
1412 RT5682_SDW,
1413 RT5682_AIFS
1414 };
1415
1416 /* filter mask */
1417 enum {
1418 RT5682_DA_STEREO1_FILTER = 0x1,
1419 RT5682_AD_STEREO1_FILTER = (0x1 << 1),
1420 };
1421
1422 enum {
1423 RT5682_CLK_SEL_SYS,
1424 RT5682_CLK_SEL_I2S1_ASRC,
1425 RT5682_CLK_SEL_I2S2_ASRC,
1426 };
1427
1428 #define RT5682_NUM_SUPPLIES 5
1429
1430 struct rt5682_priv {
1431 struct snd_soc_component *component;
1432 struct device *i2c_dev;
1433 struct rt5682_platform_data pdata;
1434 struct gpio_desc *ldo1_en;
1435 struct regmap *regmap;
1436 struct regmap *sdw_regmap;
1437 struct snd_soc_jack *hs_jack;
1438 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
1439 struct delayed_work jack_detect_work;
1440 struct delayed_work jd_check_work;
1441 struct mutex disable_irq_lock; /* imp-def irq lock protection */
1442 bool disable_irq;
1443 struct mutex calibrate_mutex;
1444 struct sdw_slave *slave;
1445 struct sdw_bus_params params;
1446 bool hw_init;
1447 bool first_hw_init;
1448 bool is_sdw;
1449
1450 #ifdef CONFIG_COMMON_CLK
1451 struct clk_hw dai_clks_hw[RT5682_DAI_NUM_CLKS];
1452 struct clk *mclk;
1453 #endif
1454
1455 int sysclk;
1456 int sysclk_src;
1457 int lrck[RT5682_AIFS];
1458 int bclk[RT5682_AIFS];
1459 int master[RT5682_AIFS];
1460
1461 int pll_src[RT5682_PLLS];
1462 int pll_in[RT5682_PLLS];
1463 int pll_out[RT5682_PLLS];
1464
1465 int jack_type;
1466 int irq;
1467 int irq_work_delay_time;
1468 };
1469
1470 extern const char *rt5682_supply_names[RT5682_NUM_SUPPLIES];
1471
1472 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
1473 unsigned int filter_mask, unsigned int clk_src);
1474
1475 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev);
1476
1477 void rt5682_jack_detect_handler(struct work_struct *work);
1478
1479 bool rt5682_volatile_register(struct device *dev, unsigned int reg);
1480 bool rt5682_readable_register(struct device *dev, unsigned int reg);
1481
1482 int rt5682_register_component(struct device *dev);
1483 void rt5682_calibrate(struct rt5682_priv *rt5682);
1484 void rt5682_reset(struct rt5682_priv *rt5682);
1485 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev);
1486 int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev);
1487
1488 int rt5682_register_dai_clks(struct rt5682_priv *rt5682);
1489
1490 #define RT5682_REG_NUM 318
1491 extern const struct reg_default rt5682_reg[RT5682_REG_NUM];
1492
1493 extern const struct snd_soc_dai_ops rt5682_aif1_dai_ops;
1494 extern const struct snd_soc_dai_ops rt5682_aif2_dai_ops;
1495 extern const struct snd_soc_component_driver rt5682_soc_component_dev;
1496
1497 #endif /* __RT5682_H__ */
1498
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