1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * rt722-sdca-sdw.h -- RT722 SDCA ALSA SoC audio driver header
4 *
5 * Copyright(c) 2023 Realtek Semiconductor Corp.
6 */
7
8 #ifndef __RT722_SDW_H__
9 #define __RT722_SDW_H__
10
11 #include <linux/regmap.h>
12 #include <linux/soundwire/sdw_registers.h>
13
14 static const struct reg_default rt722_sdca_reg_defaults[] = {
15 { 0x202d, 0x00 },
16 { 0x2f01, 0x00 },
17 { 0x2f02, 0x09 },
18 { 0x2f03, 0x00 },
19 { 0x2f04, 0x00 },
20 { 0x2f05, 0x0b },
21 { 0x2f06, 0x01 },
22 { 0x2f08, 0x00 },
23 { 0x2f09, 0x00 },
24 { 0x2f0a, 0x00 },
25 { 0x2f35, 0x00 },
26 { 0x2f36, 0x00 },
27 { 0x2f50, 0xf0 },
28 { 0x2f58, 0x07 },
29 { 0x2f59, 0x07 },
30 { 0x2f5a, 0x07 },
31 { 0x2f5b, 0x07 },
32 { 0x2f5c, 0x27 },
33 { 0x2f5d, 0x07 },
34 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
35 0), 0x09 },
36 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
37 0), 0x09 },
38 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_REQ_POWER_STATE,
39 0), 0x03 },
40 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_REQ_POWER_STATE,
41 0), 0x03 },
42 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_L),
43 0x01 },
44 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_R),
45 0x01 },
46 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_L),
47 0x01 },
48 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_R),
49 0x01 },
50 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
51 0), 0x09 },
52 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_01),
53 0x01 },
54 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_02),
55 0x01 },
56 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_03),
57 0x01 },
58 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_04),
59 0x01 },
60 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
61 0x03 },
62 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, RT722_SDCA_CTL_VENDOR_DEF, 0),
63 0x00 },
64 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
65 0x09 },
66 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_L),
67 0x01 },
68 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_R),
69 0x01 },
70 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
71 0x03 },
72 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, RT722_SDCA_CTL_VENDOR_DEF, 0), 0x00 },
73 };
74
75 static const struct reg_default rt722_sdca_mbq_defaults[] = {
76 { 0x200003c, 0xc214 },
77 { 0x2000046, 0x8004 },
78 { 0x6100006, 0x0005 },
79 { 0x6100010, 0x2630 },
80 { 0x6100011, 0x152f },
81 { 0x6100013, 0x0102 },
82 { 0x6100015, 0x2200 },
83 { 0x6100017, 0x0102 },
84 { 0x6100025, 0x2a29 },
85 { 0x6100026, 0x2a00 },
86 { 0x6100028, 0x2a2a },
87 { 0x6100029, 0x4141 },
88 { 0x6100055, 0x0000 },
89 { 0x5810000, 0x702d },
90 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
91 CH_L), 0x0000 },
92 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
93 CH_R), 0x0000 },
94 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
95 CH_L), 0x0000 },
96 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
97 CH_R), 0x0000 },
98 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
99 CH_L), 0x0000 },
100 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
101 CH_R), 0x0000 },
102 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
103 CH_01), 0x0000 },
104 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
105 CH_02), 0x0000 },
106 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
107 CH_03), 0x0000 },
108 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
109 CH_04), 0x0000 },
110 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
111 0x0000 },
112 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_02),
113 0x0000 },
114 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_03),
115 0x0000 },
116 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_04),
117 0x0000 },
118 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L),
119 0x0000 },
120 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R),
121 0x0000 },
122 };
123
124 #endif /* __RT722_SDW_H__ */
125
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