1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TAS5086 ASoC codec driver
4 *
5 * Copyright (c) 2013 Daniel Mack <zonque@gmail.com>
6 *
7 * TODO:
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
11 *
12 * Note that this chip has a very unusual register layout, specifically
13 * because the registers are of unequal size, and multi-byte registers
14 * require bulk writes to take effect. Regmap does not support that kind
15 * of devices.
16 *
17 * Currently, the driver does not touch any of the registers >= 0x20, so
18 * it doesn't matter because the entire map can be accessed as 8-bit
19 * array. In case more features will be added in the future
20 * that require access to higher registers, the entire regmap H/W I/O
21 * routines have to be open-coded.
22 */
23
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/i2c.h>
29 #include <linux/regmap.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/spi/spi.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/soc.h>
37 #include <sound/tlv.h>
38 #include <sound/tas5086.h>
39
40 #define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
41 SNDRV_PCM_FMTBIT_S20_3LE | \
42 SNDRV_PCM_FMTBIT_S24_3LE)
43
44 #define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
45 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
46 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
47 SNDRV_PCM_RATE_192000)
48
49 /*
50 * TAS5086 registers
51 */
52 #define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */
53 #define TAS5086_CLOCK_RATE(val) (val << 5)
54 #define TAS5086_CLOCK_RATE_MASK (0x7 << 5)
55 #define TAS5086_CLOCK_RATIO(val) (val << 2)
56 #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
57 #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
58 #define TAS5086_CLOCK_VALID (1 << 0)
59
60 #define TAS5086_DEEMPH_MASK 0x03
61 #define TAS5086_SOFT_MUTE_ALL 0x3f
62
63 #define TAS5086_DEV_ID 0x01 /* Device ID register */
64 #define TAS5086_ERROR_STATUS 0x02 /* Error status register */
65 #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */
66 #define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */
67 #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
68 #define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */
69 #define TAS5086_MASTER_VOL 0x07 /* Master volume */
70 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
71 #define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */
72 #define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */
73 #define TAS5086_PWM_START 0x18 /* PWM start register */
74 #define TAS5086_SURROUND 0x19 /* Surround register */
75 #define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */
76 #define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */
77 #define TAS5086_BKNDERR 0x1c
78 #define TAS5086_INPUT_MUX 0x20
79 #define TAS5086_PWM_OUTPUT_MUX 0x25
80
81 #define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX
82
83 #define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7)
84 #define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6)
85 #define TAS5086_PWM_START_CHANNEL_MASK (0x3f)
86
87 /*
88 * Default TAS5086 power-up configuration
89 */
90 static const struct reg_default tas5086_reg_defaults[] = {
91 { 0x00, 0x6c },
92 { 0x01, 0x03 },
93 { 0x02, 0x00 },
94 { 0x03, 0xa0 },
95 { 0x04, 0x05 },
96 { 0x05, 0x60 },
97 { 0x06, 0x00 },
98 { 0x07, 0xff },
99 { 0x08, 0x30 },
100 { 0x09, 0x30 },
101 { 0x0a, 0x30 },
102 { 0x0b, 0x30 },
103 { 0x0c, 0x30 },
104 { 0x0d, 0x30 },
105 { 0x0e, 0xb1 },
106 { 0x0f, 0x00 },
107 { 0x10, 0x02 },
108 { 0x11, 0x00 },
109 { 0x12, 0x00 },
110 { 0x13, 0x00 },
111 { 0x14, 0x00 },
112 { 0x15, 0x00 },
113 { 0x16, 0x00 },
114 { 0x17, 0x00 },
115 { 0x18, 0x3f },
116 { 0x19, 0x00 },
117 { 0x1a, 0x18 },
118 { 0x1b, 0x82 },
119 { 0x1c, 0x05 },
120 };
121
122 static int tas5086_register_size(struct device *dev, unsigned int reg)
123 {
124 switch (reg) {
125 case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR:
126 return 1;
127 case TAS5086_INPUT_MUX:
128 case TAS5086_PWM_OUTPUT_MUX:
129 return 4;
130 }
131
132 dev_err(dev, "Unsupported register address: %d\n", reg);
133 return 0;
134 }
135
136 static bool tas5086_accessible_reg(struct device *dev, unsigned int reg)
137 {
138 switch (reg) {
139 case 0x0f:
140 case 0x11 ... 0x17:
141 case 0x1d ... 0x1f:
142 return false;
143 default:
144 return true;
145 }
146 }
147
148 static bool tas5086_volatile_reg(struct device *dev, unsigned int reg)
149 {
150 switch (reg) {
151 case TAS5086_DEV_ID:
152 case TAS5086_ERROR_STATUS:
153 return true;
154 }
155
156 return false;
157 }
158
159 static bool tas5086_writeable_reg(struct device *dev, unsigned int reg)
160 {
161 return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID);
162 }
163
164 static int tas5086_reg_write(void *context, unsigned int reg,
165 unsigned int value)
166 {
167 struct i2c_client *client = context;
168 unsigned int i, size;
169 uint8_t buf[5];
170 int ret;
171
172 size = tas5086_register_size(&client->dev, reg);
173 if (size == 0)
174 return -EINVAL;
175
176 buf[0] = reg;
177
178 for (i = size; i >= 1; --i) {
179 buf[i] = value;
180 value >>= 8;
181 }
182
183 ret = i2c_master_send(client, buf, size + 1);
184 if (ret == size + 1)
185 return 0;
186 else if (ret < 0)
187 return ret;
188 else
189 return -EIO;
190 }
191
192 static int tas5086_reg_read(void *context, unsigned int reg,
193 unsigned int *value)
194 {
195 struct i2c_client *client = context;
196 uint8_t send_buf, recv_buf[4];
197 struct i2c_msg msgs[2];
198 unsigned int size;
199 unsigned int i;
200 int ret;
201
202 size = tas5086_register_size(&client->dev, reg);
203 if (size == 0)
204 return -EINVAL;
205
206 send_buf = reg;
207
208 msgs[0].addr = client->addr;
209 msgs[0].len = sizeof(send_buf);
210 msgs[0].buf = &send_buf;
211 msgs[0].flags = 0;
212
213 msgs[1].addr = client->addr;
214 msgs[1].len = size;
215 msgs[1].buf = recv_buf;
216 msgs[1].flags = I2C_M_RD;
217
218 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
219 if (ret < 0)
220 return ret;
221 else if (ret != ARRAY_SIZE(msgs))
222 return -EIO;
223
224 *value = 0;
225
226 for (i = 0; i < size; i++) {
227 *value <<= 8;
228 *value |= recv_buf[i];
229 }
230
231 return 0;
232 }
233
234 static const char * const supply_names[] = {
235 "dvdd", "avdd"
236 };
237
238 struct tas5086_private {
239 struct regmap *regmap;
240 unsigned int mclk, sclk;
241 unsigned int format;
242 bool deemph;
243 unsigned int charge_period;
244 unsigned int pwm_start_mid_z;
245 /* Current sample rate for de-emphasis control */
246 int rate;
247 /* GPIO driving Reset pin, if any */
248 struct gpio_desc *reset;
249 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
250 };
251
252 static int tas5086_deemph[] = { 0, 32000, 44100, 48000 };
253
254 static int tas5086_set_deemph(struct snd_soc_component *component)
255 {
256 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
257 int i, val = 0;
258
259 if (priv->deemph) {
260 for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) {
261 if (tas5086_deemph[i] == priv->rate) {
262 val = i;
263 break;
264 }
265 }
266 }
267
268 return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1,
269 TAS5086_DEEMPH_MASK, val);
270 }
271
272 static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol)
274 {
275 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
276 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
277
278 ucontrol->value.integer.value[0] = priv->deemph;
279
280 return 0;
281 }
282
283 static int tas5086_put_deemph(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_value *ucontrol)
285 {
286 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
287 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
288
289 priv->deemph = ucontrol->value.integer.value[0];
290
291 return tas5086_set_deemph(component);
292 }
293
294
295 static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai,
296 int clk_id, unsigned int freq, int dir)
297 {
298 struct snd_soc_component *component = codec_dai->component;
299 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
300
301 switch (clk_id) {
302 case TAS5086_CLK_IDX_MCLK:
303 priv->mclk = freq;
304 break;
305 case TAS5086_CLK_IDX_SCLK:
306 priv->sclk = freq;
307 break;
308 }
309
310 return 0;
311 }
312
313 static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai,
314 unsigned int format)
315 {
316 struct snd_soc_component *component = codec_dai->component;
317 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
318
319 /* The TAS5086 can only be slave to all clocks */
320 if ((format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC) {
321 dev_err(component->dev, "Invalid clocking mode\n");
322 return -EINVAL;
323 }
324
325 /* we need to refer to the data format from hw_params() */
326 priv->format = format;
327
328 return 0;
329 }
330
331 static const int tas5086_sample_rates[] = {
332 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000
333 };
334
335 static const int tas5086_ratios[] = {
336 64, 128, 192, 256, 384, 512
337 };
338
339 static int index_in_array(const int *array, int len, int needle)
340 {
341 int i;
342
343 for (i = 0; i < len; i++)
344 if (array[i] == needle)
345 return i;
346
347 return -ENOENT;
348 }
349
350 static int tas5086_hw_params(struct snd_pcm_substream *substream,
351 struct snd_pcm_hw_params *params,
352 struct snd_soc_dai *dai)
353 {
354 struct snd_soc_component *component = dai->component;
355 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
356 int val;
357 int ret;
358
359 priv->rate = params_rate(params);
360
361 /* Look up the sample rate and refer to the offset in the list */
362 val = index_in_array(tas5086_sample_rates,
363 ARRAY_SIZE(tas5086_sample_rates), priv->rate);
364
365 if (val < 0) {
366 dev_err(component->dev, "Invalid sample rate\n");
367 return -EINVAL;
368 }
369
370 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
371 TAS5086_CLOCK_RATE_MASK,
372 TAS5086_CLOCK_RATE(val));
373 if (ret < 0)
374 return ret;
375
376 /* MCLK / Fs ratio */
377 val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios),
378 priv->mclk / priv->rate);
379 if (val < 0) {
380 dev_err(component->dev, "Invalid MCLK / Fs ratio\n");
381 return -EINVAL;
382 }
383
384 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
385 TAS5086_CLOCK_RATIO_MASK,
386 TAS5086_CLOCK_RATIO(val));
387 if (ret < 0)
388 return ret;
389
390
391 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
392 TAS5086_CLOCK_SCLK_RATIO_48,
393 (priv->sclk == 48 * priv->rate) ?
394 TAS5086_CLOCK_SCLK_RATIO_48 : 0);
395 if (ret < 0)
396 return ret;
397
398 /*
399 * The chip has a very unituitive register mapping and muxes information
400 * about data format and sample depth into the same register, but not on
401 * a logical bit-boundary. Hence, we have to refer to the format passed
402 * in the set_dai_fmt() callback and set up everything from here.
403 *
404 * First, determine the 'base' value, using the format ...
405 */
406 switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
407 case SND_SOC_DAIFMT_RIGHT_J:
408 val = 0x00;
409 break;
410 case SND_SOC_DAIFMT_I2S:
411 val = 0x03;
412 break;
413 case SND_SOC_DAIFMT_LEFT_J:
414 val = 0x06;
415 break;
416 default:
417 dev_err(component->dev, "Invalid DAI format\n");
418 return -EINVAL;
419 }
420
421 /* ... then add the offset for the sample bit depth. */
422 switch (params_width(params)) {
423 case 16:
424 val += 0;
425 break;
426 case 20:
427 val += 1;
428 break;
429 case 24:
430 val += 2;
431 break;
432 default:
433 dev_err(component->dev, "Invalid bit width\n");
434 return -EINVAL;
435 }
436
437 ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val);
438 if (ret < 0)
439 return ret;
440
441 /* clock is considered valid now */
442 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
443 TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID);
444 if (ret < 0)
445 return ret;
446
447 return tas5086_set_deemph(component);
448 }
449
450 static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
451 {
452 struct snd_soc_component *component = dai->component;
453 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
454 unsigned int val = 0;
455
456 if (mute)
457 val = TAS5086_SOFT_MUTE_ALL;
458
459 return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val);
460 }
461
462 static void tas5086_reset(struct tas5086_private *priv)
463 {
464 if (priv->reset) {
465 /* Reset codec - minimum assertion time is 400ns */
466 gpiod_direction_output(priv->reset, 1);
467 udelay(1);
468 gpiod_set_value(priv->reset, 0);
469
470 /* Codec needs ~15ms to wake up */
471 msleep(15);
472 }
473 }
474
475 /* charge period values in microseconds */
476 static const int tas5086_charge_period[] = {
477 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200,
478 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000,
479 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000,
480 };
481
482 static int tas5086_init(struct device *dev, struct tas5086_private *priv)
483 {
484 int ret, i;
485
486 /*
487 * If any of the channels is configured to start in Mid-Z mode,
488 * configure 'part 1' of the PWM starts to use Mid-Z, and tell
489 * all configured mid-z channels to start under 'part 1'.
490 */
491 if (priv->pwm_start_mid_z)
492 regmap_write(priv->regmap, TAS5086_PWM_START,
493 TAS5086_PWM_START_MIDZ_FOR_START_1 |
494 priv->pwm_start_mid_z);
495
496 /* lookup and set split-capacitor charge period */
497 if (priv->charge_period == 0) {
498 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0);
499 } else {
500 i = index_in_array(tas5086_charge_period,
501 ARRAY_SIZE(tas5086_charge_period),
502 priv->charge_period);
503 if (i >= 0)
504 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE,
505 i + 0x08);
506 else
507 dev_warn(dev,
508 "Invalid split-cap charge period of %d ns.\n",
509 priv->charge_period);
510 }
511
512 /* enable factory trim */
513 ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00);
514 if (ret < 0)
515 return ret;
516
517 /* start all channels */
518 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20);
519 if (ret < 0)
520 return ret;
521
522 /* mute all channels for now */
523 ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE,
524 TAS5086_SOFT_MUTE_ALL);
525 if (ret < 0)
526 return ret;
527
528 return 0;
529 }
530
531 /* TAS5086 controls */
532 static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
533
534 static const struct snd_kcontrol_new tas5086_controls[] = {
535 SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL,
536 0, 0xff, 1, tas5086_dac_tlv),
537 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
538 TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1),
539 0, 0xff, 1, tas5086_dac_tlv),
540 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
541 TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3),
542 0, 0xff, 1, tas5086_dac_tlv),
543 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
544 TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5),
545 0, 0xff, 1, tas5086_dac_tlv),
546 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
547 tas5086_get_deemph, tas5086_put_deemph),
548 };
549
550 /* Input mux controls */
551 static const char *tas5086_dapm_sdin_texts[] =
552 {
553 "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
554 "SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
555 };
556
557 static const struct soc_enum tas5086_dapm_input_mux_enum[] = {
558 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts),
559 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts),
560 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts),
561 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts),
562 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts),
563 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts),
564 };
565
566 static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = {
567 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
568 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
569 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
570 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
571 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
572 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
573 };
574
575 /* Output mux controls */
576 static const char *tas5086_dapm_channel_texts[] =
577 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
578 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
579
580 static const struct soc_enum tas5086_dapm_output_mux_enum[] = {
581 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts),
582 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts),
583 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts),
584 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts),
585 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts),
586 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts),
587 };
588
589 static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = {
590 SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]),
591 SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]),
592 SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]),
593 SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]),
594 SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]),
595 SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]),
596 };
597
598 static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = {
599 SND_SOC_DAPM_INPUT("SDIN1-L"),
600 SND_SOC_DAPM_INPUT("SDIN1-R"),
601 SND_SOC_DAPM_INPUT("SDIN2-L"),
602 SND_SOC_DAPM_INPUT("SDIN2-R"),
603 SND_SOC_DAPM_INPUT("SDIN3-L"),
604 SND_SOC_DAPM_INPUT("SDIN3-R"),
605 SND_SOC_DAPM_INPUT("SDIN4-L"),
606 SND_SOC_DAPM_INPUT("SDIN4-R"),
607
608 SND_SOC_DAPM_OUTPUT("PWM1"),
609 SND_SOC_DAPM_OUTPUT("PWM2"),
610 SND_SOC_DAPM_OUTPUT("PWM3"),
611 SND_SOC_DAPM_OUTPUT("PWM4"),
612 SND_SOC_DAPM_OUTPUT("PWM5"),
613 SND_SOC_DAPM_OUTPUT("PWM6"),
614
615 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
616 &tas5086_dapm_input_mux_controls[0]),
617 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
618 &tas5086_dapm_input_mux_controls[1]),
619 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
620 &tas5086_dapm_input_mux_controls[2]),
621 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
622 &tas5086_dapm_input_mux_controls[3]),
623 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
624 &tas5086_dapm_input_mux_controls[4]),
625 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
626 &tas5086_dapm_input_mux_controls[5]),
627
628 SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0,
629 &tas5086_dapm_output_mux_controls[0]),
630 SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0,
631 &tas5086_dapm_output_mux_controls[1]),
632 SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0,
633 &tas5086_dapm_output_mux_controls[2]),
634 SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0,
635 &tas5086_dapm_output_mux_controls[3]),
636 SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0,
637 &tas5086_dapm_output_mux_controls[4]),
638 SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0,
639 &tas5086_dapm_output_mux_controls[5]),
640 };
641
642 static const struct snd_soc_dapm_route tas5086_dapm_routes[] = {
643 /* SDIN inputs -> channel muxes */
644 { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
645 { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
646 { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
647 { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
648 { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
649 { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
650
651 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
652 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
653 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
654 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
655 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
656 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
657
658 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
659 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
660 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
661 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
662 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
663 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
664
665 { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
666 { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
667 { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
668 { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
669 { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
670 { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
671
672 { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
673 { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
674 { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
675 { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
676 { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
677 { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
678
679 { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
680 { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
681 { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
682 { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
683 { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
684 { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
685
686 { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
687 { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
688 { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
689 { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
690 { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
691 { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
692
693 /* Channel muxes -> PWM muxes */
694 { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
695 { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
696 { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
697 { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
698 { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
699 { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
700
701 { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
702 { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
703 { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
704 { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
705 { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
706 { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
707
708 { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
709 { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
710 { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
711 { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
712 { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
713 { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
714
715 { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
716 { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
717 { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
718 { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
719 { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
720 { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
721
722 { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
723 { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
724 { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
725 { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
726 { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
727 { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
728
729 { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
730 { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
731 { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
732 { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
733 { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
734 { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
735
736 /* The PWM muxes are directly connected to the PWM outputs */
737 { "PWM1", NULL, "PWM1 Mux" },
738 { "PWM2", NULL, "PWM2 Mux" },
739 { "PWM3", NULL, "PWM3 Mux" },
740 { "PWM4", NULL, "PWM4 Mux" },
741 { "PWM5", NULL, "PWM5 Mux" },
742 { "PWM6", NULL, "PWM6 Mux" },
743
744 };
745
746 static const struct snd_soc_dai_ops tas5086_dai_ops = {
747 .hw_params = tas5086_hw_params,
748 .set_sysclk = tas5086_set_dai_sysclk,
749 .set_fmt = tas5086_set_dai_fmt,
750 .mute_stream = tas5086_mute_stream,
751 };
752
753 static struct snd_soc_dai_driver tas5086_dai = {
754 .name = "tas5086-hifi",
755 .playback = {
756 .stream_name = "Playback",
757 .channels_min = 2,
758 .channels_max = 6,
759 .rates = TAS5086_PCM_RATES,
760 .formats = TAS5086_PCM_FORMATS,
761 },
762 .ops = &tas5086_dai_ops,
763 };
764
765 #ifdef CONFIG_PM
766 static int tas5086_soc_suspend(struct snd_soc_component *component)
767 {
768 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
769 int ret;
770
771 /* Shut down all channels */
772 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60);
773 if (ret < 0)
774 return ret;
775
776 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
777
778 return 0;
779 }
780
781 static int tas5086_soc_resume(struct snd_soc_component *component)
782 {
783 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
784 int ret;
785
786 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
787 if (ret < 0)
788 return ret;
789
790 tas5086_reset(priv);
791 regcache_mark_dirty(priv->regmap);
792
793 ret = tas5086_init(component->dev, priv);
794 if (ret < 0)
795 return ret;
796
797 ret = regcache_sync(priv->regmap);
798 if (ret < 0)
799 return ret;
800
801 return 0;
802 }
803 #else
804 #define tas5086_soc_suspend NULL
805 #define tas5086_soc_resume NULL
806 #endif /* CONFIG_PM */
807
808 #ifdef CONFIG_OF
809 static const struct of_device_id tas5086_dt_ids[] = {
810 { .compatible = "ti,tas5086", },
811 { }
812 };
813 MODULE_DEVICE_TABLE(of, tas5086_dt_ids);
814 #endif
815
816 static int tas5086_probe(struct snd_soc_component *component)
817 {
818 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
819 int i, ret;
820
821 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
822 if (ret < 0) {
823 dev_err(component->dev, "Failed to enable regulators: %d\n", ret);
824 return ret;
825 }
826
827 priv->pwm_start_mid_z = 0;
828 priv->charge_period = 1300000; /* hardware default is 1300 ms */
829
830 if (of_match_device(of_match_ptr(tas5086_dt_ids), component->dev)) {
831 struct device_node *of_node = component->dev->of_node;
832
833 of_property_read_u32(of_node, "ti,charge-period",
834 &priv->charge_period);
835
836 for (i = 0; i < 6; i++) {
837 char name[25];
838
839 snprintf(name, sizeof(name),
840 "ti,mid-z-channel-%d", i + 1);
841
842 if (of_property_read_bool(of_node, name))
843 priv->pwm_start_mid_z |= 1 << i;
844 }
845 }
846
847 tas5086_reset(priv);
848 ret = tas5086_init(component->dev, priv);
849 if (ret < 0)
850 goto exit_disable_regulators;
851
852 /* set master volume to 0 dB */
853 ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30);
854 if (ret < 0)
855 goto exit_disable_regulators;
856
857 return 0;
858
859 exit_disable_regulators:
860 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
861
862 return ret;
863 }
864
865 static void tas5086_remove(struct snd_soc_component *component)
866 {
867 struct tas5086_private *priv = snd_soc_component_get_drvdata(component);
868
869 if (priv->reset)
870 /* Set codec to the reset state */
871 gpiod_set_value(priv->reset, 1);
872
873 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
874 };
875
876 static const struct snd_soc_component_driver soc_component_dev_tas5086 = {
877 .probe = tas5086_probe,
878 .remove = tas5086_remove,
879 .suspend = tas5086_soc_suspend,
880 .resume = tas5086_soc_resume,
881 .controls = tas5086_controls,
882 .num_controls = ARRAY_SIZE(tas5086_controls),
883 .dapm_widgets = tas5086_dapm_widgets,
884 .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets),
885 .dapm_routes = tas5086_dapm_routes,
886 .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes),
887 .idle_bias_on = 1,
888 .use_pmdown_time = 1,
889 .endianness = 1,
890 };
891
892 static const struct i2c_device_id tas5086_i2c_id[] = {
893 { "tas5086" },
894 { }
895 };
896 MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id);
897
898 static const struct regmap_config tas5086_regmap = {
899 .reg_bits = 8,
900 .val_bits = 32,
901 .max_register = TAS5086_MAX_REGISTER,
902 .reg_defaults = tas5086_reg_defaults,
903 .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults),
904 .cache_type = REGCACHE_RBTREE,
905 .volatile_reg = tas5086_volatile_reg,
906 .writeable_reg = tas5086_writeable_reg,
907 .readable_reg = tas5086_accessible_reg,
908 .reg_read = tas5086_reg_read,
909 .reg_write = tas5086_reg_write,
910 };
911
912 static int tas5086_i2c_probe(struct i2c_client *i2c)
913 {
914 struct tas5086_private *priv;
915 struct device *dev = &i2c->dev;
916 int i, ret;
917
918 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
919 if (!priv)
920 return -ENOMEM;
921
922 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
923 priv->supplies[i].supply = supply_names[i];
924
925 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
926 priv->supplies);
927 if (ret < 0) {
928 dev_err(dev, "Failed to get regulators: %d\n", ret);
929 return ret;
930 }
931
932 priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap);
933 if (IS_ERR(priv->regmap)) {
934 ret = PTR_ERR(priv->regmap);
935 dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
936 return ret;
937 }
938
939 i2c_set_clientdata(i2c, priv);
940
941 /* Request line asserted */
942 priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
943 if (IS_ERR(priv->reset))
944 return PTR_ERR(priv->reset);
945 gpiod_set_consumer_name(priv->reset, "TAS5086 Reset");
946
947 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
948 if (ret < 0) {
949 dev_err(dev, "Failed to enable regulators: %d\n", ret);
950 return ret;
951 }
952
953 tas5086_reset(priv);
954
955 /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */
956 ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i);
957 if (ret == 0 && i != 0x3) {
958 dev_err(dev,
959 "Failed to identify TAS5086 codec (got %02x)\n", i);
960 ret = -ENODEV;
961 }
962
963 /*
964 * The chip has been identified, so we can turn off the power
965 * again until the dai link is set up.
966 */
967 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
968
969 if (ret == 0)
970 ret = devm_snd_soc_register_component(&i2c->dev,
971 &soc_component_dev_tas5086,
972 &tas5086_dai, 1);
973
974 return ret;
975 }
976
977 static void tas5086_i2c_remove(struct i2c_client *i2c)
978 {}
979
980 static struct i2c_driver tas5086_i2c_driver = {
981 .driver = {
982 .name = "tas5086",
983 .of_match_table = of_match_ptr(tas5086_dt_ids),
984 },
985 .id_table = tas5086_i2c_id,
986 .probe = tas5086_i2c_probe,
987 .remove = tas5086_i2c_remove,
988 };
989
990 module_i2c_driver(tas5086_i2c_driver);
991
992 MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>");
993 MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver");
994 MODULE_LICENSE("GPL");
995
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