1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3
4 #include <linux/component.h>
5 #include <linux/delay.h>
6 #include <linux/device.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of_gpio.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <sound/jack.h>
18 #include <sound/pcm_params.h>
19 #include <sound/pcm.h>
20 #include <sound/soc-dapm.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23
24 #include "wcd-clsh-v2.h"
25 #include "wcd-mbhc-v2.h"
26 #include "wcd937x.h"
27
28 enum {
29 CHIPID_WCD9370 = 0,
30 CHIPID_WCD9375 = 5,
31 };
32
33 /* Z value defined in milliohm */
34 #define WCD937X_ZDET_VAL_32 (32000)
35 #define WCD937X_ZDET_VAL_400 (400000)
36 #define WCD937X_ZDET_VAL_1200 (1200000)
37 #define WCD937X_ZDET_VAL_100K (100000000)
38 /* Z floating defined in ohms */
39 #define WCD937X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
40 #define WCD937X_ZDET_NUM_MEASUREMENTS (900)
41 #define WCD937X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14)
42 #define WCD937X_MBHC_GET_X1(x) ((x) & 0x3FFF)
43 /* Z value compared in milliOhm */
44 #define WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z) (((z) > 400000) || ((z) < 32000))
45 #define WCD937X_MBHC_ZDET_CONST (86 * 16384)
46 #define WCD937X_MBHC_MOISTURE_RREF R_24_KOHM
47 #define WCD_MBHC_HS_V_MAX 1600
48 #define EAR_RX_PATH_AUX 1
49 #define WCD937X_MBHC_MAX_BUTTONS 8
50
51 #define WCD937X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
52 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
53 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
54 SNDRV_PCM_RATE_384000)
55
56 /* Fractional Rates */
57 #define WCD937X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
58 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
59
60 #define WCD937X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |\
61 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
62
63 enum {
64 ALLOW_BUCK_DISABLE,
65 HPH_COMP_DELAY,
66 HPH_PA_DELAY,
67 AMIC2_BCS_ENABLE,
68 };
69
70 enum {
71 AIF1_PB = 0,
72 AIF1_CAP,
73 NUM_CODEC_DAIS,
74 };
75
76 struct wcd937x_priv {
77 struct sdw_slave *tx_sdw_dev;
78 struct wcd937x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
79 struct device *txdev;
80 struct device *rxdev;
81 struct device_node *rxnode;
82 struct device_node *txnode;
83 struct regmap *regmap;
84 /* micb setup lock */
85 struct mutex micb_lock;
86 /* mbhc module */
87 struct wcd_mbhc *wcd_mbhc;
88 struct wcd_mbhc_config mbhc_cfg;
89 struct wcd_mbhc_intr intr_ids;
90 struct wcd_clsh_ctrl *clsh_info;
91 struct irq_domain *virq;
92 struct regmap_irq_chip *wcd_regmap_irq_chip;
93 struct regmap_irq_chip_data *irq_chip;
94 struct regulator_bulk_data supplies[WCD937X_MAX_BULK_SUPPLY];
95 struct regulator *buck_supply;
96 struct snd_soc_jack *jack;
97 unsigned long status_mask;
98 s32 micb_ref[WCD937X_MAX_MICBIAS];
99 s32 pullup_ref[WCD937X_MAX_MICBIAS];
100 u32 hph_mode;
101 int ear_rx_path;
102 u32 micb1_mv;
103 u32 micb2_mv;
104 u32 micb3_mv;
105 int hphr_pdm_wd_int;
106 int hphl_pdm_wd_int;
107 int aux_pdm_wd_int;
108 bool comp1_enable;
109 bool comp2_enable;
110
111 struct gpio_desc *us_euro_gpio;
112 struct gpio_desc *reset_gpio;
113
114 atomic_t rx_clk_cnt;
115 atomic_t ana_clk_count;
116 };
117
118 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
119 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
120 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
121
122 struct wcd937x_mbhc_zdet_param {
123 u16 ldo_ctl;
124 u16 noff;
125 u16 nshift;
126 u16 btn5;
127 u16 btn6;
128 u16 btn7;
129 };
130
131 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
132 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD937X_ANA_MBHC_MECH, 0x80),
133 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD937X_ANA_MBHC_MECH, 0x40),
134 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD937X_ANA_MBHC_MECH, 0x20),
135 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
136 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD937X_ANA_MBHC_ELECT, 0x08),
137 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
138 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD937X_ANA_MBHC_MECH, 0x04),
139 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x10),
140 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD937X_ANA_MBHC_MECH, 0x08),
141 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD937X_ANA_MBHC_MECH, 0x01),
142 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD937X_ANA_MBHC_ELECT, 0x06),
143 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD937X_ANA_MBHC_ELECT, 0x80),
144 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
145 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD937X_MBHC_NEW_CTL_1, 0x03),
146 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD937X_MBHC_NEW_CTL_2, 0x03),
147 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x08),
148 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD937X_ANA_MBHC_RESULT_3, 0x10),
149 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x20),
150 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x80),
151 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x40),
152 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD937X_HPH_OCP_CTL, 0x10),
153 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0x07),
154 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD937X_ANA_MBHC_ELECT, 0x70),
155 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD937X_ANA_MBHC_RESULT_3, 0xFF),
156 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD937X_ANA_MICB2, 0xC0),
157 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD937X_HPH_CNP_WG_TIME, 0xFF),
158 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD937X_ANA_HPH, 0x40),
159 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD937X_ANA_HPH, 0x80),
160 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD937X_ANA_HPH, 0xC0),
161 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD937X_ANA_MBHC_RESULT_3, 0x10),
162 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD937X_MBHC_CTL_BCS, 0x02),
163 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x01),
164 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD937X_MBHC_NEW_CTL_2, 0x70),
165 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD937X_MBHC_NEW_FSM_STATUS, 0x20),
166 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD937X_HPH_PA_CTL2, 0x40),
167 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD937X_HPH_PA_CTL2, 0x10),
168 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD937X_HPH_L_TEST, 0x01),
169 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD937X_HPH_R_TEST, 0x01),
170 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x80),
171 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD937X_DIGITAL_INTR_STATUS_0, 0x20),
172 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD937X_MBHC_NEW_CTL_1, 0x08),
173 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD937X_MBHC_NEW_FSM_STATUS, 0x40),
174 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD937X_MBHC_NEW_FSM_STATUS, 0x80),
175 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD937X_MBHC_NEW_ADC_RESULT, 0xFF),
176 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD937X_ANA_MICB2, 0x3F),
177 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD937X_MBHC_NEW_CTL_1, 0x10),
178 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD937X_MBHC_NEW_CTL_1, 0x04),
179 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD937X_ANA_MBHC_ZDET, 0x02),
180 };
181
182 static const struct regmap_irq wcd937x_irqs[WCD937X_NUM_IRQS] = {
183 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_PRESS_DET, 0, BIT(0)),
184 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, BIT(1)),
185 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_DET, 0, BIT(2)),
186 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, BIT(3)),
187 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_SW_DET, 0, BIT(4)),
188 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_OCP_INT, 0, BIT(5)),
189 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_CNP_INT, 0, BIT(6)),
190 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_OCP_INT, 0, BIT(7)),
191 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_CNP_INT, 1, BIT(0)),
192 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_CNP_INT, 1, BIT(1)),
193 REGMAP_IRQ_REG(WCD937X_IRQ_EAR_SCD_INT, 1, BIT(2)),
194 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_CNP_INT, 1, BIT(3)),
195 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_SCD_INT, 1, BIT(4)),
196 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_PDM_WD_INT, 1, BIT(5)),
197 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_PDM_WD_INT, 1, BIT(6)),
198 REGMAP_IRQ_REG(WCD937X_IRQ_AUX_PDM_WD_INT, 1, BIT(7)),
199 REGMAP_IRQ_REG(WCD937X_IRQ_LDORT_SCD_INT, 2, BIT(0)),
200 REGMAP_IRQ_REG(WCD937X_IRQ_MBHC_MOISTURE_INT, 2, BIT(1)),
201 REGMAP_IRQ_REG(WCD937X_IRQ_HPHL_SURGE_DET_INT, 2, BIT(2)),
202 REGMAP_IRQ_REG(WCD937X_IRQ_HPHR_SURGE_DET_INT, 2, BIT(3)),
203 };
204
205 static int wcd937x_handle_post_irq(void *data)
206 {
207 struct wcd937x_priv *wcd937x;
208
209 if (data)
210 wcd937x = (struct wcd937x_priv *)data;
211 else
212 return IRQ_HANDLED;
213
214 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_0, 0);
215 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_1, 0);
216 regmap_write(wcd937x->regmap, WCD937X_DIGITAL_INTR_CLEAR_2, 0);
217
218 return IRQ_HANDLED;
219 }
220
221 static const u32 wcd937x_config_regs[] = {
222 WCD937X_DIGITAL_INTR_LEVEL_0,
223 };
224
225 static const struct regmap_irq_chip wcd937x_regmap_irq_chip = {
226 .name = "wcd937x",
227 .irqs = wcd937x_irqs,
228 .num_irqs = ARRAY_SIZE(wcd937x_irqs),
229 .num_regs = 3,
230 .status_base = WCD937X_DIGITAL_INTR_STATUS_0,
231 .mask_base = WCD937X_DIGITAL_INTR_MASK_0,
232 .ack_base = WCD937X_DIGITAL_INTR_CLEAR_0,
233 .use_ack = 1,
234 .clear_ack = 1,
235 .config_base = wcd937x_config_regs,
236 .num_config_bases = ARRAY_SIZE(wcd937x_config_regs),
237 .num_config_regs = 1,
238 .runtime_pm = true,
239 .handle_post_irq = wcd937x_handle_post_irq,
240 .irq_drv_data = NULL,
241 };
242
243 static void wcd937x_reset(struct wcd937x_priv *wcd937x)
244 {
245 gpiod_set_value(wcd937x->reset_gpio, 1);
246 usleep_range(20, 30);
247 gpiod_set_value(wcd937x->reset_gpio, 0);
248 usleep_range(20, 30);
249 }
250
251 static void wcd937x_io_init(struct regmap *regmap)
252 {
253 u32 val = 0, temp = 0, temp1 = 0;
254
255 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_29, &val);
256
257 val = val & 0x0F;
258
259 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &temp);
260 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_17, &temp1);
261
262 if (temp == 0x02 || temp1 > 0x09)
263 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0E, val);
264 else
265 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x0e, 0x0e);
266
267 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x80, 0x80);
268 usleep_range(1000, 1010);
269
270 regmap_update_bits(regmap, WCD937X_SLEEP_CTL, 0x40, 0x40);
271 usleep_range(1000, 1010);
272
273 regmap_update_bits(regmap, WCD937X_LDORXTX_CONFIG, BIT(4), 0x00);
274 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xf0, BIT(7));
275 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(7), BIT(7));
276 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), BIT(6));
277 usleep_range(10000, 10010);
278
279 regmap_update_bits(regmap, WCD937X_ANA_BIAS, BIT(6), 0x00);
280 regmap_update_bits(regmap, WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xff, 0xd9);
281 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_1, 0xff, 0xfa);
282 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_1, 0xff, 0xfa);
283 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_1, 0xff, 0xfa);
284
285 regmap_update_bits(regmap, WCD937X_MICB1_TEST_CTL_2, 0x38, 0x00);
286 regmap_update_bits(regmap, WCD937X_MICB2_TEST_CTL_2, 0x38, 0x00);
287 regmap_update_bits(regmap, WCD937X_MICB3_TEST_CTL_2, 0x38, 0x00);
288
289 /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */
290 regmap_read(regmap, WCD937X_DIGITAL_EFUSE_REG_16, &val);
291 if (val == 0x01) {
292 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
293 } else if (val == 0x02) {
294 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04);
295 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04);
296 regmap_update_bits(regmap, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0);
297 regmap_update_bits(regmap, WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xF0, 0x50);
298 }
299 }
300
301 static int wcd937x_rx_clk_enable(struct snd_soc_component *component)
302 {
303 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
304
305 if (atomic_read(&wcd937x->rx_clk_cnt))
306 return 0;
307
308 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(3), BIT(3));
309 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), BIT(0));
310 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), BIT(0));
311 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX0_CTL, BIT(6), 0x00);
312 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX1_CTL, BIT(6), 0x00);
313 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_RX2_CTL, BIT(6), 0x00);
314 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), BIT(1));
315
316 atomic_inc(&wcd937x->rx_clk_cnt);
317
318 return 0;
319 }
320
321 static int wcd937x_rx_clk_disable(struct snd_soc_component *component)
322 {
323 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
324
325 if (!atomic_read(&wcd937x->rx_clk_cnt)) {
326 dev_err(component->dev, "clk already disabled\n");
327 return 0;
328 }
329
330 atomic_dec(&wcd937x->rx_clk_cnt);
331
332 snd_soc_component_update_bits(component, WCD937X_ANA_RX_SUPPLIES, BIT(0), 0x00);
333 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(1), 0x00);
334 snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(0), 0x00);
335
336 return 0;
337 }
338
339 static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
340 struct snd_kcontrol *kcontrol,
341 int event)
342 {
343 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
344 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
345 int hph_mode = wcd937x->hph_mode;
346
347 switch (event) {
348 case SND_SOC_DAPM_PRE_PMU:
349 wcd937x_rx_clk_enable(component);
350 snd_soc_component_update_bits(component,
351 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
352 BIT(0), BIT(0));
353 snd_soc_component_update_bits(component,
354 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
355 BIT(2), BIT(2));
356 snd_soc_component_update_bits(component,
357 WCD937X_HPH_RDAC_CLK_CTL1,
358 BIT(7), 0x00);
359 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
360 break;
361 case SND_SOC_DAPM_POST_PMU:
362 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
363 snd_soc_component_update_bits(component,
364 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
365 0x0f, BIT(1));
366 else if (hph_mode == CLS_H_LOHIFI)
367 snd_soc_component_update_bits(component,
368 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
369 0x0f, 0x06);
370
371 if (wcd937x->comp1_enable) {
372 snd_soc_component_update_bits(component,
373 WCD937X_DIGITAL_CDC_COMP_CTL_0,
374 BIT(1), BIT(1));
375 snd_soc_component_update_bits(component,
376 WCD937X_HPH_L_EN,
377 BIT(5), 0x00);
378
379 if (wcd937x->comp2_enable) {
380 snd_soc_component_update_bits(component,
381 WCD937X_DIGITAL_CDC_COMP_CTL_0,
382 BIT(0), BIT(0));
383 snd_soc_component_update_bits(component,
384 WCD937X_HPH_R_EN, BIT(5), 0x00);
385 }
386
387 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
388 usleep_range(5000, 5110);
389 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
390 }
391 } else {
392 snd_soc_component_update_bits(component,
393 WCD937X_DIGITAL_CDC_COMP_CTL_0,
394 BIT(1), 0x00);
395 snd_soc_component_update_bits(component,
396 WCD937X_HPH_L_EN,
397 BIT(5), BIT(5));
398 }
399
400 snd_soc_component_update_bits(component,
401 WCD937X_HPH_NEW_INT_HPH_TIMER1,
402 BIT(1), 0x00);
403 break;
404 case SND_SOC_DAPM_POST_PMD:
405 snd_soc_component_update_bits(component,
406 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
407 0x0f, BIT(0));
408 break;
409 }
410
411 return 0;
412 }
413
414 static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
415 struct snd_kcontrol *kcontrol,
416 int event)
417 {
418 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
419 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
420 int hph_mode = wcd937x->hph_mode;
421
422 switch (event) {
423 case SND_SOC_DAPM_PRE_PMU:
424 wcd937x_rx_clk_enable(component);
425 snd_soc_component_update_bits(component,
426 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(1), BIT(1));
427 snd_soc_component_update_bits(component,
428 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, BIT(3), BIT(3));
429 snd_soc_component_update_bits(component,
430 WCD937X_HPH_RDAC_CLK_CTL1, BIT(7), 0x00);
431 set_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
432 break;
433 case SND_SOC_DAPM_POST_PMU:
434 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
435 snd_soc_component_update_bits(component,
436 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
437 0x0f, BIT(1));
438 else if (hph_mode == CLS_H_LOHIFI)
439 snd_soc_component_update_bits(component,
440 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
441 0x0f, 0x06);
442 if (wcd937x->comp2_enable) {
443 snd_soc_component_update_bits(component,
444 WCD937X_DIGITAL_CDC_COMP_CTL_0,
445 BIT(0), BIT(0));
446 snd_soc_component_update_bits(component,
447 WCD937X_HPH_R_EN, BIT(5), 0x00);
448 if (wcd937x->comp1_enable) {
449 snd_soc_component_update_bits(component,
450 WCD937X_DIGITAL_CDC_COMP_CTL_0,
451 BIT(1), BIT(1));
452 snd_soc_component_update_bits(component,
453 WCD937X_HPH_L_EN,
454 BIT(5), 0x00);
455 }
456
457 if (test_bit(HPH_COMP_DELAY, &wcd937x->status_mask)) {
458 usleep_range(5000, 5110);
459 clear_bit(HPH_COMP_DELAY, &wcd937x->status_mask);
460 }
461 } else {
462 snd_soc_component_update_bits(component,
463 WCD937X_DIGITAL_CDC_COMP_CTL_0,
464 BIT(0), 0x00);
465 snd_soc_component_update_bits(component,
466 WCD937X_HPH_R_EN,
467 BIT(5), BIT(5));
468 }
469 snd_soc_component_update_bits(component,
470 WCD937X_HPH_NEW_INT_HPH_TIMER1,
471 BIT(1), 0x00);
472 break;
473 case SND_SOC_DAPM_POST_PMD:
474 snd_soc_component_update_bits(component,
475 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R,
476 0x0f, BIT(0));
477 break;
478 }
479
480 return 0;
481 }
482
483 static int wcd937x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
484 struct snd_kcontrol *kcontrol,
485 int event)
486 {
487 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
488 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
489 int hph_mode = wcd937x->hph_mode;
490
491 switch (event) {
492 case SND_SOC_DAPM_PRE_PMU:
493 wcd937x_rx_clk_enable(component);
494 snd_soc_component_update_bits(component,
495 WCD937X_DIGITAL_CDC_HPH_GAIN_CTL,
496 BIT(2), BIT(2));
497 snd_soc_component_update_bits(component,
498 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
499 BIT(0), BIT(0));
500
501 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI)
502 snd_soc_component_update_bits(component,
503 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
504 0x0f, BIT(1));
505 else if (hph_mode == CLS_H_LOHIFI)
506 snd_soc_component_update_bits(component,
507 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
508 0x0f, 0x06);
509 if (wcd937x->comp1_enable)
510 snd_soc_component_update_bits(component,
511 WCD937X_DIGITAL_CDC_COMP_CTL_0,
512 BIT(1), BIT(1));
513 usleep_range(5000, 5010);
514
515 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN, BIT(2), 0x00);
516 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
517 WCD_CLSH_EVENT_PRE_DAC,
518 WCD_CLSH_STATE_EAR,
519 hph_mode);
520
521 break;
522 case SND_SOC_DAPM_POST_PMD:
523 if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_LOHIFI ||
524 hph_mode == CLS_H_HIFI)
525 snd_soc_component_update_bits(component,
526 WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L,
527 0x0f, BIT(0));
528 if (wcd937x->comp1_enable)
529 snd_soc_component_update_bits(component,
530 WCD937X_DIGITAL_CDC_COMP_CTL_0,
531 BIT(1), 0x00);
532 break;
533 }
534
535 return 0;
536 }
537
538 static int wcd937x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
539 struct snd_kcontrol *kcontrol,
540 int event)
541 {
542 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
543 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
544 int hph_mode = wcd937x->hph_mode;
545
546 switch (event) {
547 case SND_SOC_DAPM_PRE_PMU:
548 wcd937x_rx_clk_enable(component);
549 snd_soc_component_update_bits(component,
550 WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
551 BIT(2), BIT(2));
552 snd_soc_component_update_bits(component,
553 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
554 BIT(2), BIT(2));
555 snd_soc_component_update_bits(component,
556 WCD937X_DIGITAL_CDC_AUX_GAIN_CTL,
557 BIT(0), BIT(0));
558 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
559 WCD_CLSH_EVENT_PRE_DAC,
560 WCD_CLSH_STATE_AUX,
561 hph_mode);
562
563 break;
564 case SND_SOC_DAPM_POST_PMD:
565 snd_soc_component_update_bits(component,
566 WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
567 BIT(2), 0x00);
568 break;
569 }
570
571 return 0;
572 }
573
574 static int wcd937x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
575 struct snd_kcontrol *kcontrol,
576 int event)
577 {
578 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
579 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
580 int hph_mode = wcd937x->hph_mode;
581
582 switch (event) {
583 case SND_SOC_DAPM_PRE_PMU:
584 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
585 WCD_CLSH_EVENT_PRE_DAC,
586 WCD_CLSH_STATE_HPHR,
587 hph_mode);
588 snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
589 BIT(4), BIT(4));
590 usleep_range(100, 110);
591 set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
592 snd_soc_component_update_bits(component,
593 WCD937X_DIGITAL_PDM_WD_CTL1,
594 0x07, 0x03);
595 break;
596 case SND_SOC_DAPM_POST_PMU:
597 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
598 if (wcd937x->comp2_enable)
599 usleep_range(7000, 7100);
600 else
601 usleep_range(20000, 20100);
602 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
603 }
604
605 snd_soc_component_update_bits(component,
606 WCD937X_HPH_NEW_INT_HPH_TIMER1,
607 BIT(1), BIT(1));
608 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
609 snd_soc_component_update_bits(component,
610 WCD937X_ANA_RX_SUPPLIES,
611 BIT(1), BIT(1));
612 enable_irq(wcd937x->hphr_pdm_wd_int);
613 break;
614 case SND_SOC_DAPM_PRE_PMD:
615 disable_irq_nosync(wcd937x->hphr_pdm_wd_int);
616 set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
617 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
618 break;
619 case SND_SOC_DAPM_POST_PMD:
620 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
621 if (wcd937x->comp2_enable)
622 usleep_range(7000, 7100);
623 else
624 usleep_range(20000, 20100);
625 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
626 }
627
628 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
629 snd_soc_component_update_bits(component,
630 WCD937X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
631 snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
632 BIT(4), 0x00);
633 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
634 WCD_CLSH_EVENT_POST_PA,
635 WCD_CLSH_STATE_HPHR,
636 hph_mode);
637 break;
638 }
639
640 return 0;
641 }
642
643 static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
644 struct snd_kcontrol *kcontrol,
645 int event)
646 {
647 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
648 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
649 int hph_mode = wcd937x->hph_mode;
650
651 switch (event) {
652 case SND_SOC_DAPM_PRE_PMU:
653 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
654 WCD_CLSH_EVENT_PRE_DAC,
655 WCD_CLSH_STATE_HPHL,
656 hph_mode);
657 snd_soc_component_update_bits(component, WCD937X_ANA_HPH,
658 BIT(5), BIT(5));
659 usleep_range(100, 110);
660 set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
661 snd_soc_component_update_bits(component,
662 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
663 break;
664 case SND_SOC_DAPM_POST_PMU:
665 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
666 if (!wcd937x->comp1_enable)
667 usleep_range(20000, 20100);
668 else
669 usleep_range(7000, 7100);
670 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
671 }
672
673 snd_soc_component_update_bits(component,
674 WCD937X_HPH_NEW_INT_HPH_TIMER1,
675 BIT(1), BIT(1));
676 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
677 snd_soc_component_update_bits(component,
678 WCD937X_ANA_RX_SUPPLIES,
679 BIT(1), BIT(1));
680 enable_irq(wcd937x->hphl_pdm_wd_int);
681 break;
682 case SND_SOC_DAPM_PRE_PMD:
683 disable_irq_nosync(wcd937x->hphl_pdm_wd_int);
684 set_bit(HPH_PA_DELAY, &wcd937x->status_mask);
685 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
686 break;
687 case SND_SOC_DAPM_POST_PMD:
688 if (test_bit(HPH_PA_DELAY, &wcd937x->status_mask)) {
689 if (!wcd937x->comp1_enable)
690 usleep_range(20000, 20100);
691 else
692 usleep_range(7000, 7100);
693 clear_bit(HPH_PA_DELAY, &wcd937x->status_mask);
694 }
695
696 wcd_mbhc_event_notify(wcd937x->wcd_mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
697 snd_soc_component_update_bits(component,
698 WCD937X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
699 snd_soc_component_update_bits(component,
700 WCD937X_ANA_HPH, BIT(5), 0x00);
701 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
702 WCD_CLSH_EVENT_POST_PA,
703 WCD_CLSH_STATE_HPHL,
704 hph_mode);
705 break;
706 }
707
708 return 0;
709 }
710
711 static int wcd937x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
712 struct snd_kcontrol *kcontrol,
713 int event)
714 {
715 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
716 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
717 int hph_mode = wcd937x->hph_mode;
718
719 switch (event) {
720 case SND_SOC_DAPM_PRE_PMU:
721 snd_soc_component_update_bits(component,
722 WCD937X_DIGITAL_PDM_WD_CTL2,
723 BIT(0), BIT(0));
724 break;
725 case SND_SOC_DAPM_POST_PMU:
726 usleep_range(1000, 1010);
727 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
728 snd_soc_component_update_bits(component,
729 WCD937X_ANA_RX_SUPPLIES,
730 BIT(1), BIT(1));
731 enable_irq(wcd937x->aux_pdm_wd_int);
732 break;
733 case SND_SOC_DAPM_PRE_PMD:
734 disable_irq_nosync(wcd937x->aux_pdm_wd_int);
735 break;
736 case SND_SOC_DAPM_POST_PMD:
737 usleep_range(2000, 2010);
738 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
739 WCD_CLSH_EVENT_POST_PA,
740 WCD_CLSH_STATE_AUX,
741 hph_mode);
742 snd_soc_component_update_bits(component,
743 WCD937X_DIGITAL_PDM_WD_CTL2,
744 BIT(0), 0x00);
745 break;
746 }
747
748 return 0;
749 }
750
751 static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
752 struct snd_kcontrol *kcontrol,
753 int event)
754 {
755 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
756 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
757 int hph_mode = wcd937x->hph_mode;
758
759 switch (event) {
760 case SND_SOC_DAPM_PRE_PMU:
761 /* Enable watchdog interrupt for HPHL or AUX depending on mux value */
762 wcd937x->ear_rx_path = snd_soc_component_read(component,
763 WCD937X_DIGITAL_CDC_EAR_PATH_CTL);
764
765 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
766 snd_soc_component_update_bits(component,
767 WCD937X_DIGITAL_PDM_WD_CTL2,
768 BIT(0), BIT(0));
769 else
770 snd_soc_component_update_bits(component,
771 WCD937X_DIGITAL_PDM_WD_CTL0,
772 0x07, 0x03);
773 if (!wcd937x->comp1_enable)
774 snd_soc_component_update_bits(component,
775 WCD937X_ANA_EAR_COMPANDER_CTL,
776 BIT(7), BIT(7));
777 break;
778 case SND_SOC_DAPM_POST_PMU:
779 usleep_range(6000, 6010);
780 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI)
781 snd_soc_component_update_bits(component,
782 WCD937X_ANA_RX_SUPPLIES,
783 BIT(1), BIT(1));
784
785 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
786 enable_irq(wcd937x->aux_pdm_wd_int);
787 else
788 enable_irq(wcd937x->hphl_pdm_wd_int);
789 break;
790 case SND_SOC_DAPM_PRE_PMD:
791 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
792 disable_irq_nosync(wcd937x->aux_pdm_wd_int);
793 else
794 disable_irq_nosync(wcd937x->hphl_pdm_wd_int);
795 break;
796 case SND_SOC_DAPM_POST_PMD:
797 if (!wcd937x->comp1_enable)
798 snd_soc_component_update_bits(component,
799 WCD937X_ANA_EAR_COMPANDER_CTL,
800 BIT(7), 0x00);
801 usleep_range(7000, 7010);
802 wcd_clsh_ctrl_set_state(wcd937x->clsh_info,
803 WCD_CLSH_EVENT_POST_PA,
804 WCD_CLSH_STATE_EAR,
805 hph_mode);
806 snd_soc_component_update_bits(component, WCD937X_FLYBACK_EN,
807 BIT(2), BIT(2));
808
809 if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX)
810 snd_soc_component_update_bits(component,
811 WCD937X_DIGITAL_PDM_WD_CTL2,
812 BIT(0), 0x00);
813 else
814 snd_soc_component_update_bits(component,
815 WCD937X_DIGITAL_PDM_WD_CTL0,
816 0x07, 0x00);
817 break;
818 }
819
820 return 0;
821 }
822
823 static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w,
824 struct snd_kcontrol *kcontrol,
825 int event)
826 {
827 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
828
829 if (event == SND_SOC_DAPM_POST_PMD) {
830 wcd937x_rx_clk_disable(component);
831 snd_soc_component_update_bits(component,
832 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
833 BIT(0), 0x00);
834 }
835
836 return 0;
837 }
838
839 static int wcd937x_enable_rx2(struct snd_soc_dapm_widget *w,
840 struct snd_kcontrol *kcontrol, int event)
841 {
842 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
843
844 if (event == SND_SOC_DAPM_POST_PMD) {
845 wcd937x_rx_clk_disable(component);
846 snd_soc_component_update_bits(component,
847 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
848 BIT(1), 0x00);
849 }
850
851 return 0;
852 }
853
854 static int wcd937x_enable_rx3(struct snd_soc_dapm_widget *w,
855 struct snd_kcontrol *kcontrol,
856 int event)
857 {
858 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
859
860 if (event == SND_SOC_DAPM_POST_PMD) {
861 usleep_range(6000, 6010);
862 wcd937x_rx_clk_disable(component);
863 snd_soc_component_update_bits(component,
864 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
865 BIT(2), 0x00);
866 }
867
868 return 0;
869 }
870
871 static int wcd937x_get_micb_vout_ctl_val(u32 micb_mv)
872 {
873 if (micb_mv < 1000 || micb_mv > 2850) {
874 pr_err("Unsupported micbias voltage (%u mV)\n", micb_mv);
875 return -EINVAL;
876 }
877
878 return (micb_mv - 1000) / 50;
879 }
880
881 static int wcd937x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
882 struct snd_kcontrol *kcontrol, int event)
883 {
884 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
885 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
886 bool use_amic3 = snd_soc_component_read(component, WCD937X_TX_NEW_TX_CH2_SEL) & BIT(7);
887
888 /* Enable BCS for Headset mic */
889 if (event == SND_SOC_DAPM_PRE_PMU && strnstr(w->name, "ADC", sizeof("ADC")))
890 if (w->shift == 1 && !use_amic3)
891 set_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
892
893 return 0;
894 }
895
896 static int wcd937x_codec_enable_adc(struct snd_soc_dapm_widget *w,
897 struct snd_kcontrol *kcontrol, int event)
898 {
899 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
900 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
901
902 switch (event) {
903 case SND_SOC_DAPM_PRE_PMU:
904 atomic_inc(&wcd937x->ana_clk_count);
905 snd_soc_component_update_bits(component,
906 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(7), BIT(7));
907 snd_soc_component_update_bits(component,
908 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), BIT(3));
909 snd_soc_component_update_bits(component,
910 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(4), BIT(4));
911 break;
912 case SND_SOC_DAPM_POST_PMD:
913 if (w->shift == 1 && test_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask))
914 clear_bit(AMIC2_BCS_ENABLE, &wcd937x->status_mask);
915
916 snd_soc_component_update_bits(component,
917 WCD937X_DIGITAL_CDC_ANA_CLK_CTL, BIT(3), 0x00);
918 break;
919 }
920
921 return 0;
922 }
923
924 static int wcd937x_enable_req(struct snd_soc_dapm_widget *w,
925 struct snd_kcontrol *kcontrol, int event)
926 {
927 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
928 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
929
930 switch (event) {
931 case SND_SOC_DAPM_PRE_PMU:
932 snd_soc_component_update_bits(component,
933 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(1), BIT(1));
934 snd_soc_component_update_bits(component,
935 WCD937X_DIGITAL_CDC_REQ_CTL, BIT(0), 0x00);
936 snd_soc_component_update_bits(component,
937 WCD937X_ANA_TX_CH2, BIT(6), BIT(6));
938 snd_soc_component_update_bits(component,
939 WCD937X_ANA_TX_CH3_HPF, BIT(6), BIT(6));
940 snd_soc_component_update_bits(component,
941 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70);
942 snd_soc_component_update_bits(component,
943 WCD937X_ANA_TX_CH1, BIT(7), BIT(7));
944 snd_soc_component_update_bits(component,
945 WCD937X_ANA_TX_CH2, BIT(6), 0x00);
946 snd_soc_component_update_bits(component,
947 WCD937X_ANA_TX_CH2, BIT(7), BIT(7));
948 snd_soc_component_update_bits(component,
949 WCD937X_ANA_TX_CH3, BIT(7), BIT(7));
950 break;
951 case SND_SOC_DAPM_POST_PMD:
952 snd_soc_component_update_bits(component,
953 WCD937X_ANA_TX_CH1, BIT(7), 0x00);
954 snd_soc_component_update_bits(component,
955 WCD937X_ANA_TX_CH2, BIT(7), 0x00);
956 snd_soc_component_update_bits(component,
957 WCD937X_ANA_TX_CH3, BIT(7), 0x00);
958 snd_soc_component_update_bits(component,
959 WCD937X_DIGITAL_CDC_DIG_CLK_CTL, BIT(4), 0x00);
960
961 atomic_dec(&wcd937x->ana_clk_count);
962 if (atomic_read(&wcd937x->ana_clk_count) <= 0) {
963 snd_soc_component_update_bits(component,
964 WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
965 BIT(4), 0x00);
966 atomic_set(&wcd937x->ana_clk_count, 0);
967 }
968
969 snd_soc_component_update_bits(component,
970 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
971 BIT(7), 0x00);
972 break;
973 }
974
975 return 0;
976 }
977
978 static int wcd937x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol,
980 int event)
981 {
982 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
983 u16 dmic_clk_reg;
984
985 switch (w->shift) {
986 case 0:
987 case 1:
988 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC1_CTL;
989 break;
990 case 2:
991 case 3:
992 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC2_CTL;
993 break;
994 case 4:
995 case 5:
996 dmic_clk_reg = WCD937X_DIGITAL_CDC_DMIC3_CTL;
997 break;
998 default:
999 dev_err(component->dev, "Invalid DMIC Selection\n");
1000 return -EINVAL;
1001 }
1002
1003 switch (event) {
1004 case SND_SOC_DAPM_PRE_PMU:
1005 snd_soc_component_update_bits(component,
1006 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
1007 BIT(7), BIT(7));
1008 snd_soc_component_update_bits(component,
1009 dmic_clk_reg, 0x07, BIT(1));
1010 snd_soc_component_update_bits(component,
1011 dmic_clk_reg, BIT(3), BIT(3));
1012 snd_soc_component_update_bits(component,
1013 dmic_clk_reg, 0x70, BIT(5));
1014 break;
1015 }
1016
1017 return 0;
1018 }
1019
1020 static int wcd937x_micbias_control(struct snd_soc_component *component,
1021 int micb_num, int req, bool is_dapm)
1022 {
1023 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1024 int micb_index = micb_num - 1;
1025 u16 micb_reg;
1026
1027 if (micb_index < 0 || (micb_index > WCD937X_MAX_MICBIAS - 1)) {
1028 dev_err(component->dev, "Invalid micbias index, micb_ind:%d\n", micb_index);
1029 return -EINVAL;
1030 }
1031 switch (micb_num) {
1032 case MIC_BIAS_1:
1033 micb_reg = WCD937X_ANA_MICB1;
1034 break;
1035 case MIC_BIAS_2:
1036 micb_reg = WCD937X_ANA_MICB2;
1037 break;
1038 case MIC_BIAS_3:
1039 micb_reg = WCD937X_ANA_MICB3;
1040 break;
1041 default:
1042 dev_err(component->dev, "Invalid micbias number: %d\n", micb_num);
1043 return -EINVAL;
1044 }
1045
1046 mutex_lock(&wcd937x->micb_lock);
1047 switch (req) {
1048 case MICB_PULLUP_ENABLE:
1049 wcd937x->pullup_ref[micb_index]++;
1050 if (wcd937x->pullup_ref[micb_index] == 1 &&
1051 wcd937x->micb_ref[micb_index] == 0)
1052 snd_soc_component_update_bits(component, micb_reg,
1053 0xc0, BIT(7));
1054 break;
1055 case MICB_PULLUP_DISABLE:
1056 if (wcd937x->pullup_ref[micb_index] > 0)
1057 wcd937x->pullup_ref[micb_index]++;
1058 if (wcd937x->pullup_ref[micb_index] == 0 &&
1059 wcd937x->micb_ref[micb_index] == 0)
1060 snd_soc_component_update_bits(component, micb_reg,
1061 0xc0, 0x00);
1062 break;
1063 case MICB_ENABLE:
1064 wcd937x->micb_ref[micb_index]++;
1065 atomic_inc(&wcd937x->ana_clk_count);
1066 if (wcd937x->micb_ref[micb_index] == 1) {
1067 snd_soc_component_update_bits(component,
1068 WCD937X_DIGITAL_CDC_DIG_CLK_CTL,
1069 0xf0, 0xf0);
1070 snd_soc_component_update_bits(component,
1071 WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
1072 BIT(4), BIT(4));
1073 snd_soc_component_update_bits(component,
1074 WCD937X_MICB1_TEST_CTL_2,
1075 BIT(0), BIT(0));
1076 snd_soc_component_update_bits(component,
1077 WCD937X_MICB2_TEST_CTL_2,
1078 BIT(0), BIT(0));
1079 snd_soc_component_update_bits(component,
1080 WCD937X_MICB3_TEST_CTL_2,
1081 BIT(0), BIT(0));
1082 snd_soc_component_update_bits(component,
1083 micb_reg, 0xc0, BIT(6));
1084
1085 if (micb_num == MIC_BIAS_2)
1086 wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1087 WCD_EVENT_POST_MICBIAS_2_ON);
1088
1089 if (micb_num == MIC_BIAS_2 && is_dapm)
1090 wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1091 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1092 }
1093 break;
1094 case MICB_DISABLE:
1095 atomic_dec(&wcd937x->ana_clk_count);
1096 if (wcd937x->micb_ref[micb_index] > 0)
1097 wcd937x->micb_ref[micb_index]--;
1098 if (wcd937x->micb_ref[micb_index] == 0 &&
1099 wcd937x->pullup_ref[micb_index] > 0)
1100 snd_soc_component_update_bits(component, micb_reg,
1101 0xc0, BIT(7));
1102 else if (wcd937x->micb_ref[micb_index] == 0 &&
1103 wcd937x->pullup_ref[micb_index] == 0) {
1104 if (micb_num == MIC_BIAS_2)
1105 wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1106 WCD_EVENT_PRE_MICBIAS_2_OFF);
1107
1108 snd_soc_component_update_bits(component, micb_reg,
1109 0xc0, 0x00);
1110 if (micb_num == MIC_BIAS_2)
1111 wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1112 WCD_EVENT_POST_MICBIAS_2_OFF);
1113 }
1114
1115 if (is_dapm && micb_num == MIC_BIAS_2)
1116 wcd_mbhc_event_notify(wcd937x->wcd_mbhc,
1117 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1118 if (atomic_read(&wcd937x->ana_clk_count) <= 0) {
1119 snd_soc_component_update_bits(component,
1120 WCD937X_DIGITAL_CDC_ANA_CLK_CTL,
1121 BIT(4), 0x00);
1122 atomic_set(&wcd937x->ana_clk_count, 0);
1123 }
1124 break;
1125 }
1126 mutex_unlock(&wcd937x->micb_lock);
1127
1128 return 0;
1129 }
1130
1131 static int __wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1132 int event)
1133 {
1134 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1135 int micb_num = w->shift;
1136
1137 switch (event) {
1138 case SND_SOC_DAPM_PRE_PMU:
1139 wcd937x_micbias_control(component, micb_num,
1140 MICB_ENABLE, true);
1141 break;
1142 case SND_SOC_DAPM_POST_PMU:
1143 usleep_range(1000, 1100);
1144 break;
1145 case SND_SOC_DAPM_POST_PMD:
1146 wcd937x_micbias_control(component, micb_num,
1147 MICB_DISABLE, true);
1148 break;
1149 }
1150
1151 return 0;
1152 }
1153
1154 static int wcd937x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1155 struct snd_kcontrol *kcontrol,
1156 int event)
1157 {
1158 return __wcd937x_codec_enable_micbias(w, event);
1159 }
1160
1161 static int __wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1162 int event)
1163 {
1164 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1165 int micb_num = w->shift;
1166
1167 switch (event) {
1168 case SND_SOC_DAPM_PRE_PMU:
1169 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_ENABLE, true);
1170 break;
1171 case SND_SOC_DAPM_POST_PMU:
1172 usleep_range(1000, 1100);
1173 break;
1174 case SND_SOC_DAPM_POST_PMD:
1175 wcd937x_micbias_control(component, micb_num, MICB_PULLUP_DISABLE, true);
1176 break;
1177 }
1178
1179 return 0;
1180 }
1181
1182 static int wcd937x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1183 struct snd_kcontrol *kcontrol,
1184 int event)
1185 {
1186 return __wcd937x_codec_enable_micbias_pullup(w, event);
1187 }
1188
1189 static int wcd937x_connect_port(struct wcd937x_sdw_priv *wcd, u8 port_idx, u8 ch_id, bool enable)
1190 {
1191 struct sdw_port_config *port_config = &wcd->port_config[port_idx - 1];
1192 const struct wcd937x_sdw_ch_info *ch_info = &wcd->ch_info[ch_id];
1193 u8 port_num = ch_info->port_num;
1194 u8 ch_mask = ch_info->ch_mask;
1195
1196 port_config->num = port_num;
1197
1198 if (enable)
1199 port_config->ch_mask |= ch_mask;
1200 else
1201 port_config->ch_mask &= ~ch_mask;
1202
1203 return 0;
1204 }
1205
1206 static int wcd937x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1207 struct snd_ctl_elem_value *ucontrol)
1208 {
1209 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1210 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1211
1212 ucontrol->value.integer.value[0] = wcd937x->hph_mode;
1213 return 0;
1214 }
1215
1216 static int wcd937x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1217 struct snd_ctl_elem_value *ucontrol)
1218 {
1219 struct snd_soc_component *component =
1220 snd_soc_kcontrol_component(kcontrol);
1221 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1222 u32 mode_val;
1223
1224 mode_val = ucontrol->value.enumerated.item[0];
1225
1226 if (!mode_val)
1227 mode_val = CLS_AB;
1228
1229 if (mode_val == wcd937x->hph_mode)
1230 return 0;
1231
1232 switch (mode_val) {
1233 case CLS_H_NORMAL:
1234 case CLS_H_HIFI:
1235 case CLS_H_LP:
1236 case CLS_AB:
1237 case CLS_H_LOHIFI:
1238 case CLS_H_ULP:
1239 case CLS_AB_LP:
1240 case CLS_AB_HIFI:
1241 wcd937x->hph_mode = mode_val;
1242 return 1;
1243 }
1244
1245 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__);
1246 return -EINVAL;
1247 }
1248
1249 static int wcd937x_get_compander(struct snd_kcontrol *kcontrol,
1250 struct snd_ctl_elem_value *ucontrol)
1251 {
1252 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1253 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1254 struct soc_mixer_control *mc;
1255 bool hphr;
1256
1257 mc = (struct soc_mixer_control *)(kcontrol->private_value);
1258 hphr = mc->shift;
1259
1260 ucontrol->value.integer.value[0] = hphr ? wcd937x->comp2_enable :
1261 wcd937x->comp1_enable;
1262 return 0;
1263 }
1264
1265 static int wcd937x_set_compander(struct snd_kcontrol *kcontrol,
1266 struct snd_ctl_elem_value *ucontrol)
1267 {
1268 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1269 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1270 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[AIF1_PB];
1271 int value = ucontrol->value.integer.value[0];
1272 struct soc_mixer_control *mc;
1273 int portidx;
1274 bool hphr;
1275
1276 mc = (struct soc_mixer_control *)(kcontrol->private_value);
1277 hphr = mc->shift;
1278
1279 if (hphr) {
1280 if (value == wcd937x->comp2_enable)
1281 return 0;
1282
1283 wcd937x->comp2_enable = value;
1284 } else {
1285 if (value == wcd937x->comp1_enable)
1286 return 0;
1287
1288 wcd937x->comp1_enable = value;
1289 }
1290
1291 portidx = wcd->ch_info[mc->reg].port_num;
1292
1293 if (value)
1294 wcd937x_connect_port(wcd, portidx, mc->reg, true);
1295 else
1296 wcd937x_connect_port(wcd, portidx, mc->reg, false);
1297
1298 return 1;
1299 }
1300
1301 static int wcd937x_get_swr_port(struct snd_kcontrol *kcontrol,
1302 struct snd_ctl_elem_value *ucontrol)
1303 {
1304 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1305 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1306 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp);
1307 struct wcd937x_sdw_priv *wcd;
1308 int dai_id = mixer->shift;
1309 int ch_idx = mixer->reg;
1310 int portidx;
1311
1312 wcd = wcd937x->sdw_priv[dai_id];
1313 portidx = wcd->ch_info[ch_idx].port_num;
1314
1315 ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
1316
1317 return 0;
1318 }
1319
1320 static int wcd937x_set_swr_port(struct snd_kcontrol *kcontrol,
1321 struct snd_ctl_elem_value *ucontrol)
1322 {
1323 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1324 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1325 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(comp);
1326 struct wcd937x_sdw_priv *wcd;
1327 int dai_id = mixer->shift;
1328 int ch_idx = mixer->reg;
1329 int portidx;
1330 bool enable;
1331
1332 wcd = wcd937x->sdw_priv[dai_id];
1333
1334 portidx = wcd->ch_info[ch_idx].port_num;
1335
1336 enable = ucontrol->value.integer.value[0];
1337
1338 if (enable == wcd->port_enable[portidx]) {
1339 wcd937x_connect_port(wcd, portidx, ch_idx, enable);
1340 return 0;
1341 }
1342
1343 wcd->port_enable[portidx] = enable;
1344 wcd937x_connect_port(wcd, portidx, ch_idx, enable);
1345
1346 return 1;
1347 }
1348
1349 static const char * const rx_hph_mode_mux_text[] = {
1350 "CLS_H_NORMAL", "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB",
1351 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_AB_LP", "CLS_AB_HIFI",
1352 };
1353
1354 static const struct soc_enum rx_hph_mode_mux_enum =
1355 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), rx_hph_mode_mux_text);
1356
1357 /* MBHC related */
1358 static void wcd937x_mbhc_clk_setup(struct snd_soc_component *component,
1359 bool enable)
1360 {
1361 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_1,
1362 WCD937X_MBHC_CTL_RCO_EN_MASK, enable);
1363 }
1364
1365 static void wcd937x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1366 bool enable)
1367 {
1368 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_ELECT,
1369 WCD937X_ANA_MBHC_BIAS_EN, enable);
1370 }
1371
1372 static void wcd937x_mbhc_program_btn_thr(struct snd_soc_component *component,
1373 int *btn_low, int *btn_high,
1374 int num_btn, bool is_micbias)
1375 {
1376 int i, vth;
1377
1378 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1379 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1380 __func__, num_btn);
1381 return;
1382 }
1383
1384 for (i = 0; i < num_btn; i++) {
1385 vth = ((btn_high[i] * 2) / 25) & 0x3F;
1386 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_BTN0 + i,
1387 WCD937X_MBHC_BTN_VTH_MASK, vth);
1388 }
1389 }
1390
1391 static bool wcd937x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1392 {
1393 u8 val;
1394
1395 if (micb_num == MIC_BIAS_2) {
1396 val = snd_soc_component_read_field(component,
1397 WCD937X_ANA_MICB2,
1398 WCD937X_ANA_MICB2_ENABLE_MASK);
1399 if (val == WCD937X_MICB_ENABLE)
1400 return true;
1401 }
1402 return false;
1403 }
1404
1405 static void wcd937x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1406 int pull_up_cur)
1407 {
1408 /* Default pull up current to 2uA */
1409 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
1410 pull_up_cur = HS_PULLUP_I_2P0_UA;
1411
1412 snd_soc_component_write_field(component,
1413 WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT,
1414 WCD937X_HSDET_PULLUP_C_MASK, pull_up_cur);
1415 }
1416
1417 static int wcd937x_mbhc_request_micbias(struct snd_soc_component *component,
1418 int micb_num, int req)
1419 {
1420 return wcd937x_micbias_control(component, micb_num, req, false);
1421 }
1422
1423 static void wcd937x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1424 bool enable)
1425 {
1426 if (enable) {
1427 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1428 WCD937X_RAMP_SHIFT_CTRL_MASK, 0x0C);
1429 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1430 WCD937X_RAMP_EN_MASK, 1);
1431 } else {
1432 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1433 WCD937X_RAMP_EN_MASK, 0);
1434 snd_soc_component_write_field(component, WCD937X_ANA_MICB2_RAMP,
1435 WCD937X_RAMP_SHIFT_CTRL_MASK, 0);
1436 }
1437 }
1438
1439 static int wcd937x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1440 int req_volt, int micb_num)
1441 {
1442 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1443 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
1444
1445 switch (micb_num) {
1446 case MIC_BIAS_1:
1447 micb_reg = WCD937X_ANA_MICB1;
1448 break;
1449 case MIC_BIAS_2:
1450 micb_reg = WCD937X_ANA_MICB2;
1451 break;
1452 case MIC_BIAS_3:
1453 micb_reg = WCD937X_ANA_MICB3;
1454 break;
1455 default:
1456 return -EINVAL;
1457 }
1458 mutex_lock(&wcd937x->micb_lock);
1459 /*
1460 * If requested micbias voltage is same as current micbias
1461 * voltage, then just return. Otherwise, adjust voltage as
1462 * per requested value. If micbias is already enabled, then
1463 * to avoid slow micbias ramp-up or down enable pull-up
1464 * momentarily, change the micbias value and then re-enable
1465 * micbias.
1466 */
1467 micb_en = snd_soc_component_read_field(component, micb_reg,
1468 WCD937X_MICB_EN_MASK);
1469 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
1470 WCD937X_MICB_VOUT_MASK);
1471
1472 req_vout_ctl = wcd937x_get_micb_vout_ctl_val(req_volt);
1473 if (req_vout_ctl < 0) {
1474 ret = -EINVAL;
1475 goto exit;
1476 }
1477
1478 if (cur_vout_ctl == req_vout_ctl) {
1479 ret = 0;
1480 goto exit;
1481 }
1482
1483 if (micb_en == WCD937X_MICB_ENABLE)
1484 snd_soc_component_write_field(component, micb_reg,
1485 WCD937X_MICB_EN_MASK,
1486 WCD937X_MICB_PULL_UP);
1487
1488 snd_soc_component_write_field(component, micb_reg,
1489 WCD937X_MICB_VOUT_MASK,
1490 req_vout_ctl);
1491
1492 if (micb_en == WCD937X_MICB_ENABLE) {
1493 snd_soc_component_write_field(component, micb_reg,
1494 WCD937X_MICB_EN_MASK,
1495 WCD937X_MICB_ENABLE);
1496 /*
1497 * Add 2ms delay as per HW requirement after enabling
1498 * micbias
1499 */
1500 usleep_range(2000, 2100);
1501 }
1502 exit:
1503 mutex_unlock(&wcd937x->micb_lock);
1504 return ret;
1505 }
1506
1507 static int wcd937x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
1508 int micb_num, bool req_en)
1509 {
1510 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1511 int micb_mv;
1512
1513 if (micb_num != MIC_BIAS_2)
1514 return -EINVAL;
1515 /*
1516 * If device tree micbias level is already above the minimum
1517 * voltage needed to detect threshold microphone, then do
1518 * not change the micbias, just return.
1519 */
1520 if (wcd937x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
1521 return 0;
1522
1523 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd937x->micb2_mv;
1524
1525 return wcd937x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
1526 }
1527
1528 static void wcd937x_mbhc_get_result_params(struct snd_soc_component *component,
1529 s16 *d1_a, u16 noff,
1530 int32_t *zdet)
1531 {
1532 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1533 int i;
1534 int val, val1;
1535 s16 c1;
1536 s32 x1, d1;
1537 s32 denom;
1538 static const int minCode_param[] = {
1539 3277, 1639, 820, 410, 205, 103, 52, 26
1540 };
1541
1542 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x20);
1543 for (i = 0; i < WCD937X_ZDET_NUM_MEASUREMENTS; i++) {
1544 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_2, &val);
1545 if (val & 0x80)
1546 break;
1547 }
1548 val = val << 0x8;
1549 regmap_read(wcd937x->regmap, WCD937X_ANA_MBHC_RESULT_1, &val1);
1550 val |= val1;
1551 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MBHC_ZDET, 0x20, 0x00);
1552 x1 = WCD937X_MBHC_GET_X1(val);
1553 c1 = WCD937X_MBHC_GET_C1(val);
1554 /* If ramp is not complete, give additional 5ms */
1555 if (c1 < 2 && x1)
1556 usleep_range(5000, 5050);
1557
1558 if (!c1 || !x1) {
1559 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n",
1560 c1, x1);
1561 goto ramp_down;
1562 }
1563 d1 = d1_a[c1];
1564 denom = (x1 * d1) - (1 << (14 - noff));
1565 if (denom > 0)
1566 *zdet = (WCD937X_MBHC_ZDET_CONST * 1000) / denom;
1567 else if (x1 < minCode_param[noff])
1568 *zdet = WCD937X_ZDET_FLOATING_IMPEDANCE;
1569
1570 dev_err(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n",
1571 __func__, d1, c1, x1, *zdet);
1572 ramp_down:
1573 i = 0;
1574 while (x1) {
1575 regmap_read(wcd937x->regmap,
1576 WCD937X_ANA_MBHC_RESULT_1, &val);
1577 regmap_read(wcd937x->regmap,
1578 WCD937X_ANA_MBHC_RESULT_2, &val1);
1579 val = val << 0x08;
1580 val |= val1;
1581 x1 = WCD937X_MBHC_GET_X1(val);
1582 i++;
1583 if (i == WCD937X_ZDET_NUM_MEASUREMENTS)
1584 break;
1585 }
1586 }
1587
1588 static void wcd937x_mbhc_zdet_ramp(struct snd_soc_component *component,
1589 struct wcd937x_mbhc_zdet_param *zdet_param,
1590 s32 *zl, s32 *zr, s16 *d1_a)
1591 {
1592 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1593 s32 zdet = 0;
1594
1595 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL,
1596 WCD937X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
1597 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN5,
1598 WCD937X_VTH_MASK, zdet_param->btn5);
1599 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN6,
1600 WCD937X_VTH_MASK, zdet_param->btn6);
1601 snd_soc_component_update_bits(component, WCD937X_ANA_MBHC_BTN7,
1602 WCD937X_VTH_MASK, zdet_param->btn7);
1603 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL,
1604 WCD937X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
1605 snd_soc_component_update_bits(component, WCD937X_MBHC_NEW_ZDET_RAMP_CTL,
1606 0x0F, zdet_param->nshift);
1607
1608 if (!zl)
1609 goto z_right;
1610 /* Start impedance measurement for HPH_L */
1611 regmap_update_bits(wcd937x->regmap,
1612 WCD937X_ANA_MBHC_ZDET, 0x80, 0x80);
1613 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
1614 regmap_update_bits(wcd937x->regmap,
1615 WCD937X_ANA_MBHC_ZDET, 0x80, 0x00);
1616
1617 *zl = zdet;
1618
1619 z_right:
1620 if (!zr)
1621 return;
1622 /* Start impedance measurement for HPH_R */
1623 regmap_update_bits(wcd937x->regmap,
1624 WCD937X_ANA_MBHC_ZDET, 0x40, 0x40);
1625 wcd937x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet);
1626 regmap_update_bits(wcd937x->regmap,
1627 WCD937X_ANA_MBHC_ZDET, 0x40, 0x00);
1628
1629 *zr = zdet;
1630 }
1631
1632 static void wcd937x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
1633 s32 *z_val, int flag_l_r)
1634 {
1635 s16 q1;
1636 int q1_cal;
1637
1638 if (*z_val < (WCD937X_ZDET_VAL_400 / 1000))
1639 q1 = snd_soc_component_read(component,
1640 WCD937X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
1641 else
1642 q1 = snd_soc_component_read(component,
1643 WCD937X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
1644 if (q1 & 0x80)
1645 q1_cal = (10000 - ((q1 & 0x7F) * 25));
1646 else
1647 q1_cal = (10000 + (q1 * 25));
1648 if (q1_cal > 0)
1649 *z_val = ((*z_val) * 10000) / q1_cal;
1650 }
1651
1652 static void wcd937x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
1653 u32 *zl, u32 *zr)
1654 {
1655 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1656 s16 reg0, reg1, reg2, reg3, reg4;
1657 s32 z1l, z1r, z1ls;
1658 int zMono, z_diff1, z_diff2;
1659 bool is_fsm_disable = false;
1660 struct wcd937x_mbhc_zdet_param zdet_param[] = {
1661 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
1662 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
1663 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
1664 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
1665 };
1666 struct wcd937x_mbhc_zdet_param *zdet_param_ptr = NULL;
1667 s16 d1_a[][4] = {
1668 {0, 30, 90, 30},
1669 {0, 30, 30, 5},
1670 {0, 30, 30, 5},
1671 {0, 30, 30, 5},
1672 };
1673 s16 *d1 = NULL;
1674
1675 reg0 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN5);
1676 reg1 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN6);
1677 reg2 = snd_soc_component_read(component, WCD937X_ANA_MBHC_BTN7);
1678 reg3 = snd_soc_component_read(component, WCD937X_MBHC_CTL_CLK);
1679 reg4 = snd_soc_component_read(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL);
1680
1681 if (snd_soc_component_read(component, WCD937X_ANA_MBHC_ELECT) & 0x80) {
1682 is_fsm_disable = true;
1683 regmap_update_bits(wcd937x->regmap,
1684 WCD937X_ANA_MBHC_ELECT, 0x80, 0x00);
1685 }
1686
1687 /* For NO-jack, disable L_DET_EN before Z-det measurements */
1688 if (wcd937x->mbhc_cfg.hphl_swh)
1689 regmap_update_bits(wcd937x->regmap,
1690 WCD937X_ANA_MBHC_MECH, 0x80, 0x00);
1691
1692 /* Turn off 100k pull down on HPHL */
1693 regmap_update_bits(wcd937x->regmap,
1694 WCD937X_ANA_MBHC_MECH, 0x01, 0x00);
1695
1696 /* Disable surge protection before impedance detection.
1697 * This is done to give correct value for high impedance.
1698 */
1699 regmap_update_bits(wcd937x->regmap,
1700 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
1701 /* 1ms delay needed after disable surge protection */
1702 usleep_range(1000, 1010);
1703
1704 /* First get impedance on Left */
1705 d1 = d1_a[1];
1706 zdet_param_ptr = &zdet_param[1];
1707 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1);
1708
1709 if (!WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1l))
1710 goto left_ch_impedance;
1711
1712 /* Second ramp for left ch */
1713 if (z1l < WCD937X_ZDET_VAL_32) {
1714 zdet_param_ptr = &zdet_param[0];
1715 d1 = d1_a[0];
1716 } else if ((z1l > WCD937X_ZDET_VAL_400) &&
1717 (z1l <= WCD937X_ZDET_VAL_1200)) {
1718 zdet_param_ptr = &zdet_param[2];
1719 d1 = d1_a[2];
1720 } else if (z1l > WCD937X_ZDET_VAL_1200) {
1721 zdet_param_ptr = &zdet_param[3];
1722 d1 = d1_a[3];
1723 }
1724 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1l, NULL, d1);
1725
1726 left_ch_impedance:
1727 if (z1l == WCD937X_ZDET_FLOATING_IMPEDANCE ||
1728 z1l > WCD937X_ZDET_VAL_100K) {
1729 *zl = WCD937X_ZDET_FLOATING_IMPEDANCE;
1730 zdet_param_ptr = &zdet_param[1];
1731 d1 = d1_a[1];
1732 } else {
1733 *zl = z1l / 1000;
1734 wcd937x_wcd_mbhc_qfuse_cal(component, zl, 0);
1735 }
1736
1737 /* Start of right impedance ramp and calculation */
1738 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1);
1739 if (WCD937X_MBHC_IS_SECOND_RAMP_REQUIRED(z1r)) {
1740 if ((z1r > WCD937X_ZDET_VAL_1200 &&
1741 zdet_param_ptr->noff == 0x6) ||
1742 ((*zl) != WCD937X_ZDET_FLOATING_IMPEDANCE))
1743 goto right_ch_impedance;
1744 /* Second ramp for right ch */
1745 if (z1r < WCD937X_ZDET_VAL_32) {
1746 zdet_param_ptr = &zdet_param[0];
1747 d1 = d1_a[0];
1748 } else if ((z1r > WCD937X_ZDET_VAL_400) &&
1749 (z1r <= WCD937X_ZDET_VAL_1200)) {
1750 zdet_param_ptr = &zdet_param[2];
1751 d1 = d1_a[2];
1752 } else if (z1r > WCD937X_ZDET_VAL_1200) {
1753 zdet_param_ptr = &zdet_param[3];
1754 d1 = d1_a[3];
1755 }
1756 wcd937x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1r, d1);
1757 }
1758 right_ch_impedance:
1759 if (z1r == WCD937X_ZDET_FLOATING_IMPEDANCE ||
1760 z1r > WCD937X_ZDET_VAL_100K) {
1761 *zr = WCD937X_ZDET_FLOATING_IMPEDANCE;
1762 } else {
1763 *zr = z1r / 1000;
1764 wcd937x_wcd_mbhc_qfuse_cal(component, zr, 1);
1765 }
1766
1767 /* Mono/stereo detection */
1768 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) &&
1769 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE)) {
1770 dev_err(component->dev,
1771 "%s: plug type is invalid or extension cable\n",
1772 __func__);
1773 goto zdet_complete;
1774 }
1775 if ((*zl == WCD937X_ZDET_FLOATING_IMPEDANCE) ||
1776 (*zr == WCD937X_ZDET_FLOATING_IMPEDANCE) ||
1777 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
1778 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
1779 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO);
1780 goto zdet_complete;
1781 }
1782 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST,
1783 WCD937X_HPHPA_GND_OVR_MASK, 1);
1784 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1785 WCD937X_HPHPA_GND_R_MASK, 1);
1786 if (*zl < (WCD937X_ZDET_VAL_32 / 1000))
1787 wcd937x_mbhc_zdet_ramp(component, &zdet_param[0], &z1ls, NULL, d1);
1788 else
1789 wcd937x_mbhc_zdet_ramp(component, &zdet_param[1], &z1ls, NULL, d1);
1790 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1791 WCD937X_HPHPA_GND_R_MASK, 0);
1792 snd_soc_component_write_field(component, WCD937X_HPH_R_ATEST,
1793 WCD937X_HPHPA_GND_OVR_MASK, 0);
1794 z1ls /= 1000;
1795 wcd937x_wcd_mbhc_qfuse_cal(component, &z1ls, 0);
1796 /* Parallel of left Z and 9 ohm pull down resistor */
1797 zMono = ((*zl) * 9) / ((*zl) + 9);
1798 z_diff1 = (z1ls > zMono) ? (z1ls - zMono) : (zMono - z1ls);
1799 z_diff2 = ((*zl) > z1ls) ? ((*zl) - z1ls) : (z1ls - (*zl));
1800 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + zMono)))
1801 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
1802 else
1803 wcd_mbhc_set_hph_type(wcd937x->wcd_mbhc, WCD_MBHC_HPH_MONO);
1804
1805 /* Enable surge protection again after impedance detection */
1806 regmap_update_bits(wcd937x->regmap,
1807 WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1808 zdet_complete:
1809 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN5, reg0);
1810 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN6, reg1);
1811 snd_soc_component_write(component, WCD937X_ANA_MBHC_BTN7, reg2);
1812 /* Turn on 100k pull down on HPHL */
1813 regmap_update_bits(wcd937x->regmap,
1814 WCD937X_ANA_MBHC_MECH, 0x01, 0x01);
1815
1816 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
1817 if (wcd937x->mbhc_cfg.hphl_swh)
1818 regmap_update_bits(wcd937x->regmap,
1819 WCD937X_ANA_MBHC_MECH, 0x80, 0x80);
1820
1821 snd_soc_component_write(component, WCD937X_MBHC_NEW_ZDET_ANA_CTL, reg4);
1822 snd_soc_component_write(component, WCD937X_MBHC_CTL_CLK, reg3);
1823 if (is_fsm_disable)
1824 regmap_update_bits(wcd937x->regmap,
1825 WCD937X_ANA_MBHC_ELECT, 0x80, 0x80);
1826 }
1827
1828 static void wcd937x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
1829 bool enable)
1830 {
1831 if (enable) {
1832 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1833 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 1);
1834 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1835 WCD937X_MBHC_GND_DET_EN_MASK, 1);
1836 } else {
1837 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1838 WCD937X_MBHC_GND_DET_EN_MASK, 0);
1839 snd_soc_component_write_field(component, WCD937X_ANA_MBHC_MECH,
1840 WCD937X_MBHC_HSG_PULLUP_COMP_EN, 0);
1841 }
1842 }
1843
1844 static void wcd937x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
1845 bool enable)
1846 {
1847 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1848 WCD937X_HPHPA_GND_R_MASK, enable);
1849 snd_soc_component_write_field(component, WCD937X_HPH_PA_CTL2,
1850 WCD937X_HPHPA_GND_L_MASK, enable);
1851 }
1852
1853 static void wcd937x_mbhc_moisture_config(struct snd_soc_component *component)
1854 {
1855 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1856
1857 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) {
1858 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1859 WCD937X_M_RTH_CTL_MASK, R_OFF);
1860 return;
1861 }
1862
1863 /* Do not enable moisture detection if jack type is NC */
1864 if (!wcd937x->mbhc_cfg.hphl_swh) {
1865 dev_err(component->dev, "%s: disable moisture detection for NC\n",
1866 __func__);
1867 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1868 WCD937X_M_RTH_CTL_MASK, R_OFF);
1869 return;
1870 }
1871
1872 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1873 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref);
1874 }
1875
1876 static void wcd937x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
1877 {
1878 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1879
1880 if (enable)
1881 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1882 WCD937X_M_RTH_CTL_MASK, wcd937x->mbhc_cfg.moist_rref);
1883 else
1884 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1885 WCD937X_M_RTH_CTL_MASK, R_OFF);
1886 }
1887
1888 static bool wcd937x_mbhc_get_moisture_status(struct snd_soc_component *component)
1889 {
1890 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1891 bool ret = false;
1892
1893 if (wcd937x->mbhc_cfg.moist_rref == R_OFF) {
1894 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1895 WCD937X_M_RTH_CTL_MASK, R_OFF);
1896 goto done;
1897 }
1898
1899 /* Do not enable moisture detection if jack type is NC */
1900 if (!wcd937x->mbhc_cfg.hphl_swh) {
1901 dev_err(component->dev, "%s: disable moisture detection for NC\n",
1902 __func__);
1903 snd_soc_component_write_field(component, WCD937X_MBHC_NEW_CTL_2,
1904 WCD937X_M_RTH_CTL_MASK, R_OFF);
1905 goto done;
1906 }
1907
1908 /*
1909 * If moisture_en is already enabled, then skip to plug type
1910 * detection.
1911 */
1912 if (snd_soc_component_read_field(component, WCD937X_MBHC_NEW_CTL_2, WCD937X_M_RTH_CTL_MASK))
1913 goto done;
1914
1915 wcd937x_mbhc_moisture_detect_en(component, true);
1916 /* Read moisture comparator status */
1917 ret = ((snd_soc_component_read(component, WCD937X_MBHC_NEW_FSM_STATUS)
1918 & 0x20) ? 0 : 1);
1919 done:
1920 return ret;
1921 }
1922
1923 static void wcd937x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
1924 bool enable)
1925 {
1926 snd_soc_component_write_field(component,
1927 WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
1928 WCD937X_MOISTURE_EN_POLLING_MASK, enable);
1929 }
1930
1931 static const struct wcd_mbhc_cb mbhc_cb = {
1932 .clk_setup = wcd937x_mbhc_clk_setup,
1933 .mbhc_bias = wcd937x_mbhc_mbhc_bias_control,
1934 .set_btn_thr = wcd937x_mbhc_program_btn_thr,
1935 .micbias_enable_status = wcd937x_mbhc_micb_en_status,
1936 .hph_pull_up_control_v2 = wcd937x_mbhc_hph_l_pull_up_control,
1937 .mbhc_micbias_control = wcd937x_mbhc_request_micbias,
1938 .mbhc_micb_ramp_control = wcd937x_mbhc_micb_ramp_control,
1939 .mbhc_micb_ctrl_thr_mic = wcd937x_mbhc_micb_ctrl_threshold_mic,
1940 .compute_impedance = wcd937x_wcd_mbhc_calc_impedance,
1941 .mbhc_gnd_det_ctrl = wcd937x_mbhc_gnd_det_ctrl,
1942 .hph_pull_down_ctrl = wcd937x_mbhc_hph_pull_down_ctrl,
1943 .mbhc_moisture_config = wcd937x_mbhc_moisture_config,
1944 .mbhc_get_moisture_status = wcd937x_mbhc_get_moisture_status,
1945 .mbhc_moisture_polling_ctrl = wcd937x_mbhc_moisture_polling_ctrl,
1946 .mbhc_moisture_detect_en = wcd937x_mbhc_moisture_detect_en,
1947 };
1948
1949 static int wcd937x_get_hph_type(struct snd_kcontrol *kcontrol,
1950 struct snd_ctl_elem_value *ucontrol)
1951 {
1952 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1953 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1954
1955 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd937x->wcd_mbhc);
1956
1957 return 0;
1958 }
1959
1960 static int wcd937x_hph_impedance_get(struct snd_kcontrol *kcontrol,
1961 struct snd_ctl_elem_value *ucontrol)
1962 {
1963 u32 zl, zr;
1964 bool hphr;
1965 struct soc_mixer_control *mc;
1966 struct snd_soc_component *component =
1967 snd_soc_kcontrol_component(kcontrol);
1968 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1969
1970 mc = (struct soc_mixer_control *)(kcontrol->private_value);
1971 hphr = mc->shift;
1972 wcd_mbhc_get_impedance(wcd937x->wcd_mbhc, &zl, &zr);
1973 ucontrol->value.integer.value[0] = hphr ? zr : zl;
1974
1975 return 0;
1976 }
1977
1978 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
1979 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
1980 wcd937x_get_hph_type, NULL),
1981 };
1982
1983 static const struct snd_kcontrol_new impedance_detect_controls[] = {
1984 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
1985 wcd937x_hph_impedance_get, NULL),
1986 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
1987 wcd937x_hph_impedance_get, NULL),
1988 };
1989
1990 static int wcd937x_mbhc_init(struct snd_soc_component *component)
1991 {
1992 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
1993 struct wcd_mbhc_intr *intr_ids = &wcd937x->intr_ids;
1994
1995 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd937x->irq_chip,
1996 WCD937X_IRQ_MBHC_SW_DET);
1997 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd937x->irq_chip,
1998 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET);
1999 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2000 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET);
2001 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2002 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2003 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd937x->irq_chip,
2004 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET);
2005 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd937x->irq_chip,
2006 WCD937X_IRQ_HPHL_OCP_INT);
2007 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd937x->irq_chip,
2008 WCD937X_IRQ_HPHR_OCP_INT);
2009
2010 wcd937x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2011 if (IS_ERR(wcd937x->wcd_mbhc))
2012 return PTR_ERR(wcd937x->wcd_mbhc);
2013
2014 snd_soc_add_component_controls(component, impedance_detect_controls,
2015 ARRAY_SIZE(impedance_detect_controls));
2016 snd_soc_add_component_controls(component, hph_type_detect_controls,
2017 ARRAY_SIZE(hph_type_detect_controls));
2018
2019 return 0;
2020 }
2021
2022 static void wcd937x_mbhc_deinit(struct snd_soc_component *component)
2023 {
2024 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
2025
2026 wcd_mbhc_deinit(wcd937x->wcd_mbhc);
2027 }
2028
2029 /* END MBHC */
2030
2031 static const struct snd_kcontrol_new wcd937x_snd_controls[] = {
2032 SOC_SINGLE_TLV("EAR_PA Volume", WCD937X_ANA_EAR_COMPANDER_CTL,
2033 2, 0x10, 0, ear_pa_gain),
2034 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2035 wcd937x_rx_hph_mode_get, wcd937x_rx_hph_mode_put),
2036
2037 SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
2038 wcd937x_get_compander, wcd937x_set_compander),
2039 SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
2040 wcd937x_get_compander, wcd937x_set_compander),
2041
2042 SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain),
2043 SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain),
2044 SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain),
2045 SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain),
2046 SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain),
2047
2048 SOC_SINGLE_EXT("HPHL Switch", WCD937X_HPH_L, 0, 1, 0,
2049 wcd937x_get_swr_port, wcd937x_set_swr_port),
2050 SOC_SINGLE_EXT("HPHR Switch", WCD937X_HPH_R, 0, 1, 0,
2051 wcd937x_get_swr_port, wcd937x_set_swr_port),
2052
2053 SOC_SINGLE_EXT("ADC1 Switch", WCD937X_ADC1, 1, 1, 0,
2054 wcd937x_get_swr_port, wcd937x_set_swr_port),
2055 SOC_SINGLE_EXT("ADC2 Switch", WCD937X_ADC2, 1, 1, 0,
2056 wcd937x_get_swr_port, wcd937x_set_swr_port),
2057 SOC_SINGLE_EXT("ADC3 Switch", WCD937X_ADC3, 1, 1, 0,
2058 wcd937x_get_swr_port, wcd937x_set_swr_port),
2059 SOC_SINGLE_EXT("DMIC0 Switch", WCD937X_DMIC0, 1, 1, 0,
2060 wcd937x_get_swr_port, wcd937x_set_swr_port),
2061 SOC_SINGLE_EXT("DMIC1 Switch", WCD937X_DMIC1, 1, 1, 0,
2062 wcd937x_get_swr_port, wcd937x_set_swr_port),
2063 SOC_SINGLE_EXT("MBHC Switch", WCD937X_MBHC, 1, 1, 0,
2064 wcd937x_get_swr_port, wcd937x_set_swr_port),
2065 SOC_SINGLE_EXT("DMIC2 Switch", WCD937X_DMIC2, 1, 1, 0,
2066 wcd937x_get_swr_port, wcd937x_set_swr_port),
2067 SOC_SINGLE_EXT("DMIC3 Switch", WCD937X_DMIC3, 1, 1, 0,
2068 wcd937x_get_swr_port, wcd937x_set_swr_port),
2069 SOC_SINGLE_EXT("DMIC4 Switch", WCD937X_DMIC4, 1, 1, 0,
2070 wcd937x_get_swr_port, wcd937x_set_swr_port),
2071 SOC_SINGLE_EXT("DMIC5 Switch", WCD937X_DMIC5, 1, 1, 0,
2072 wcd937x_get_swr_port, wcd937x_set_swr_port),
2073 };
2074
2075 static const struct snd_kcontrol_new adc1_switch[] = {
2076 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2077 };
2078
2079 static const struct snd_kcontrol_new adc2_switch[] = {
2080 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2081 };
2082
2083 static const struct snd_kcontrol_new adc3_switch[] = {
2084 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2085 };
2086
2087 static const struct snd_kcontrol_new dmic1_switch[] = {
2088 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2089 };
2090
2091 static const struct snd_kcontrol_new dmic2_switch[] = {
2092 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2093 };
2094
2095 static const struct snd_kcontrol_new dmic3_switch[] = {
2096 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2097 };
2098
2099 static const struct snd_kcontrol_new dmic4_switch[] = {
2100 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2101 };
2102
2103 static const struct snd_kcontrol_new dmic5_switch[] = {
2104 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2105 };
2106
2107 static const struct snd_kcontrol_new dmic6_switch[] = {
2108 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2109 };
2110
2111 static const struct snd_kcontrol_new ear_rdac_switch[] = {
2112 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2113 };
2114
2115 static const struct snd_kcontrol_new aux_rdac_switch[] = {
2116 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2117 };
2118
2119 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2120 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2121 };
2122
2123 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2124 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2125 };
2126
2127 static const char * const adc2_mux_text[] = {
2128 "INP2", "INP3"
2129 };
2130
2131 static const char * const rdac3_mux_text[] = {
2132 "RX1", "RX3"
2133 };
2134
2135 static const struct soc_enum adc2_enum =
2136 SOC_ENUM_SINGLE(WCD937X_TX_NEW_TX_CH2_SEL, 7,
2137 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2138
2139 static const struct soc_enum rdac3_enum =
2140 SOC_ENUM_SINGLE(WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2141 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2142
2143 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2144
2145 static const struct snd_kcontrol_new rx_rdac3_mux = SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2146
2147 static const struct snd_soc_dapm_widget wcd937x_dapm_widgets[] = {
2148 /* Input widgets */
2149 SND_SOC_DAPM_INPUT("AMIC1"),
2150 SND_SOC_DAPM_INPUT("AMIC2"),
2151 SND_SOC_DAPM_INPUT("AMIC3"),
2152 SND_SOC_DAPM_INPUT("IN1_HPHL"),
2153 SND_SOC_DAPM_INPUT("IN2_HPHR"),
2154 SND_SOC_DAPM_INPUT("IN3_AUX"),
2155
2156 /* TX widgets */
2157 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2158 wcd937x_codec_enable_adc,
2159 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2160 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2161 wcd937x_codec_enable_adc,
2162 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2163
2164 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
2165 NULL, 0, wcd937x_enable_req,
2166 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2167 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 0, 0,
2168 NULL, 0, wcd937x_enable_req,
2169 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2170
2171 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2172
2173 /* TX mixers */
2174 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
2175 adc1_switch, ARRAY_SIZE(adc1_switch),
2176 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2177 SND_SOC_DAPM_POST_PMD),
2178 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 1, 0,
2179 adc2_switch, ARRAY_SIZE(adc2_switch),
2180 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2181 SND_SOC_DAPM_POST_PMD),
2182
2183 /* MIC_BIAS widgets */
2184 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2185 wcd937x_codec_enable_micbias,
2186 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2187 SND_SOC_DAPM_POST_PMD),
2188 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2189 wcd937x_codec_enable_micbias,
2190 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2191 SND_SOC_DAPM_POST_PMD),
2192 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2193 wcd937x_codec_enable_micbias,
2194 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2195 SND_SOC_DAPM_POST_PMD),
2196
2197 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2198 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2199
2200 /* RX widgets */
2201 SND_SOC_DAPM_PGA_E("EAR PGA", WCD937X_ANA_EAR, 7, 0, NULL, 0,
2202 wcd937x_codec_enable_ear_pa,
2203 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2204 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2205 SND_SOC_DAPM_PGA_E("AUX PGA", WCD937X_AUX_AUXPA, 7, 0, NULL, 0,
2206 wcd937x_codec_enable_aux_pa,
2207 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2208 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2209 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD937X_ANA_HPH, 7, 0, NULL, 0,
2210 wcd937x_codec_enable_hphl_pa,
2211 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2212 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2213 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD937X_ANA_HPH, 6, 0, NULL, 0,
2214 wcd937x_codec_enable_hphr_pa,
2215 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2216 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2217
2218 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2219 wcd937x_codec_hphl_dac_event,
2220 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2221 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2222 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2223 wcd937x_codec_hphr_dac_event,
2224 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2225 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2226 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2227 wcd937x_codec_ear_dac_event,
2228 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2229 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2230 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
2231 wcd937x_codec_aux_dac_event,
2232 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2233 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2234
2235 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2236
2237 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
2238 wcd937x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
2239 SND_SOC_DAPM_POST_PMD),
2240 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
2241 wcd937x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
2242 SND_SOC_DAPM_POST_PMD),
2243 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
2244 wcd937x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
2245 SND_SOC_DAPM_POST_PMD),
2246
2247 /* RX mixer widgets*/
2248 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2249 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2250 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
2251 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
2252 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2253 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2254 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2255 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2256
2257 /* TX output widgets */
2258 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2259 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2260 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2261 SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
2262
2263 /* RX output widgets */
2264 SND_SOC_DAPM_OUTPUT("EAR"),
2265 SND_SOC_DAPM_OUTPUT("AUX"),
2266 SND_SOC_DAPM_OUTPUT("HPHL"),
2267 SND_SOC_DAPM_OUTPUT("HPHR"),
2268
2269 /* MIC_BIAS pull up widgets */
2270 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2271 wcd937x_codec_enable_micbias_pullup,
2272 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2273 SND_SOC_DAPM_POST_PMD),
2274 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2275 wcd937x_codec_enable_micbias_pullup,
2276 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2277 SND_SOC_DAPM_POST_PMD),
2278 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2279 wcd937x_codec_enable_micbias_pullup,
2280 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2281 SND_SOC_DAPM_POST_PMD),
2282 };
2283
2284 static const struct snd_soc_dapm_widget wcd9375_dapm_widgets[] = {
2285 /* Input widgets */
2286 SND_SOC_DAPM_INPUT("AMIC4"),
2287
2288 /* TX widgets */
2289 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2290 wcd937x_codec_enable_adc,
2291 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2292
2293 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 0, 0,
2294 NULL, 0, wcd937x_enable_req,
2295 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2296
2297 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2298 wcd937x_codec_enable_dmic,
2299 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2300 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2301 wcd937x_codec_enable_dmic,
2302 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2303 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2304 wcd937x_codec_enable_dmic,
2305 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2306 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2307 wcd937x_codec_enable_dmic,
2308 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2309 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2310 wcd937x_codec_enable_dmic,
2311 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2312 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2313 wcd937x_codec_enable_dmic,
2314 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2315
2316 /* TX mixer widgets */
2317 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0,
2318 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
2319 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2320 SND_SOC_DAPM_POST_PMD),
2321 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 1,
2322 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
2323 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2324 SND_SOC_DAPM_POST_PMD),
2325 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 2,
2326 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
2327 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2328 SND_SOC_DAPM_POST_PMD),
2329 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 3,
2330 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
2331 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2332 SND_SOC_DAPM_POST_PMD),
2333 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 4,
2334 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
2335 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2336 SND_SOC_DAPM_POST_PMD),
2337 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 5,
2338 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
2339 wcd937x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
2340 SND_SOC_DAPM_POST_PMD),
2341 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 2, 0, adc3_switch,
2342 ARRAY_SIZE(adc3_switch), wcd937x_tx_swr_ctrl,
2343 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2344
2345 /* Output widgets */
2346 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2347 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2348 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2349 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2350 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2351 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2352 };
2353
2354 static const struct snd_soc_dapm_route wcd937x_audio_map[] = {
2355 { "ADC1_OUTPUT", NULL, "ADC1_MIXER" },
2356 { "ADC1_MIXER", "Switch", "ADC1 REQ" },
2357 { "ADC1 REQ", NULL, "ADC1" },
2358 { "ADC1", NULL, "AMIC1" },
2359
2360 { "ADC2_OUTPUT", NULL, "ADC2_MIXER" },
2361 { "ADC2_MIXER", "Switch", "ADC2 REQ" },
2362 { "ADC2 REQ", NULL, "ADC2" },
2363 { "ADC2", NULL, "ADC2 MUX" },
2364 { "ADC2 MUX", "INP3", "AMIC3" },
2365 { "ADC2 MUX", "INP2", "AMIC2" },
2366
2367 { "IN1_HPHL", NULL, "VDD_BUCK" },
2368 { "IN1_HPHL", NULL, "CLS_H_PORT" },
2369 { "RX1", NULL, "IN1_HPHL" },
2370 { "RDAC1", NULL, "RX1" },
2371 { "HPHL_RDAC", "Switch", "RDAC1" },
2372 { "HPHL PGA", NULL, "HPHL_RDAC" },
2373 { "HPHL", NULL, "HPHL PGA" },
2374
2375 { "IN2_HPHR", NULL, "VDD_BUCK" },
2376 { "IN2_HPHR", NULL, "CLS_H_PORT" },
2377 { "RX2", NULL, "IN2_HPHR" },
2378 { "RDAC2", NULL, "RX2" },
2379 { "HPHR_RDAC", "Switch", "RDAC2" },
2380 { "HPHR PGA", NULL, "HPHR_RDAC" },
2381 { "HPHR", NULL, "HPHR PGA" },
2382
2383 { "IN3_AUX", NULL, "VDD_BUCK" },
2384 { "IN3_AUX", NULL, "CLS_H_PORT" },
2385 { "RX3", NULL, "IN3_AUX" },
2386 { "RDAC4", NULL, "RX3" },
2387 { "AUX_RDAC", "Switch", "RDAC4" },
2388 { "AUX PGA", NULL, "AUX_RDAC" },
2389 { "AUX", NULL, "AUX PGA" },
2390
2391 { "RDAC3_MUX", "RX3", "RX3" },
2392 { "RDAC3_MUX", "RX1", "RX1" },
2393 { "RDAC3", NULL, "RDAC3_MUX" },
2394 { "EAR_RDAC", "Switch", "RDAC3" },
2395 { "EAR PGA", NULL, "EAR_RDAC" },
2396 { "EAR", NULL, "EAR PGA" },
2397 };
2398
2399 static const struct snd_soc_dapm_route wcd9375_audio_map[] = {
2400 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" },
2401 { "ADC3_OUTPUT", NULL, "ADC3_MIXER" },
2402 { "ADC3_MIXER", "Switch", "ADC3 REQ" },
2403 { "ADC3 REQ", NULL, "ADC3" },
2404 { "ADC3", NULL, "AMIC4" },
2405
2406 { "DMIC1_OUTPUT", NULL, "DMIC1_MIXER" },
2407 { "DMIC1_MIXER", "Switch", "DMIC1" },
2408
2409 { "DMIC2_OUTPUT", NULL, "DMIC2_MIXER" },
2410 { "DMIC2_MIXER", "Switch", "DMIC2" },
2411
2412 { "DMIC3_OUTPUT", NULL, "DMIC3_MIXER" },
2413 { "DMIC3_MIXER", "Switch", "DMIC3" },
2414
2415 { "DMIC4_OUTPUT", NULL, "DMIC4_MIXER" },
2416 { "DMIC4_MIXER", "Switch", "DMIC4" },
2417
2418 { "DMIC5_OUTPUT", NULL, "DMIC5_MIXER" },
2419 { "DMIC5_MIXER", "Switch", "DMIC5" },
2420
2421 { "DMIC6_OUTPUT", NULL, "DMIC6_MIXER" },
2422 { "DMIC6_MIXER", "Switch", "DMIC6" },
2423 };
2424
2425 static int wcd937x_set_micbias_data(struct wcd937x_priv *wcd937x)
2426 {
2427 int vout_ctl[3];
2428
2429 /* Set micbias voltage */
2430 vout_ctl[0] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb1_mv);
2431 vout_ctl[1] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb2_mv);
2432 vout_ctl[2] = wcd937x_get_micb_vout_ctl_val(wcd937x->micb3_mv);
2433 if ((vout_ctl[0] | vout_ctl[1] | vout_ctl[2]) < 0)
2434 return -EINVAL;
2435
2436 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB1, WCD937X_ANA_MICB_VOUT, vout_ctl[0]);
2437 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB2, WCD937X_ANA_MICB_VOUT, vout_ctl[1]);
2438 regmap_update_bits(wcd937x->regmap, WCD937X_ANA_MICB3, WCD937X_ANA_MICB_VOUT, vout_ctl[2]);
2439
2440 return 0;
2441 }
2442
2443 static irqreturn_t wcd937x_wd_handle_irq(int irq, void *data)
2444 {
2445 return IRQ_HANDLED;
2446 }
2447
2448 static const struct irq_chip wcd_irq_chip = {
2449 .name = "WCD937x",
2450 };
2451
2452 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2453 irq_hw_number_t hw)
2454 {
2455 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2456 irq_set_nested_thread(virq, 1);
2457 irq_set_noprobe(virq);
2458
2459 return 0;
2460 }
2461
2462 static const struct irq_domain_ops wcd_domain_ops = {
2463 .map = wcd_irq_chip_map,
2464 };
2465
2466 static int wcd937x_irq_init(struct wcd937x_priv *wcd, struct device *dev)
2467 {
2468 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
2469 if (!(wcd->virq)) {
2470 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2471 return -EINVAL;
2472 }
2473
2474 return devm_regmap_add_irq_chip(dev, wcd->regmap,
2475 irq_create_mapping(wcd->virq, 0),
2476 IRQF_ONESHOT, 0, &wcd937x_regmap_irq_chip,
2477 &wcd->irq_chip);
2478 }
2479
2480 static int wcd937x_soc_codec_probe(struct snd_soc_component *component)
2481 {
2482 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2483 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
2484 struct sdw_slave *tx_sdw_dev = wcd937x->tx_sdw_dev;
2485 struct device *dev = component->dev;
2486 unsigned long time_left;
2487 int i, ret;
2488 u32 chipid;
2489
2490 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
2491 msecs_to_jiffies(5000));
2492 if (!time_left) {
2493 dev_err(dev, "soundwire device init timeout\n");
2494 return -ETIMEDOUT;
2495 }
2496
2497 snd_soc_component_init_regmap(component, wcd937x->regmap);
2498 ret = pm_runtime_resume_and_get(dev);
2499 if (ret < 0)
2500 return ret;
2501
2502 chipid = (snd_soc_component_read(component,
2503 WCD937X_DIGITAL_EFUSE_REG_0) & 0x1e) >> 1;
2504 if (chipid != CHIPID_WCD9370 && chipid != CHIPID_WCD9375) {
2505 dev_err(dev, "Got unknown chip id: 0x%x\n", chipid);
2506 pm_runtime_put(dev);
2507 return -EINVAL;
2508 }
2509
2510 wcd937x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD937X);
2511 if (IS_ERR(wcd937x->clsh_info)) {
2512 pm_runtime_put(dev);
2513 return PTR_ERR(wcd937x->clsh_info);
2514 }
2515
2516 wcd937x_io_init(wcd937x->regmap);
2517 /* Set all interrupts as edge triggered */
2518 for (i = 0; i < wcd937x_regmap_irq_chip.num_regs; i++)
2519 regmap_write(wcd937x->regmap, (WCD937X_DIGITAL_INTR_LEVEL_0 + i), 0);
2520
2521 pm_runtime_put(dev);
2522
2523 wcd937x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip,
2524 WCD937X_IRQ_HPHR_PDM_WD_INT);
2525 wcd937x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip,
2526 WCD937X_IRQ_HPHL_PDM_WD_INT);
2527 wcd937x->aux_pdm_wd_int = regmap_irq_get_virq(wcd937x->irq_chip,
2528 WCD937X_IRQ_AUX_PDM_WD_INT);
2529
2530 /* Request for watchdog interrupt */
2531 ret = devm_request_threaded_irq(dev, wcd937x->hphr_pdm_wd_int, NULL, wcd937x_wd_handle_irq,
2532 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2533 "HPHR PDM WDOG INT", wcd937x);
2534 if (ret)
2535 dev_err(dev, "Failed to request HPHR watchdog interrupt (%d)\n", ret);
2536
2537 ret = devm_request_threaded_irq(dev, wcd937x->hphl_pdm_wd_int, NULL, wcd937x_wd_handle_irq,
2538 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2539 "HPHL PDM WDOG INT", wcd937x);
2540 if (ret)
2541 dev_err(dev, "Failed to request HPHL watchdog interrupt (%d)\n", ret);
2542
2543 ret = devm_request_threaded_irq(dev, wcd937x->aux_pdm_wd_int, NULL, wcd937x_wd_handle_irq,
2544 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2545 "AUX PDM WDOG INT", wcd937x);
2546 if (ret)
2547 dev_err(dev, "Failed to request Aux watchdog interrupt (%d)\n", ret);
2548
2549 /* Disable watchdog interrupt for HPH and AUX */
2550 disable_irq_nosync(wcd937x->hphr_pdm_wd_int);
2551 disable_irq_nosync(wcd937x->hphl_pdm_wd_int);
2552 disable_irq_nosync(wcd937x->aux_pdm_wd_int);
2553
2554 if (chipid == CHIPID_WCD9375) {
2555 ret = snd_soc_dapm_new_controls(dapm, wcd9375_dapm_widgets,
2556 ARRAY_SIZE(wcd9375_dapm_widgets));
2557 if (ret < 0) {
2558 dev_err(component->dev, "Failed to add snd_ctls\n");
2559 return ret;
2560 }
2561
2562 ret = snd_soc_dapm_add_routes(dapm, wcd9375_audio_map,
2563 ARRAY_SIZE(wcd9375_audio_map));
2564 if (ret < 0) {
2565 dev_err(component->dev, "Failed to add routes\n");
2566 return ret;
2567 }
2568 }
2569
2570 ret = wcd937x_mbhc_init(component);
2571 if (ret)
2572 dev_err(component->dev, "mbhc initialization failed\n");
2573
2574 return ret;
2575 }
2576
2577 static void wcd937x_soc_codec_remove(struct snd_soc_component *component)
2578 {
2579 struct wcd937x_priv *wcd937x = snd_soc_component_get_drvdata(component);
2580
2581 wcd937x_mbhc_deinit(component);
2582 free_irq(wcd937x->aux_pdm_wd_int, wcd937x);
2583 free_irq(wcd937x->hphl_pdm_wd_int, wcd937x);
2584 free_irq(wcd937x->hphr_pdm_wd_int, wcd937x);
2585
2586 wcd_clsh_ctrl_free(wcd937x->clsh_info);
2587 }
2588
2589 static int wcd937x_codec_set_jack(struct snd_soc_component *comp,
2590 struct snd_soc_jack *jack, void *data)
2591 {
2592 struct wcd937x_priv *wcd = dev_get_drvdata(comp->dev);
2593 int ret = 0;
2594
2595 if (jack)
2596 ret = wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
2597 else
2598 wcd_mbhc_stop(wcd->wcd_mbhc);
2599
2600 return ret;
2601 }
2602
2603 static const struct snd_soc_component_driver soc_codec_dev_wcd937x = {
2604 .name = "wcd937x_codec",
2605 .probe = wcd937x_soc_codec_probe,
2606 .remove = wcd937x_soc_codec_remove,
2607 .controls = wcd937x_snd_controls,
2608 .num_controls = ARRAY_SIZE(wcd937x_snd_controls),
2609 .dapm_widgets = wcd937x_dapm_widgets,
2610 .num_dapm_widgets = ARRAY_SIZE(wcd937x_dapm_widgets),
2611 .dapm_routes = wcd937x_audio_map,
2612 .num_dapm_routes = ARRAY_SIZE(wcd937x_audio_map),
2613 .set_jack = wcd937x_codec_set_jack,
2614 .endianness = 1,
2615 };
2616
2617 static void wcd937x_dt_parse_micbias_info(struct device *dev, struct wcd937x_priv *wcd)
2618 {
2619 struct device_node *np = dev->of_node;
2620 u32 prop_val = 0;
2621 int ret = 0;
2622
2623 ret = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
2624 if (!ret)
2625 wcd->micb1_mv = prop_val / 1000;
2626 else
2627 dev_warn(dev, "Micbias1 DT property not found\n");
2628
2629 ret = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
2630 if (!ret)
2631 wcd->micb2_mv = prop_val / 1000;
2632 else
2633 dev_warn(dev, "Micbias2 DT property not found\n");
2634
2635 ret = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
2636 if (!ret)
2637 wcd->micb3_mv = prop_val / 1000;
2638 else
2639 dev_warn(dev, "Micbias3 DT property not found\n");
2640 }
2641
2642 static bool wcd937x_swap_gnd_mic(struct snd_soc_component *component, bool active)
2643 {
2644 int value;
2645 struct wcd937x_priv *wcd937x;
2646
2647 wcd937x = snd_soc_component_get_drvdata(component);
2648
2649 value = gpiod_get_value(wcd937x->us_euro_gpio);
2650 gpiod_set_value(wcd937x->us_euro_gpio, !value);
2651
2652 return true;
2653 }
2654
2655 static int wcd937x_codec_hw_params(struct snd_pcm_substream *substream,
2656 struct snd_pcm_hw_params *params,
2657 struct snd_soc_dai *dai)
2658 {
2659 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev);
2660 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id];
2661
2662 return wcd937x_sdw_hw_params(wcd, substream, params, dai);
2663 }
2664
2665 static int wcd937x_codec_free(struct snd_pcm_substream *substream,
2666 struct snd_soc_dai *dai)
2667 {
2668 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev);
2669 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id];
2670
2671 return sdw_stream_remove_slave(wcd->sdev, wcd->sruntime);
2672 }
2673
2674 static int wcd937x_codec_set_sdw_stream(struct snd_soc_dai *dai,
2675 void *stream, int direction)
2676 {
2677 struct wcd937x_priv *wcd937x = dev_get_drvdata(dai->dev);
2678 struct wcd937x_sdw_priv *wcd = wcd937x->sdw_priv[dai->id];
2679
2680 wcd->sruntime = stream;
2681
2682 return 0;
2683 }
2684
2685 static const struct snd_soc_dai_ops wcd937x_sdw_dai_ops = {
2686 .hw_params = wcd937x_codec_hw_params,
2687 .hw_free = wcd937x_codec_free,
2688 .set_stream = wcd937x_codec_set_sdw_stream,
2689 };
2690
2691 static struct snd_soc_dai_driver wcd937x_dais[] = {
2692 [0] = {
2693 .name = "wcd937x-sdw-rx",
2694 .playback = {
2695 .stream_name = "WCD AIF Playback",
2696 .rates = WCD937X_RATES | WCD937X_FRAC_RATES,
2697 .formats = WCD937X_FORMATS,
2698 .rate_min = 8000,
2699 .rate_max = 384000,
2700 .channels_min = 1,
2701 .channels_max = 4,
2702 },
2703 .ops = &wcd937x_sdw_dai_ops,
2704 },
2705 [1] = {
2706 .name = "wcd937x-sdw-tx",
2707 .capture = {
2708 .stream_name = "WCD AIF Capture",
2709 .rates = WCD937X_RATES,
2710 .formats = WCD937X_FORMATS,
2711 .rate_min = 8000,
2712 .rate_max = 192000,
2713 .channels_min = 1,
2714 .channels_max = 4,
2715 },
2716 .ops = &wcd937x_sdw_dai_ops,
2717 },
2718 };
2719
2720 static int wcd937x_bind(struct device *dev)
2721 {
2722 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
2723 int ret;
2724
2725 /* Give the SDW subdevices some more time to settle */
2726 usleep_range(5000, 5010);
2727
2728 ret = component_bind_all(dev, wcd937x);
2729 if (ret) {
2730 dev_err(dev, "Slave bind failed, ret = %d\n", ret);
2731 return ret;
2732 }
2733
2734 wcd937x->rxdev = wcd937x_sdw_device_get(wcd937x->rxnode);
2735 if (!wcd937x->rxdev) {
2736 dev_err(dev, "could not find slave with matching of node\n");
2737 return -EINVAL;
2738 }
2739
2740 wcd937x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd937x->rxdev);
2741 wcd937x->sdw_priv[AIF1_PB]->wcd937x = wcd937x;
2742
2743 wcd937x->txdev = wcd937x_sdw_device_get(wcd937x->txnode);
2744 if (!wcd937x->txdev) {
2745 dev_err(dev, "could not find txslave with matching of node\n");
2746 return -EINVAL;
2747 }
2748
2749 wcd937x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd937x->txdev);
2750 wcd937x->sdw_priv[AIF1_CAP]->wcd937x = wcd937x;
2751 wcd937x->tx_sdw_dev = dev_to_sdw_dev(wcd937x->txdev);
2752 if (!wcd937x->tx_sdw_dev) {
2753 dev_err(dev, "could not get txslave with matching of dev\n");
2754 return -EINVAL;
2755 }
2756
2757 /*
2758 * As TX is the main CSR reg interface, which should not be suspended first.
2759 * expicilty add the dependency link
2760 */
2761 if (!device_link_add(wcd937x->rxdev, wcd937x->txdev,
2762 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) {
2763 dev_err(dev, "Could not devlink TX and RX\n");
2764 return -EINVAL;
2765 }
2766
2767 if (!device_link_add(dev, wcd937x->txdev,
2768 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) {
2769 dev_err(dev, "Could not devlink WCD and TX\n");
2770 return -EINVAL;
2771 }
2772
2773 if (!device_link_add(dev, wcd937x->rxdev,
2774 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) {
2775 dev_err(dev, "Could not devlink WCD and RX\n");
2776 return -EINVAL;
2777 }
2778
2779 wcd937x->regmap = dev_get_regmap(&wcd937x->tx_sdw_dev->dev, NULL);
2780 if (!wcd937x->regmap) {
2781 dev_err(dev, "could not get TX device regmap\n");
2782 return -EINVAL;
2783 }
2784
2785 ret = wcd937x_irq_init(wcd937x, dev);
2786 if (ret) {
2787 dev_err(dev, "IRQ init failed: %d\n", ret);
2788 return ret;
2789 }
2790
2791 wcd937x->sdw_priv[AIF1_PB]->slave_irq = wcd937x->virq;
2792 wcd937x->sdw_priv[AIF1_CAP]->slave_irq = wcd937x->virq;
2793
2794 ret = wcd937x_set_micbias_data(wcd937x);
2795 if (ret < 0) {
2796 dev_err(dev, "Bad micbias pdata\n");
2797 return ret;
2798 }
2799
2800 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd937x,
2801 wcd937x_dais, ARRAY_SIZE(wcd937x_dais));
2802 if (ret)
2803 dev_err(dev, "Codec registration failed\n");
2804
2805 return ret;
2806 }
2807
2808 static void wcd937x_unbind(struct device *dev)
2809 {
2810 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
2811
2812 snd_soc_unregister_component(dev);
2813 device_link_remove(dev, wcd937x->txdev);
2814 device_link_remove(dev, wcd937x->rxdev);
2815 device_link_remove(wcd937x->rxdev, wcd937x->txdev);
2816 component_unbind_all(dev, wcd937x);
2817 mutex_destroy(&wcd937x->micb_lock);
2818 }
2819
2820 static const struct component_master_ops wcd937x_comp_ops = {
2821 .bind = wcd937x_bind,
2822 .unbind = wcd937x_unbind,
2823 };
2824
2825 static int wcd937x_add_slave_components(struct wcd937x_priv *wcd937x,
2826 struct device *dev,
2827 struct component_match **matchptr)
2828 {
2829 struct device_node *np = dev->of_node;
2830
2831 wcd937x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
2832 if (!wcd937x->rxnode) {
2833 dev_err(dev, "Couldn't parse phandle to qcom,rx-device!\n");
2834 return -ENODEV;
2835 }
2836 of_node_get(wcd937x->rxnode);
2837 component_match_add_release(dev, matchptr, component_release_of,
2838 component_compare_of, wcd937x->rxnode);
2839
2840 wcd937x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
2841 if (!wcd937x->txnode) {
2842 dev_err(dev, "Couldn't parse phandle to qcom,tx-device\n");
2843 return -ENODEV;
2844 }
2845 of_node_get(wcd937x->txnode);
2846 component_match_add_release(dev, matchptr, component_release_of,
2847 component_compare_of, wcd937x->txnode);
2848
2849 return 0;
2850 }
2851
2852 static int wcd937x_probe(struct platform_device *pdev)
2853 {
2854 struct component_match *match = NULL;
2855 struct device *dev = &pdev->dev;
2856 struct wcd937x_priv *wcd937x;
2857 struct wcd_mbhc_config *cfg;
2858 int ret;
2859
2860 wcd937x = devm_kzalloc(dev, sizeof(*wcd937x), GFP_KERNEL);
2861 if (!wcd937x)
2862 return -ENOMEM;
2863
2864 dev_set_drvdata(dev, wcd937x);
2865 mutex_init(&wcd937x->micb_lock);
2866
2867 wcd937x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2868 if (IS_ERR(wcd937x->reset_gpio))
2869 return dev_err_probe(dev, PTR_ERR(wcd937x->reset_gpio),
2870 "failed to reset wcd gpio\n");
2871
2872 wcd937x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW);
2873 if (IS_ERR(wcd937x->us_euro_gpio))
2874 return dev_err_probe(dev, PTR_ERR(wcd937x->us_euro_gpio),
2875 "us-euro swap Control GPIO not found\n");
2876
2877 cfg = &wcd937x->mbhc_cfg;
2878 cfg->swap_gnd_mic = wcd937x_swap_gnd_mic;
2879
2880 wcd937x->supplies[0].supply = "vdd-rxtx";
2881 wcd937x->supplies[1].supply = "vdd-px";
2882 wcd937x->supplies[2].supply = "vdd-mic-bias";
2883 wcd937x->supplies[3].supply = "vdd-buck";
2884
2885 ret = devm_regulator_bulk_get(dev, WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2886 if (ret)
2887 return dev_err_probe(dev, ret, "Failed to get supplies\n");
2888
2889 ret = regulator_bulk_enable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2890 if (ret) {
2891 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2892 return dev_err_probe(dev, ret, "Failed to enable supplies\n");
2893 }
2894
2895 wcd937x_dt_parse_micbias_info(dev, wcd937x);
2896
2897 cfg->mbhc_micbias = MIC_BIAS_2;
2898 cfg->anc_micbias = MIC_BIAS_2;
2899 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
2900 cfg->num_btn = WCD937X_MBHC_MAX_BUTTONS;
2901 cfg->micb_mv = wcd937x->micb2_mv;
2902 cfg->linein_th = 5000;
2903 cfg->hs_thr = 1700;
2904 cfg->hph_thr = 50;
2905
2906 wcd_dt_parse_mbhc_data(dev, &wcd937x->mbhc_cfg);
2907
2908 ret = wcd937x_add_slave_components(wcd937x, dev, &match);
2909 if (ret)
2910 goto err_disable_regulators;
2911
2912 wcd937x_reset(wcd937x);
2913
2914 ret = component_master_add_with_match(dev, &wcd937x_comp_ops, match);
2915 if (ret)
2916 goto err_disable_regulators;
2917
2918 pm_runtime_set_autosuspend_delay(dev, 1000);
2919 pm_runtime_use_autosuspend(dev);
2920 pm_runtime_mark_last_busy(dev);
2921 pm_runtime_set_active(dev);
2922 pm_runtime_enable(dev);
2923 pm_runtime_idle(dev);
2924
2925 return 0;
2926
2927 err_disable_regulators:
2928 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2929 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2930
2931 return ret;
2932 }
2933
2934 static void wcd937x_remove(struct platform_device *pdev)
2935 {
2936 struct device *dev = &pdev->dev;
2937 struct wcd937x_priv *wcd937x = dev_get_drvdata(dev);
2938
2939 component_master_del(&pdev->dev, &wcd937x_comp_ops);
2940
2941 pm_runtime_disable(dev);
2942 pm_runtime_set_suspended(dev);
2943 pm_runtime_dont_use_autosuspend(dev);
2944
2945 regulator_bulk_disable(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2946 regulator_bulk_free(WCD937X_MAX_BULK_SUPPLY, wcd937x->supplies);
2947 }
2948
2949 #if defined(CONFIG_OF)
2950 static const struct of_device_id wcd937x_of_match[] = {
2951 { .compatible = "qcom,wcd9370-codec" },
2952 { .compatible = "qcom,wcd9375-codec" },
2953 { }
2954 };
2955 MODULE_DEVICE_TABLE(of, wcd937x_of_match);
2956 #endif
2957
2958 static struct platform_driver wcd937x_codec_driver = {
2959 .probe = wcd937x_probe,
2960 .remove_new = wcd937x_remove,
2961 .driver = {
2962 .name = "wcd937x_codec",
2963 .of_match_table = of_match_ptr(wcd937x_of_match),
2964 .suppress_bind_attrs = true,
2965 },
2966 };
2967
2968 module_platform_driver(wcd937x_codec_driver);
2969 MODULE_DESCRIPTION("WCD937X Codec driver");
2970 MODULE_LICENSE("GPL");
2971
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