1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * wm5100.h -- WM5100 ALSA SoC Audio driver 4 * 5 * Copyright 2011 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #ifndef WM5100_ASOC_H 11 #define WM5100_ASOC_H 12 13 #include <sound/soc.h> 14 #include <linux/regmap.h> 15 16 int wm5100_detect(struct snd_soc_component *component, struct snd_soc_jack *jack); 17 18 #define WM5100_CLK_AIF1 1 19 #define WM5100_CLK_AIF2 2 20 #define WM5100_CLK_AIF3 3 21 #define WM5100_CLK_SYSCLK 4 22 #define WM5100_CLK_ASYNCCLK 5 23 #define WM5100_CLK_32KHZ 6 24 #define WM5100_CLK_OPCLK 7 25 26 #define WM5100_CLKSRC_MCLK1 0 27 #define WM5100_CLKSRC_MCLK2 1 28 #define WM5100_CLKSRC_SYSCLK 2 29 #define WM5100_CLKSRC_FLL1 4 30 #define WM5100_CLKSRC_FLL2 5 31 #define WM5100_CLKSRC_AIF1BCLK 8 32 #define WM5100_CLKSRC_AIF2BCLK 9 33 #define WM5100_CLKSRC_AIF3BCLK 10 34 #define WM5100_CLKSRC_ASYNCCLK 0x100 35 36 #define WM5100_FLL1 1 37 #define WM5100_FLL2 2 38 39 #define WM5100_FLL_SRC_MCLK1 0x0 40 #define WM5100_FLL_SRC_MCLK2 0x1 41 #define WM5100_FLL_SRC_FLL1 0x4 42 #define WM5100_FLL_SRC_FLL2 0x5 43 #define WM5100_FLL_SRC_AIF1BCLK 0x8 44 #define WM5100_FLL_SRC_AIF2BCLK 0x9 45 #define WM5100_FLL_SRC_AIF3BCLK 0xa 46 47 /* 48 * Register values. 49 */ 50 #define WM5100_SOFTWARE_RESET 0x00 51 #define WM5100_DEVICE_REVISION 0x01 52 #define WM5100_CTRL_IF_1 0x10 53 #define WM5100_TONE_GENERATOR_1 0x20 54 #define WM5100_PWM_DRIVE_1 0x30 55 #define WM5100_PWM_DRIVE_2 0x31 56 #define WM5100_PWM_DRIVE_3 0x32 57 #define WM5100_CLOCKING_1 0x100 58 #define WM5100_CLOCKING_3 0x101 59 #define WM5100_CLOCKING_4 0x102 60 #define WM5100_CLOCKING_5 0x103 61 #define WM5100_CLOCKING_6 0x104 62 #define WM5100_CLOCKING_7 0x107 63 #define WM5100_CLOCKING_8 0x108 64 #define WM5100_ASRC_ENABLE 0x120 65 #define WM5100_ASRC_STATUS 0x121 66 #define WM5100_ASRC_RATE1 0x122 67 #define WM5100_ISRC_1_CTRL_1 0x141 68 #define WM5100_ISRC_1_CTRL_2 0x142 69 #define WM5100_ISRC_2_CTRL1 0x143 70 #define WM5100_ISRC_2_CTRL_2 0x144 71 #define WM5100_FLL1_CONTROL_1 0x182 72 #define WM5100_FLL1_CONTROL_2 0x183 73 #define WM5100_FLL1_CONTROL_3 0x184 74 #define WM5100_FLL1_CONTROL_5 0x186 75 #define WM5100_FLL1_CONTROL_6 0x187 76 #define WM5100_FLL1_EFS_1 0x188 77 #define WM5100_FLL2_CONTROL_1 0x1A2 78 #define WM5100_FLL2_CONTROL_2 0x1A3 79 #define WM5100_FLL2_CONTROL_3 0x1A4 80 #define WM5100_FLL2_CONTROL_5 0x1A6 81 #define WM5100_FLL2_CONTROL_6 0x1A7 82 #define WM5100_FLL2_EFS_1 0x1A8 83 #define WM5100_MIC_CHARGE_PUMP_1 0x200 84 #define WM5100_MIC_CHARGE_PUMP_2 0x201 85 #define WM5100_HP_CHARGE_PUMP_1 0x202 86 #define WM5100_LDO1_CONTROL 0x211 87 #define WM5100_MIC_BIAS_CTRL_1 0x215 88 #define WM5100_MIC_BIAS_CTRL_2 0x216 89 #define WM5100_MIC_BIAS_CTRL_3 0x217 90 #define WM5100_ACCESSORY_DETECT_MODE_1 0x280 91 #define WM5100_HEADPHONE_DETECT_1 0x288 92 #define WM5100_HEADPHONE_DETECT_2 0x289 93 #define WM5100_MIC_DETECT_1 0x290 94 #define WM5100_MIC_DETECT_2 0x291 95 #define WM5100_MIC_DETECT_3 0x292 96 #define WM5100_MISC_CONTROL 0x2BB 97 #define WM5100_INPUT_ENABLES 0x301 98 #define WM5100_INPUT_ENABLES_STATUS 0x302 99 #define WM5100_IN1L_CONTROL 0x310 100 #define WM5100_IN1R_CONTROL 0x311 101 #define WM5100_IN2L_CONTROL 0x312 102 #define WM5100_IN2R_CONTROL 0x313 103 #define WM5100_IN3L_CONTROL 0x314 104 #define WM5100_IN3R_CONTROL 0x315 105 #define WM5100_IN4L_CONTROL 0x316 106 #define WM5100_IN4R_CONTROL 0x317 107 #define WM5100_RXANC_SRC 0x318 108 #define WM5100_INPUT_VOLUME_RAMP 0x319 109 #define WM5100_ADC_DIGITAL_VOLUME_1L 0x320 110 #define WM5100_ADC_DIGITAL_VOLUME_1R 0x321 111 #define WM5100_ADC_DIGITAL_VOLUME_2L 0x322 112 #define WM5100_ADC_DIGITAL_VOLUME_2R 0x323 113 #define WM5100_ADC_DIGITAL_VOLUME_3L 0x324 114 #define WM5100_ADC_DIGITAL_VOLUME_3R 0x325 115 #define WM5100_ADC_DIGITAL_VOLUME_4L 0x326 116 #define WM5100_ADC_DIGITAL_VOLUME_4R 0x327 117 #define WM5100_OUTPUT_ENABLES_2 0x401 118 #define WM5100_OUTPUT_STATUS_1 0x402 119 #define WM5100_OUTPUT_STATUS_2 0x403 120 #define WM5100_CHANNEL_ENABLES_1 0x408 121 #define WM5100_OUT_VOLUME_1L 0x410 122 #define WM5100_OUT_VOLUME_1R 0x411 123 #define WM5100_DAC_VOLUME_LIMIT_1L 0x412 124 #define WM5100_DAC_VOLUME_LIMIT_1R 0x413 125 #define WM5100_OUT_VOLUME_2L 0x414 126 #define WM5100_OUT_VOLUME_2R 0x415 127 #define WM5100_DAC_VOLUME_LIMIT_2L 0x416 128 #define WM5100_DAC_VOLUME_LIMIT_2R 0x417 129 #define WM5100_OUT_VOLUME_3L 0x418 130 #define WM5100_OUT_VOLUME_3R 0x419 131 #define WM5100_DAC_VOLUME_LIMIT_3L 0x41A 132 #define WM5100_DAC_VOLUME_LIMIT_3R 0x41B 133 #define WM5100_OUT_VOLUME_4L 0x41C 134 #define WM5100_OUT_VOLUME_4R 0x41D 135 #define WM5100_DAC_VOLUME_LIMIT_5L 0x41E 136 #define WM5100_DAC_VOLUME_LIMIT_5R 0x41F 137 #define WM5100_DAC_VOLUME_LIMIT_6L 0x420 138 #define WM5100_DAC_VOLUME_LIMIT_6R 0x421 139 #define WM5100_DAC_AEC_CONTROL_1 0x440 140 #define WM5100_OUTPUT_VOLUME_RAMP 0x441 141 #define WM5100_DAC_DIGITAL_VOLUME_1L 0x480 142 #define WM5100_DAC_DIGITAL_VOLUME_1R 0x481 143 #define WM5100_DAC_DIGITAL_VOLUME_2L 0x482 144 #define WM5100_DAC_DIGITAL_VOLUME_2R 0x483 145 #define WM5100_DAC_DIGITAL_VOLUME_3L 0x484 146 #define WM5100_DAC_DIGITAL_VOLUME_3R 0x485 147 #define WM5100_DAC_DIGITAL_VOLUME_4L 0x486 148 #define WM5100_DAC_DIGITAL_VOLUME_4R 0x487 149 #define WM5100_DAC_DIGITAL_VOLUME_5L 0x488 150 #define WM5100_DAC_DIGITAL_VOLUME_5R 0x489 151 #define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A 152 #define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B 153 #define WM5100_PDM_SPK1_CTRL_1 0x4C0 154 #define WM5100_PDM_SPK1_CTRL_2 0x4C1 155 #define WM5100_PDM_SPK2_CTRL_1 0x4C2 156 #define WM5100_PDM_SPK2_CTRL_2 0x4C3 157 #define WM5100_AUDIO_IF_1_1 0x500 158 #define WM5100_AUDIO_IF_1_2 0x501 159 #define WM5100_AUDIO_IF_1_3 0x502 160 #define WM5100_AUDIO_IF_1_4 0x503 161 #define WM5100_AUDIO_IF_1_5 0x504 162 #define WM5100_AUDIO_IF_1_6 0x505 163 #define WM5100_AUDIO_IF_1_7 0x506 164 #define WM5100_AUDIO_IF_1_8 0x507 165 #define WM5100_AUDIO_IF_1_9 0x508 166 #define WM5100_AUDIO_IF_1_10 0x509 167 #define WM5100_AUDIO_IF_1_11 0x50A 168 #define WM5100_AUDIO_IF_1_12 0x50B 169 #define WM5100_AUDIO_IF_1_13 0x50C 170 #define WM5100_AUDIO_IF_1_14 0x50D 171 #define WM5100_AUDIO_IF_1_15 0x50E 172 #define WM5100_AUDIO_IF_1_16 0x50F 173 #define WM5100_AUDIO_IF_1_17 0x510 174 #define WM5100_AUDIO_IF_1_18 0x511 175 #define WM5100_AUDIO_IF_1_19 0x512 176 #define WM5100_AUDIO_IF_1_20 0x513 177 #define WM5100_AUDIO_IF_1_21 0x514 178 #define WM5100_AUDIO_IF_1_22 0x515 179 #define WM5100_AUDIO_IF_1_23 0x516 180 #define WM5100_AUDIO_IF_1_24 0x517 181 #define WM5100_AUDIO_IF_1_25 0x518 182 #define WM5100_AUDIO_IF_1_26 0x519 183 #define WM5100_AUDIO_IF_1_27 0x51A 184 #define WM5100_AUDIO_IF_2_1 0x540 185 #define WM5100_AUDIO_IF_2_2 0x541 186 #define WM5100_AUDIO_IF_2_3 0x542 187 #define WM5100_AUDIO_IF_2_4 0x543 188 #define WM5100_AUDIO_IF_2_5 0x544 189 #define WM5100_AUDIO_IF_2_6 0x545 190 #define WM5100_AUDIO_IF_2_7 0x546 191 #define WM5100_AUDIO_IF_2_8 0x547 192 #define WM5100_AUDIO_IF_2_9 0x548 193 #define WM5100_AUDIO_IF_2_10 0x549 194 #define WM5100_AUDIO_IF_2_11 0x54A 195 #define WM5100_AUDIO_IF_2_18 0x551 196 #define WM5100_AUDIO_IF_2_19 0x552 197 #define WM5100_AUDIO_IF_2_26 0x559 198 #define WM5100_AUDIO_IF_2_27 0x55A 199 #define WM5100_AUDIO_IF_3_1 0x580 200 #define WM5100_AUDIO_IF_3_2 0x581 201 #define WM5100_AUDIO_IF_3_3 0x582 202 #define WM5100_AUDIO_IF_3_4 0x583 203 #define WM5100_AUDIO_IF_3_5 0x584 204 #define WM5100_AUDIO_IF_3_6 0x585 205 #define WM5100_AUDIO_IF_3_7 0x586 206 #define WM5100_AUDIO_IF_3_8 0x587 207 #define WM5100_AUDIO_IF_3_9 0x588 208 #define WM5100_AUDIO_IF_3_10 0x589 209 #define WM5100_AUDIO_IF_3_11 0x58A 210 #define WM5100_AUDIO_IF_3_18 0x591 211 #define WM5100_AUDIO_IF_3_19 0x592 212 #define WM5100_AUDIO_IF_3_26 0x599 213 #define WM5100_AUDIO_IF_3_27 0x59A 214 #define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640 215 #define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641 216 #define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642 217 #define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643 218 #define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644 219 #define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645 220 #define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646 221 #define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647 222 #define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648 223 #define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649 224 #define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A 225 #define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B 226 #define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C 227 #define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D 228 #define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E 229 #define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F 230 #define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680 231 #define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681 232 #define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682 233 #define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683 234 #define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684 235 #define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685 236 #define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686 237 #define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687 238 #define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688 239 #define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689 240 #define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A 241 #define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B 242 #define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C 243 #define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D 244 #define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E 245 #define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F 246 #define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690 247 #define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691 248 #define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692 249 #define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693 250 #define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694 251 #define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695 252 #define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696 253 #define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697 254 #define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698 255 #define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699 256 #define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A 257 #define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B 258 #define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C 259 #define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D 260 #define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E 261 #define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F 262 #define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0 263 #define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1 264 #define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2 265 #define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3 266 #define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4 267 #define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5 268 #define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6 269 #define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7 270 #define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8 271 #define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9 272 #define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA 273 #define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB 274 #define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC 275 #define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD 276 #define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE 277 #define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF 278 #define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0 279 #define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1 280 #define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2 281 #define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3 282 #define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4 283 #define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5 284 #define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6 285 #define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7 286 #define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8 287 #define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9 288 #define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA 289 #define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB 290 #define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC 291 #define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD 292 #define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE 293 #define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF 294 #define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0 295 #define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1 296 #define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2 297 #define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3 298 #define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4 299 #define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5 300 #define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6 301 #define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7 302 #define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8 303 #define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9 304 #define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA 305 #define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB 306 #define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC 307 #define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD 308 #define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE 309 #define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF 310 #define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0 311 #define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1 312 #define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2 313 #define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3 314 #define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4 315 #define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5 316 #define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6 317 #define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7 318 #define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8 319 #define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9 320 #define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA 321 #define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB 322 #define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC 323 #define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD 324 #define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE 325 #define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF 326 #define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700 327 #define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701 328 #define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702 329 #define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703 330 #define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704 331 #define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705 332 #define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706 333 #define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707 334 #define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708 335 #define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709 336 #define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A 337 #define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B 338 #define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C 339 #define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D 340 #define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E 341 #define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F 342 #define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710 343 #define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711 344 #define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712 345 #define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713 346 #define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714 347 #define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715 348 #define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716 349 #define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717 350 #define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718 351 #define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719 352 #define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A 353 #define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B 354 #define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C 355 #define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D 356 #define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E 357 #define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F 358 #define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720 359 #define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721 360 #define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722 361 #define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723 362 #define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724 363 #define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725 364 #define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726 365 #define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727 366 #define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728 367 #define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729 368 #define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A 369 #define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B 370 #define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C 371 #define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D 372 #define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E 373 #define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F 374 #define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730 375 #define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731 376 #define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732 377 #define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733 378 #define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734 379 #define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735 380 #define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736 381 #define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737 382 #define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738 383 #define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739 384 #define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A 385 #define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B 386 #define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C 387 #define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D 388 #define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E 389 #define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F 390 #define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740 391 #define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741 392 #define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742 393 #define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743 394 #define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744 395 #define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745 396 #define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746 397 #define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747 398 #define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748 399 #define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749 400 #define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A 401 #define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B 402 #define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C 403 #define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D 404 #define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E 405 #define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F 406 #define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780 407 #define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781 408 #define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782 409 #define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783 410 #define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784 411 #define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785 412 #define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786 413 #define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787 414 #define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788 415 #define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789 416 #define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A 417 #define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B 418 #define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C 419 #define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 420 #define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 421 #define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 422 #define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880 423 #define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881 424 #define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882 425 #define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883 426 #define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884 427 #define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885 428 #define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886 429 #define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887 430 #define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888 431 #define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889 432 #define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A 433 #define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B 434 #define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C 435 #define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D 436 #define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E 437 #define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F 438 #define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890 439 #define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891 440 #define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892 441 #define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893 442 #define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894 443 #define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895 444 #define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896 445 #define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897 446 #define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898 447 #define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899 448 #define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A 449 #define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B 450 #define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C 451 #define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D 452 #define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E 453 #define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F 454 #define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0 455 #define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1 456 #define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2 457 #define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3 458 #define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4 459 #define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5 460 #define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6 461 #define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7 462 #define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8 463 #define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9 464 #define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA 465 #define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB 466 #define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC 467 #define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD 468 #define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE 469 #define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF 470 #define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900 471 #define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901 472 #define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902 473 #define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903 474 #define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904 475 #define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905 476 #define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906 477 #define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907 478 #define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908 479 #define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909 480 #define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A 481 #define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B 482 #define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C 483 #define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D 484 #define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E 485 #define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F 486 #define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910 487 #define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911 488 #define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912 489 #define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913 490 #define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914 491 #define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915 492 #define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916 493 #define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917 494 #define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918 495 #define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919 496 #define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A 497 #define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B 498 #define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C 499 #define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D 500 #define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E 501 #define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F 502 #define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940 503 #define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941 504 #define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942 505 #define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943 506 #define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944 507 #define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945 508 #define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946 509 #define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947 510 #define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948 511 #define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949 512 #define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A 513 #define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B 514 #define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C 515 #define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D 516 #define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E 517 #define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F 518 #define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950 519 #define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958 520 #define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960 521 #define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968 522 #define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970 523 #define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978 524 #define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980 525 #define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981 526 #define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982 527 #define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983 528 #define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984 529 #define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985 530 #define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986 531 #define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987 532 #define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988 533 #define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989 534 #define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A 535 #define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B 536 #define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C 537 #define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D 538 #define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E 539 #define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F 540 #define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990 541 #define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998 542 #define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0 543 #define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8 544 #define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0 545 #define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8 546 #define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0 547 #define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1 548 #define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2 549 #define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3 550 #define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4 551 #define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5 552 #define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6 553 #define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7 554 #define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8 555 #define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9 556 #define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA 557 #define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB 558 #define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC 559 #define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD 560 #define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE 561 #define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF 562 #define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0 563 #define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8 564 #define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0 565 #define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8 566 #define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0 567 #define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8 568 #define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80 569 #define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88 570 #define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90 571 #define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98 572 #define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00 573 #define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08 574 #define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10 575 #define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18 576 #define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20 577 #define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28 578 #define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 579 #define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 580 #define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 581 #define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 582 #define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50 583 #define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58 584 #define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 585 #define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 586 #define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70 587 #define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78 588 #define WM5100_GPIO_CTRL_1 0xC00 589 #define WM5100_GPIO_CTRL_2 0xC01 590 #define WM5100_GPIO_CTRL_3 0xC02 591 #define WM5100_GPIO_CTRL_4 0xC03 592 #define WM5100_GPIO_CTRL_5 0xC04 593 #define WM5100_GPIO_CTRL_6 0xC05 594 #define WM5100_MISC_PAD_CTRL_1 0xC23 595 #define WM5100_MISC_PAD_CTRL_2 0xC24 596 #define WM5100_MISC_PAD_CTRL_3 0xC25 597 #define WM5100_MISC_PAD_CTRL_4 0xC26 598 #define WM5100_MISC_PAD_CTRL_5 0xC27 599 #define WM5100_MISC_GPIO_1 0xC28 600 #define WM5100_INTERRUPT_STATUS_1 0xD00 601 #define WM5100_INTERRUPT_STATUS_2 0xD01 602 #define WM5100_INTERRUPT_STATUS_3 0xD02 603 #define WM5100_INTERRUPT_STATUS_4 0xD03 604 #define WM5100_INTERRUPT_RAW_STATUS_2 0xD04 605 #define WM5100_INTERRUPT_RAW_STATUS_3 0xD05 606 #define WM5100_INTERRUPT_RAW_STATUS_4 0xD06 607 #define WM5100_INTERRUPT_STATUS_1_MASK 0xD07 608 #define WM5100_INTERRUPT_STATUS_2_MASK 0xD08 609 #define WM5100_INTERRUPT_STATUS_3_MASK 0xD09 610 #define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A 611 #define WM5100_INTERRUPT_CONTROL 0xD1F 612 #define WM5100_IRQ_DEBOUNCE_1 0xD20 613 #define WM5100_IRQ_DEBOUNCE_2 0xD21 614 #define WM5100_FX_CTRL 0xE00 615 #define WM5100_EQ1_1 0xE10 616 #define WM5100_EQ1_2 0xE11 617 #define WM5100_EQ1_3 0xE12 618 #define WM5100_EQ1_4 0xE13 619 #define WM5100_EQ1_5 0xE14 620 #define WM5100_EQ1_6 0xE15 621 #define WM5100_EQ1_7 0xE16 622 #define WM5100_EQ1_8 0xE17 623 #define WM5100_EQ1_9 0xE18 624 #define WM5100_EQ1_10 0xE19 625 #define WM5100_EQ1_11 0xE1A 626 #define WM5100_EQ1_12 0xE1B 627 #define WM5100_EQ1_13 0xE1C 628 #define WM5100_EQ1_14 0xE1D 629 #define WM5100_EQ1_15 0xE1E 630 #define WM5100_EQ1_16 0xE1F 631 #define WM5100_EQ1_17 0xE20 632 #define WM5100_EQ1_18 0xE21 633 #define WM5100_EQ1_19 0xE22 634 #define WM5100_EQ1_20 0xE23 635 #define WM5100_EQ2_1 0xE26 636 #define WM5100_EQ2_2 0xE27 637 #define WM5100_EQ2_3 0xE28 638 #define WM5100_EQ2_4 0xE29 639 #define WM5100_EQ2_5 0xE2A 640 #define WM5100_EQ2_6 0xE2B 641 #define WM5100_EQ2_7 0xE2C 642 #define WM5100_EQ2_8 0xE2D 643 #define WM5100_EQ2_9 0xE2E 644 #define WM5100_EQ2_10 0xE2F 645 #define WM5100_EQ2_11 0xE30 646 #define WM5100_EQ2_12 0xE31 647 #define WM5100_EQ2_13 0xE32 648 #define WM5100_EQ2_14 0xE33 649 #define WM5100_EQ2_15 0xE34 650 #define WM5100_EQ2_16 0xE35 651 #define WM5100_EQ2_17 0xE36 652 #define WM5100_EQ2_18 0xE37 653 #define WM5100_EQ2_19 0xE38 654 #define WM5100_EQ2_20 0xE39 655 #define WM5100_EQ3_1 0xE3C 656 #define WM5100_EQ3_2 0xE3D 657 #define WM5100_EQ3_3 0xE3E 658 #define WM5100_EQ3_4 0xE3F 659 #define WM5100_EQ3_5 0xE40 660 #define WM5100_EQ3_6 0xE41 661 #define WM5100_EQ3_7 0xE42 662 #define WM5100_EQ3_8 0xE43 663 #define WM5100_EQ3_9 0xE44 664 #define WM5100_EQ3_10 0xE45 665 #define WM5100_EQ3_11 0xE46 666 #define WM5100_EQ3_12 0xE47 667 #define WM5100_EQ3_13 0xE48 668 #define WM5100_EQ3_14 0xE49 669 #define WM5100_EQ3_15 0xE4A 670 #define WM5100_EQ3_16 0xE4B 671 #define WM5100_EQ3_17 0xE4C 672 #define WM5100_EQ3_18 0xE4D 673 #define WM5100_EQ3_19 0xE4E 674 #define WM5100_EQ3_20 0xE4F 675 #define WM5100_EQ4_1 0xE52 676 #define WM5100_EQ4_2 0xE53 677 #define WM5100_EQ4_3 0xE54 678 #define WM5100_EQ4_4 0xE55 679 #define WM5100_EQ4_5 0xE56 680 #define WM5100_EQ4_6 0xE57 681 #define WM5100_EQ4_7 0xE58 682 #define WM5100_EQ4_8 0xE59 683 #define WM5100_EQ4_9 0xE5A 684 #define WM5100_EQ4_10 0xE5B 685 #define WM5100_EQ4_11 0xE5C 686 #define WM5100_EQ4_12 0xE5D 687 #define WM5100_EQ4_13 0xE5E 688 #define WM5100_EQ4_14 0xE5F 689 #define WM5100_EQ4_15 0xE60 690 #define WM5100_EQ4_16 0xE61 691 #define WM5100_EQ4_17 0xE62 692 #define WM5100_EQ4_18 0xE63 693 #define WM5100_EQ4_19 0xE64 694 #define WM5100_EQ4_20 0xE65 695 #define WM5100_DRC1_CTRL1 0xE80 696 #define WM5100_DRC1_CTRL2 0xE81 697 #define WM5100_DRC1_CTRL3 0xE82 698 #define WM5100_DRC1_CTRL4 0xE83 699 #define WM5100_DRC1_CTRL5 0xE84 700 #define WM5100_HPLPF1_1 0xEC0 701 #define WM5100_HPLPF1_2 0xEC1 702 #define WM5100_HPLPF2_1 0xEC4 703 #define WM5100_HPLPF2_2 0xEC5 704 #define WM5100_HPLPF3_1 0xEC8 705 #define WM5100_HPLPF3_2 0xEC9 706 #define WM5100_HPLPF4_1 0xECC 707 #define WM5100_HPLPF4_2 0xECD 708 #define WM5100_DSP1_CONTROL_1 0xF00 709 #define WM5100_DSP1_CONTROL_2 0xF02 710 #define WM5100_DSP1_CONTROL_3 0xF03 711 #define WM5100_DSP1_CONTROL_4 0xF04 712 #define WM5100_DSP1_CONTROL_5 0xF06 713 #define WM5100_DSP1_CONTROL_6 0xF07 714 #define WM5100_DSP1_CONTROL_7 0xF08 715 #define WM5100_DSP1_CONTROL_8 0xF09 716 #define WM5100_DSP1_CONTROL_9 0xF0A 717 #define WM5100_DSP1_CONTROL_10 0xF0B 718 #define WM5100_DSP1_CONTROL_11 0xF0C 719 #define WM5100_DSP1_CONTROL_12 0xF0D 720 #define WM5100_DSP1_CONTROL_13 0xF0F 721 #define WM5100_DSP1_CONTROL_14 0xF10 722 #define WM5100_DSP1_CONTROL_15 0xF11 723 #define WM5100_DSP1_CONTROL_16 0xF12 724 #define WM5100_DSP1_CONTROL_17 0xF13 725 #define WM5100_DSP1_CONTROL_18 0xF14 726 #define WM5100_DSP1_CONTROL_19 0xF16 727 #define WM5100_DSP1_CONTROL_20 0xF17 728 #define WM5100_DSP1_CONTROL_21 0xF18 729 #define WM5100_DSP1_CONTROL_22 0xF1A 730 #define WM5100_DSP1_CONTROL_23 0xF1B 731 #define WM5100_DSP1_CONTROL_24 0xF1C 732 #define WM5100_DSP1_CONTROL_25 0xF1E 733 #define WM5100_DSP1_CONTROL_26 0xF20 734 #define WM5100_DSP1_CONTROL_27 0xF21 735 #define WM5100_DSP1_CONTROL_28 0xF22 736 #define WM5100_DSP1_CONTROL_29 0xF23 737 #define WM5100_DSP1_CONTROL_30 0xF24 738 #define WM5100_DSP2_CONTROL_1 0x1000 739 #define WM5100_DSP2_CONTROL_2 0x1002 740 #define WM5100_DSP2_CONTROL_3 0x1003 741 #define WM5100_DSP2_CONTROL_4 0x1004 742 #define WM5100_DSP2_CONTROL_5 0x1006 743 #define WM5100_DSP2_CONTROL_6 0x1007 744 #define WM5100_DSP2_CONTROL_7 0x1008 745 #define WM5100_DSP2_CONTROL_8 0x1009 746 #define WM5100_DSP2_CONTROL_9 0x100A 747 #define WM5100_DSP2_CONTROL_10 0x100B 748 #define WM5100_DSP2_CONTROL_11 0x100C 749 #define WM5100_DSP2_CONTROL_12 0x100D 750 #define WM5100_DSP2_CONTROL_13 0x100F 751 #define WM5100_DSP2_CONTROL_14 0x1010 752 #define WM5100_DSP2_CONTROL_15 0x1011 753 #define WM5100_DSP2_CONTROL_16 0x1012 754 #define WM5100_DSP2_CONTROL_17 0x1013 755 #define WM5100_DSP2_CONTROL_18 0x1014 756 #define WM5100_DSP2_CONTROL_19 0x1016 757 #define WM5100_DSP2_CONTROL_20 0x1017 758 #define WM5100_DSP2_CONTROL_21 0x1018 759 #define WM5100_DSP2_CONTROL_22 0x101A 760 #define WM5100_DSP2_CONTROL_23 0x101B 761 #define WM5100_DSP2_CONTROL_24 0x101C 762 #define WM5100_DSP2_CONTROL_25 0x101E 763 #define WM5100_DSP2_CONTROL_26 0x1020 764 #define WM5100_DSP2_CONTROL_27 0x1021 765 #define WM5100_DSP2_CONTROL_28 0x1022 766 #define WM5100_DSP2_CONTROL_29 0x1023 767 #define WM5100_DSP2_CONTROL_30 0x1024 768 #define WM5100_DSP3_CONTROL_1 0x1100 769 #define WM5100_DSP3_CONTROL_2 0x1102 770 #define WM5100_DSP3_CONTROL_3 0x1103 771 #define WM5100_DSP3_CONTROL_4 0x1104 772 #define WM5100_DSP3_CONTROL_5 0x1106 773 #define WM5100_DSP3_CONTROL_6 0x1107 774 #define WM5100_DSP3_CONTROL_7 0x1108 775 #define WM5100_DSP3_CONTROL_8 0x1109 776 #define WM5100_DSP3_CONTROL_9 0x110A 777 #define WM5100_DSP3_CONTROL_10 0x110B 778 #define WM5100_DSP3_CONTROL_11 0x110C 779 #define WM5100_DSP3_CONTROL_12 0x110D 780 #define WM5100_DSP3_CONTROL_13 0x110F 781 #define WM5100_DSP3_CONTROL_14 0x1110 782 #define WM5100_DSP3_CONTROL_15 0x1111 783 #define WM5100_DSP3_CONTROL_16 0x1112 784 #define WM5100_DSP3_CONTROL_17 0x1113 785 #define WM5100_DSP3_CONTROL_18 0x1114 786 #define WM5100_DSP3_CONTROL_19 0x1116 787 #define WM5100_DSP3_CONTROL_20 0x1117 788 #define WM5100_DSP3_CONTROL_21 0x1118 789 #define WM5100_DSP3_CONTROL_22 0x111A 790 #define WM5100_DSP3_CONTROL_23 0x111B 791 #define WM5100_DSP3_CONTROL_24 0x111C 792 #define WM5100_DSP3_CONTROL_25 0x111E 793 #define WM5100_DSP3_CONTROL_26 0x1120 794 #define WM5100_DSP3_CONTROL_27 0x1121 795 #define WM5100_DSP3_CONTROL_28 0x1122 796 #define WM5100_DSP3_CONTROL_29 0x1123 797 #define WM5100_DSP3_CONTROL_30 0x1124 798 #define WM5100_DSP1_DM_0 0x4000 799 #define WM5100_DSP1_DM_1 0x4001 800 #define WM5100_DSP1_DM_2 0x4002 801 #define WM5100_DSP1_DM_3 0x4003 802 #define WM5100_DSP1_DM_508 0x41FC 803 #define WM5100_DSP1_DM_509 0x41FD 804 #define WM5100_DSP1_DM_510 0x41FE 805 #define WM5100_DSP1_DM_511 0x41FF 806 #define WM5100_DSP1_PM_0 0x4800 807 #define WM5100_DSP1_PM_1 0x4801 808 #define WM5100_DSP1_PM_2 0x4802 809 #define WM5100_DSP1_PM_3 0x4803 810 #define WM5100_DSP1_PM_4 0x4804 811 #define WM5100_DSP1_PM_5 0x4805 812 #define WM5100_DSP1_PM_1530 0x4DFA 813 #define WM5100_DSP1_PM_1531 0x4DFB 814 #define WM5100_DSP1_PM_1532 0x4DFC 815 #define WM5100_DSP1_PM_1533 0x4DFD 816 #define WM5100_DSP1_PM_1534 0x4DFE 817 #define WM5100_DSP1_PM_1535 0x4DFF 818 #define WM5100_DSP1_ZM_0 0x5000 819 #define WM5100_DSP1_ZM_1 0x5001 820 #define WM5100_DSP1_ZM_2 0x5002 821 #define WM5100_DSP1_ZM_3 0x5003 822 #define WM5100_DSP1_ZM_2044 0x57FC 823 #define WM5100_DSP1_ZM_2045 0x57FD 824 #define WM5100_DSP1_ZM_2046 0x57FE 825 #define WM5100_DSP1_ZM_2047 0x57FF 826 #define WM5100_DSP2_DM_0 0x6000 827 #define WM5100_DSP2_DM_1 0x6001 828 #define WM5100_DSP2_DM_2 0x6002 829 #define WM5100_DSP2_DM_3 0x6003 830 #define WM5100_DSP2_DM_508 0x61FC 831 #define WM5100_DSP2_DM_509 0x61FD 832 #define WM5100_DSP2_DM_510 0x61FE 833 #define WM5100_DSP2_DM_511 0x61FF 834 #define WM5100_DSP2_PM_0 0x6800 835 #define WM5100_DSP2_PM_1 0x6801 836 #define WM5100_DSP2_PM_2 0x6802 837 #define WM5100_DSP2_PM_3 0x6803 838 #define WM5100_DSP2_PM_4 0x6804 839 #define WM5100_DSP2_PM_5 0x6805 840 #define WM5100_DSP2_PM_1530 0x6DFA 841 #define WM5100_DSP2_PM_1531 0x6DFB 842 #define WM5100_DSP2_PM_1532 0x6DFC 843 #define WM5100_DSP2_PM_1533 0x6DFD 844 #define WM5100_DSP2_PM_1534 0x6DFE 845 #define WM5100_DSP2_PM_1535 0x6DFF 846 #define WM5100_DSP2_ZM_0 0x7000 847 #define WM5100_DSP2_ZM_1 0x7001 848 #define WM5100_DSP2_ZM_2 0x7002 849 #define WM5100_DSP2_ZM_3 0x7003 850 #define WM5100_DSP2_ZM_2044 0x77FC 851 #define WM5100_DSP2_ZM_2045 0x77FD 852 #define WM5100_DSP2_ZM_2046 0x77FE 853 #define WM5100_DSP2_ZM_2047 0x77FF 854 #define WM5100_DSP3_DM_0 0x8000 855 #define WM5100_DSP3_DM_1 0x8001 856 #define WM5100_DSP3_DM_2 0x8002 857 #define WM5100_DSP3_DM_3 0x8003 858 #define WM5100_DSP3_DM_508 0x81FC 859 #define WM5100_DSP3_DM_509 0x81FD 860 #define WM5100_DSP3_DM_510 0x81FE 861 #define WM5100_DSP3_DM_511 0x81FF 862 #define WM5100_DSP3_PM_0 0x8800 863 #define WM5100_DSP3_PM_1 0x8801 864 #define WM5100_DSP3_PM_2 0x8802 865 #define WM5100_DSP3_PM_3 0x8803 866 #define WM5100_DSP3_PM_4 0x8804 867 #define WM5100_DSP3_PM_5 0x8805 868 #define WM5100_DSP3_PM_1530 0x8DFA 869 #define WM5100_DSP3_PM_1531 0x8DFB 870 #define WM5100_DSP3_PM_1532 0x8DFC 871 #define WM5100_DSP3_PM_1533 0x8DFD 872 #define WM5100_DSP3_PM_1534 0x8DFE 873 #define WM5100_DSP3_PM_1535 0x8DFF 874 #define WM5100_DSP3_ZM_0 0x9000 875 #define WM5100_DSP3_ZM_1 0x9001 876 #define WM5100_DSP3_ZM_2 0x9002 877 #define WM5100_DSP3_ZM_3 0x9003 878 #define WM5100_DSP3_ZM_2044 0x97FC 879 #define WM5100_DSP3_ZM_2045 0x97FD 880 #define WM5100_DSP3_ZM_2046 0x97FE 881 #define WM5100_DSP3_ZM_2047 0x97FF 882 883 #define WM5100_REGISTER_COUNT 1435 884 #define WM5100_MAX_REGISTER 0x97FF 885 886 /* 887 * Field Definitions. 888 */ 889 890 /* 891 * R0 (0x00) - software reset 892 */ 893 #define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 894 #define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 895 #define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 896 897 /* 898 * R1 (0x01) - Device Revision 899 */ 900 #define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ 901 #define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ 902 #define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ 903 904 /* 905 * R16 (0x10) - Ctrl IF 1 906 */ 907 #define WM5100_AUTO_INC 0x0001 /* AUTO_INC */ 908 #define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 909 #define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */ 910 #define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */ 911 912 /* 913 * R32 (0x20) - Tone Generator 1 914 */ 915 #define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */ 916 #define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */ 917 #define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */ 918 #define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */ 919 #define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */ 920 #define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */ 921 #define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */ 922 #define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */ 923 #define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */ 924 #define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */ 925 #define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */ 926 #define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */ 927 #define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */ 928 #define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */ 929 930 /* 931 * R48 (0x30) - PWM Drive 1 932 */ 933 #define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */ 934 #define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */ 935 #define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */ 936 #define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */ 937 #define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */ 938 #define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */ 939 #define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */ 940 #define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */ 941 #define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */ 942 #define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */ 943 #define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */ 944 #define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */ 945 #define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */ 946 #define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */ 947 #define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */ 948 #define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */ 949 #define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */ 950 #define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */ 951 #define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */ 952 #define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */ 953 #define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */ 954 #define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */ 955 956 /* 957 * R49 (0x31) - PWM Drive 2 958 */ 959 #define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */ 960 #define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */ 961 #define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */ 962 963 /* 964 * R50 (0x32) - PWM Drive 3 965 */ 966 #define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */ 967 #define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */ 968 #define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */ 969 970 /* 971 * R256 (0x100) - Clocking 1 972 */ 973 #define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */ 974 #define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */ 975 #define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */ 976 977 /* 978 * R257 (0x101) - Clocking 3 979 */ 980 #define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 981 #define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 982 #define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 983 #define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 984 #define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 985 #define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 986 #define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 987 #define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 988 #define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 989 #define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 990 991 /* 992 * R258 (0x102) - Clocking 4 993 */ 994 #define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 995 #define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 996 #define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 997 998 /* 999 * R259 (0x103) - Clocking 5 1000 */ 1001 #define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */ 1002 #define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */ 1003 #define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */ 1004 1005 /* 1006 * R260 (0x104) - Clocking 6 1007 */ 1008 #define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */ 1009 #define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */ 1010 #define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */ 1011 1012 /* 1013 * R263 (0x107) - Clocking 7 1014 */ 1015 #define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */ 1016 #define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */ 1017 #define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */ 1018 #define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */ 1019 #define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */ 1020 #define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */ 1021 #define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */ 1022 #define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */ 1023 #define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */ 1024 #define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */ 1025 1026 /* 1027 * R264 (0x108) - Clocking 8 1028 */ 1029 #define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */ 1030 #define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */ 1031 #define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */ 1032 1033 /* 1034 * R288 (0x120) - ASRC_ENABLE 1035 */ 1036 #define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */ 1037 #define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ 1038 #define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */ 1039 #define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */ 1040 #define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */ 1041 #define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ 1042 #define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */ 1043 #define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */ 1044 #define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */ 1045 #define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ 1046 #define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */ 1047 #define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */ 1048 #define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */ 1049 #define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ 1050 #define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */ 1051 #define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */ 1052 1053 /* 1054 * R289 (0x121) - ASRC_STATUS 1055 */ 1056 #define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */ 1057 #define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */ 1058 #define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */ 1059 #define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */ 1060 #define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */ 1061 #define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */ 1062 #define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */ 1063 #define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */ 1064 #define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */ 1065 #define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */ 1066 #define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */ 1067 #define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */ 1068 #define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */ 1069 #define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */ 1070 #define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */ 1071 #define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */ 1072 1073 /* 1074 * R290 (0x122) - ASRC_RATE1 1075 */ 1076 #define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */ 1077 #define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */ 1078 #define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */ 1079 1080 /* 1081 * R321 (0x141) - ISRC 1 CTRL 1 1082 */ 1083 #define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */ 1084 #define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */ 1085 #define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */ 1086 #define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */ 1087 #define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */ 1088 #define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */ 1089 #define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */ 1090 #define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */ 1091 #define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */ 1092 #define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */ 1093 #define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */ 1094 #define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */ 1095 #define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */ 1096 1097 /* 1098 * R322 (0x142) - ISRC 1 CTRL 2 1099 */ 1100 #define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */ 1101 #define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */ 1102 #define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */ 1103 #define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */ 1104 #define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */ 1105 #define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */ 1106 #define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */ 1107 #define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */ 1108 #define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */ 1109 #define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */ 1110 #define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */ 1111 #define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */ 1112 #define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */ 1113 #define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */ 1114 #define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */ 1115 #define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */ 1116 #define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */ 1117 #define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */ 1118 #define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */ 1119 #define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */ 1120 #define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */ 1121 #define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */ 1122 #define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */ 1123 #define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */ 1124 #define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */ 1125 #define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */ 1126 #define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */ 1127 #define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */ 1128 #define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */ 1129 #define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */ 1130 #define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */ 1131 #define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */ 1132 #define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */ 1133 #define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */ 1134 #define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */ 1135 #define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */ 1136 1137 /* 1138 * R323 (0x143) - ISRC 2 CTRL1 1139 */ 1140 #define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */ 1141 #define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */ 1142 #define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */ 1143 #define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */ 1144 #define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */ 1145 #define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */ 1146 #define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */ 1147 #define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */ 1148 #define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */ 1149 #define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */ 1150 #define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */ 1151 #define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */ 1152 #define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */ 1153 1154 /* 1155 * R324 (0x144) - ISRC 2 CTRL 2 1156 */ 1157 #define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */ 1158 #define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */ 1159 #define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */ 1160 #define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */ 1161 #define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */ 1162 #define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */ 1163 #define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */ 1164 #define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */ 1165 #define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */ 1166 #define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */ 1167 #define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */ 1168 #define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */ 1169 #define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */ 1170 #define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */ 1171 #define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */ 1172 #define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */ 1173 #define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */ 1174 #define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */ 1175 #define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */ 1176 #define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */ 1177 #define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */ 1178 #define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */ 1179 #define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */ 1180 #define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */ 1181 #define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */ 1182 #define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */ 1183 #define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */ 1184 #define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */ 1185 #define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */ 1186 #define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */ 1187 #define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */ 1188 #define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */ 1189 #define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */ 1190 #define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */ 1191 #define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */ 1192 #define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */ 1193 1194 /* 1195 * R386 (0x182) - FLL1 Control 1 1196 */ 1197 #define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */ 1198 #define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1199 #define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1200 #define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1201 1202 /* 1203 * R387 (0x183) - FLL1 Control 2 1204 */ 1205 #define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 1206 #define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 1207 #define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 1208 #define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 1209 #define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 1210 #define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 1211 1212 /* 1213 * R388 (0x184) - FLL1 Control 3 1214 */ 1215 #define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */ 1216 #define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */ 1217 #define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */ 1218 1219 /* 1220 * R390 (0x186) - FLL1 Control 5 1221 */ 1222 #define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */ 1223 #define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */ 1224 #define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */ 1225 1226 /* 1227 * R391 (0x187) - FLL1 Control 6 1228 */ 1229 #define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */ 1230 #define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */ 1231 #define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */ 1232 #define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */ 1233 #define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */ 1234 #define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */ 1235 1236 /* 1237 * R392 (0x188) - FLL1 EFS 1 1238 */ 1239 #define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */ 1240 #define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */ 1241 #define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */ 1242 1243 /* 1244 * R418 (0x1A2) - FLL2 Control 1 1245 */ 1246 #define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */ 1247 #define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1248 #define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1249 #define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1250 1251 /* 1252 * R419 (0x1A3) - FLL2 Control 2 1253 */ 1254 #define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 1255 #define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 1256 #define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 1257 #define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 1258 #define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 1259 #define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 1260 1261 /* 1262 * R420 (0x1A4) - FLL2 Control 3 1263 */ 1264 #define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */ 1265 #define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */ 1266 #define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */ 1267 1268 /* 1269 * R422 (0x1A6) - FLL2 Control 5 1270 */ 1271 #define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */ 1272 #define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */ 1273 #define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */ 1274 1275 /* 1276 * R423 (0x1A7) - FLL2 Control 6 1277 */ 1278 #define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */ 1279 #define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */ 1280 #define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */ 1281 #define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */ 1282 #define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */ 1283 #define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */ 1284 1285 /* 1286 * R424 (0x1A8) - FLL2 EFS 1 1287 */ 1288 #define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */ 1289 #define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */ 1290 #define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */ 1291 1292 /* 1293 * R512 (0x200) - Mic Charge Pump 1 1294 */ 1295 #define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */ 1296 #define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */ 1297 #define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */ 1298 #define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */ 1299 #define WM5100_CP2_ENA 0x0001 /* CP2_ENA */ 1300 #define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */ 1301 #define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */ 1302 #define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */ 1303 1304 /* 1305 * R513 (0x201) - Mic Charge Pump 2 1306 */ 1307 #define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */ 1308 #define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */ 1309 #define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */ 1310 1311 /* 1312 * R514 (0x202) - HP Charge Pump 1 1313 */ 1314 #define WM5100_CP1_ENA 0x0001 /* CP1_ENA */ 1315 #define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */ 1316 #define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */ 1317 #define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */ 1318 1319 /* 1320 * R529 (0x211) - LDO1 Control 1321 */ 1322 #define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */ 1323 #define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */ 1324 #define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */ 1325 #define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */ 1326 1327 /* 1328 * R533 (0x215) - Mic Bias Ctrl 1 1329 */ 1330 #define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */ 1331 #define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ 1332 #define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ 1333 #define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1334 #define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */ 1335 #define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1336 #define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1337 #define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1338 #define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ 1339 #define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ 1340 #define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ 1341 #define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */ 1342 #define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */ 1343 #define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */ 1344 #define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */ 1345 #define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */ 1346 #define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 1347 #define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 1348 #define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 1349 1350 /* 1351 * R534 (0x216) - Mic Bias Ctrl 2 1352 */ 1353 #define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */ 1354 #define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ 1355 #define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ 1356 #define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1357 #define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */ 1358 #define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 1359 #define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 1360 #define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 1361 #define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ 1362 #define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ 1363 #define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ 1364 #define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */ 1365 #define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */ 1366 #define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */ 1367 #define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */ 1368 #define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */ 1369 #define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 1370 #define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 1371 #define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 1372 1373 /* 1374 * R535 (0x217) - Mic Bias Ctrl 3 1375 */ 1376 #define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */ 1377 #define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */ 1378 #define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */ 1379 #define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */ 1380 #define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */ 1381 #define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */ 1382 #define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */ 1383 #define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */ 1384 #define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */ 1385 #define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */ 1386 #define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */ 1387 #define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */ 1388 #define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */ 1389 #define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */ 1390 #define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */ 1391 #define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */ 1392 #define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */ 1393 #define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */ 1394 #define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */ 1395 1396 /* 1397 * R640 (0x280) - Accessory Detect Mode 1 1398 */ 1399 #define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */ 1400 #define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */ 1401 #define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */ 1402 #define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */ 1403 #define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */ 1404 #define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */ 1405 #define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */ 1406 #define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */ 1407 #define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */ 1408 #define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */ 1409 1410 /* 1411 * R648 (0x288) - Headphone Detect 1 1412 */ 1413 #define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 1414 #define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 1415 #define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 1416 #define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 1417 #define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 1418 #define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 1419 #define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ 1420 #define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ 1421 #define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ 1422 #define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 1423 #define WM5100_HP_POLL 0x0001 /* HP_POLL */ 1424 #define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */ 1425 #define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */ 1426 #define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */ 1427 1428 /* 1429 * R649 (0x289) - Headphone Detect 2 1430 */ 1431 #define WM5100_HP_DONE 0x0080 /* HP_DONE */ 1432 #define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */ 1433 #define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */ 1434 #define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */ 1435 #define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1436 #define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1437 #define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1438 1439 /* 1440 * R656 (0x290) - Mic Detect 1 1441 */ 1442 #define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1443 #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1444 #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1445 #define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */ 1446 #define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */ 1447 #define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */ 1448 #define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */ 1449 #define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */ 1450 #define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */ 1451 #define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */ 1452 #define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */ 1453 #define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */ 1454 #define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */ 1455 #define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */ 1456 1457 /* 1458 * R657 (0x291) - Mic Detect 2 1459 */ 1460 #define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */ 1461 #define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */ 1462 #define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */ 1463 1464 /* 1465 * R658 (0x292) - Mic Detect 3 1466 */ 1467 #define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */ 1468 #define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */ 1469 #define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */ 1470 #define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */ 1471 #define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */ 1472 #define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */ 1473 #define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */ 1474 #define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */ 1475 #define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */ 1476 #define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */ 1477 #define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */ 1478 1479 /* 1480 * R699 (0x2BB) - Misc Control 1481 */ 1482 #define WM5100_HPCOM_SRC 0x200 /* HPCOM_SRC */ 1483 #define WM5100_HPCOM_SRC_SHIFT 9 /* HPCOM_SRC */ 1484 1485 /* 1486 * R769 (0x301) - Input Enables 1487 */ 1488 #define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */ 1489 #define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */ 1490 #define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */ 1491 #define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */ 1492 #define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */ 1493 #define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */ 1494 #define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */ 1495 #define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */ 1496 #define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */ 1497 #define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 1498 #define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 1499 #define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 1500 #define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */ 1501 #define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 1502 #define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 1503 #define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 1504 #define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */ 1505 #define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 1506 #define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 1507 #define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 1508 #define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */ 1509 #define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 1510 #define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 1511 #define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 1512 #define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */ 1513 #define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 1514 #define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 1515 #define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 1516 #define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */ 1517 #define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 1518 #define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 1519 #define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 1520 1521 /* 1522 * R770 (0x302) - Input Enables Status 1523 */ 1524 #define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */ 1525 #define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */ 1526 #define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */ 1527 #define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */ 1528 #define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */ 1529 #define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */ 1530 #define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */ 1531 #define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */ 1532 #define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */ 1533 #define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */ 1534 #define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */ 1535 #define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */ 1536 #define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */ 1537 #define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */ 1538 #define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */ 1539 #define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */ 1540 #define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */ 1541 #define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */ 1542 #define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */ 1543 #define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */ 1544 #define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */ 1545 #define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */ 1546 #define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */ 1547 #define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */ 1548 #define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */ 1549 #define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */ 1550 #define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */ 1551 #define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */ 1552 #define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */ 1553 #define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */ 1554 #define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */ 1555 #define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */ 1556 1557 /* 1558 * R784 (0x310) - IN1L Control 1559 */ 1560 #define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */ 1561 #define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */ 1562 #define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */ 1563 #define WM5100_IN1_OSR 0x2000 /* IN1_OSR */ 1564 #define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */ 1565 #define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */ 1566 #define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */ 1567 #define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 1568 #define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 1569 #define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 1570 #define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 1571 #define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 1572 #define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 1573 #define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 1574 #define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 1575 #define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 1576 1577 /* 1578 * R785 (0x311) - IN1R Control 1579 */ 1580 #define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 1581 #define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 1582 #define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 1583 1584 /* 1585 * R786 (0x312) - IN2L Control 1586 */ 1587 #define WM5100_IN2_OSR 0x2000 /* IN2_OSR */ 1588 #define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */ 1589 #define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */ 1590 #define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */ 1591 #define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 1592 #define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 1593 #define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 1594 #define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 1595 #define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 1596 #define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 1597 #define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 1598 #define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 1599 #define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 1600 1601 /* 1602 * R787 (0x313) - IN2R Control 1603 */ 1604 #define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 1605 #define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 1606 #define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 1607 1608 /* 1609 * R788 (0x314) - IN3L Control 1610 */ 1611 #define WM5100_IN3_OSR 0x2000 /* IN3_OSR */ 1612 #define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */ 1613 #define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */ 1614 #define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */ 1615 #define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 1616 #define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 1617 #define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 1618 #define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 1619 #define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 1620 #define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 1621 #define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 1622 #define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 1623 #define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 1624 1625 /* 1626 * R789 (0x315) - IN3R Control 1627 */ 1628 #define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 1629 #define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 1630 #define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 1631 1632 /* 1633 * R790 (0x316) - IN4L Control 1634 */ 1635 #define WM5100_IN4_OSR 0x2000 /* IN4_OSR */ 1636 #define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */ 1637 #define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */ 1638 #define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */ 1639 #define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */ 1640 #define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */ 1641 #define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */ 1642 #define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */ 1643 #define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */ 1644 #define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */ 1645 #define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */ 1646 #define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */ 1647 #define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */ 1648 1649 /* 1650 * R791 (0x317) - IN4R Control 1651 */ 1652 #define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */ 1653 #define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */ 1654 #define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */ 1655 1656 /* 1657 * R792 (0x318) - RXANC_SRC 1658 */ 1659 #define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ 1660 #define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ 1661 #define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ 1662 1663 /* 1664 * R793 (0x319) - Input Volume Ramp 1665 */ 1666 #define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 1667 #define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 1668 #define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 1669 #define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 1670 #define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 1671 #define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 1672 1673 /* 1674 * R800 (0x320) - ADC Digital Volume 1L 1675 */ 1676 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1677 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1678 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1679 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1680 #define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 1681 #define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 1682 #define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 1683 #define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1684 #define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */ 1685 #define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */ 1686 #define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */ 1687 1688 /* 1689 * R801 (0x321) - ADC Digital Volume 1R 1690 */ 1691 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1692 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1693 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1694 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1695 #define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 1696 #define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 1697 #define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 1698 #define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1699 #define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */ 1700 #define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */ 1701 #define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */ 1702 1703 /* 1704 * R802 (0x322) - ADC Digital Volume 2L 1705 */ 1706 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1707 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1708 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1709 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1710 #define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 1711 #define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 1712 #define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 1713 #define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1714 #define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */ 1715 #define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */ 1716 #define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */ 1717 1718 /* 1719 * R803 (0x323) - ADC Digital Volume 2R 1720 */ 1721 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1722 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1723 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1724 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1725 #define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 1726 #define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 1727 #define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 1728 #define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1729 #define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */ 1730 #define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */ 1731 #define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */ 1732 1733 /* 1734 * R804 (0x324) - ADC Digital Volume 3L 1735 */ 1736 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1737 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1738 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1739 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1740 #define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 1741 #define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 1742 #define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 1743 #define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 1744 #define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */ 1745 #define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */ 1746 #define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */ 1747 1748 /* 1749 * R805 (0x325) - ADC Digital Volume 3R 1750 */ 1751 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1752 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1753 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1754 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1755 #define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 1756 #define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 1757 #define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 1758 #define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 1759 #define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */ 1760 #define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */ 1761 #define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */ 1762 1763 /* 1764 * R806 (0x326) - ADC Digital Volume 4L 1765 */ 1766 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1767 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1768 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1769 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1770 #define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */ 1771 #define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */ 1772 #define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */ 1773 #define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */ 1774 #define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */ 1775 #define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */ 1776 #define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */ 1777 1778 /* 1779 * R807 (0x327) - ADC Digital Volume 4R 1780 */ 1781 #define WM5100_IN_VU 0x0200 /* IN_VU */ 1782 #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1783 #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1784 #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1785 #define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */ 1786 #define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */ 1787 #define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */ 1788 #define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */ 1789 #define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */ 1790 #define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */ 1791 #define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */ 1792 1793 /* 1794 * R1025 (0x401) - Output Enables 2 1795 */ 1796 #define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */ 1797 #define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */ 1798 #define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */ 1799 #define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */ 1800 #define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */ 1801 #define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */ 1802 #define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */ 1803 #define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */ 1804 #define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */ 1805 #define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */ 1806 #define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */ 1807 #define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */ 1808 #define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */ 1809 #define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */ 1810 #define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */ 1811 #define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */ 1812 #define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */ 1813 #define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */ 1814 #define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */ 1815 #define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */ 1816 #define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */ 1817 #define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */ 1818 #define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */ 1819 #define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */ 1820 1821 /* 1822 * R1026 (0x402) - Output Status 1 1823 */ 1824 #define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */ 1825 #define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */ 1826 #define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */ 1827 #define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */ 1828 #define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */ 1829 #define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */ 1830 #define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */ 1831 #define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */ 1832 #define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */ 1833 #define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */ 1834 #define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */ 1835 #define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */ 1836 #define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */ 1837 #define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */ 1838 #define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */ 1839 #define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */ 1840 #define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */ 1841 #define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */ 1842 #define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */ 1843 #define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */ 1844 #define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */ 1845 #define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */ 1846 #define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */ 1847 #define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */ 1848 1849 /* 1850 * R1027 (0x403) - Output Status 2 1851 */ 1852 #define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */ 1853 #define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */ 1854 #define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */ 1855 #define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */ 1856 #define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */ 1857 #define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */ 1858 #define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */ 1859 #define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */ 1860 #define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */ 1861 #define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */ 1862 #define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */ 1863 #define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */ 1864 #define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */ 1865 #define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */ 1866 #define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */ 1867 #define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */ 1868 #define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */ 1869 #define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */ 1870 #define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */ 1871 #define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */ 1872 #define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */ 1873 #define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */ 1874 #define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */ 1875 #define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */ 1876 1877 /* 1878 * R1032 (0x408) - Channel Enables 1 1879 */ 1880 #define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */ 1881 #define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */ 1882 #define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */ 1883 #define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */ 1884 #define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */ 1885 #define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */ 1886 #define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */ 1887 #define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */ 1888 #define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */ 1889 #define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */ 1890 #define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */ 1891 #define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */ 1892 #define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */ 1893 #define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */ 1894 #define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */ 1895 #define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */ 1896 #define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */ 1897 #define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */ 1898 #define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */ 1899 #define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */ 1900 #define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */ 1901 #define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */ 1902 #define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */ 1903 #define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */ 1904 1905 /* 1906 * R1040 (0x410) - Out Volume 1L 1907 */ 1908 #define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */ 1909 #define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */ 1910 #define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */ 1911 #define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */ 1912 #define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 1913 #define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 1914 #define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 1915 #define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */ 1916 #define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */ 1917 #define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */ 1918 #define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */ 1919 #define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ 1920 #define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ 1921 #define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ 1922 #define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ 1923 #define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 1924 #define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 1925 #define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 1926 1927 /* 1928 * R1041 (0x411) - Out Volume 1R 1929 */ 1930 #define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ 1931 #define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ 1932 #define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ 1933 #define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ 1934 #define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 1935 #define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 1936 #define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 1937 1938 /* 1939 * R1042 (0x412) - DAC Volume Limit 1L 1940 */ 1941 #define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */ 1942 #define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */ 1943 #define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */ 1944 1945 /* 1946 * R1043 (0x413) - DAC Volume Limit 1R 1947 */ 1948 #define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */ 1949 #define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */ 1950 #define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */ 1951 1952 /* 1953 * R1044 (0x414) - Out Volume 2L 1954 */ 1955 #define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */ 1956 #define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 1957 #define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 1958 #define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 1959 #define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */ 1960 #define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */ 1961 #define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */ 1962 #define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */ 1963 #define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ 1964 #define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ 1965 #define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ 1966 #define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ 1967 #define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */ 1968 #define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */ 1969 #define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */ 1970 1971 /* 1972 * R1045 (0x415) - Out Volume 2R 1973 */ 1974 #define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ 1975 #define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ 1976 #define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ 1977 #define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ 1978 #define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */ 1979 #define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */ 1980 #define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */ 1981 1982 /* 1983 * R1046 (0x416) - DAC Volume Limit 2L 1984 */ 1985 #define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */ 1986 #define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */ 1987 #define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */ 1988 1989 /* 1990 * R1047 (0x417) - DAC Volume Limit 2R 1991 */ 1992 #define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */ 1993 #define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */ 1994 #define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */ 1995 1996 /* 1997 * R1048 (0x418) - Out Volume 3L 1998 */ 1999 #define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */ 2000 #define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */ 2001 #define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */ 2002 #define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */ 2003 #define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */ 2004 #define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */ 2005 #define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */ 2006 #define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */ 2007 #define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */ 2008 #define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */ 2009 #define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */ 2010 #define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */ 2011 #define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */ 2012 #define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */ 2013 #define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */ 2014 2015 /* 2016 * R1049 (0x419) - Out Volume 3R 2017 */ 2018 #define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */ 2019 #define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */ 2020 #define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */ 2021 #define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */ 2022 #define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */ 2023 #define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */ 2024 #define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */ 2025 2026 /* 2027 * R1050 (0x41A) - DAC Volume Limit 3L 2028 */ 2029 #define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */ 2030 #define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */ 2031 #define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */ 2032 2033 /* 2034 * R1051 (0x41B) - DAC Volume Limit 3R 2035 */ 2036 #define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */ 2037 #define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */ 2038 #define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */ 2039 2040 /* 2041 * R1052 (0x41C) - Out Volume 4L 2042 */ 2043 #define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */ 2044 #define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */ 2045 #define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */ 2046 #define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */ 2047 #define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */ 2048 #define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */ 2049 #define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */ 2050 #define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */ 2051 #define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */ 2052 #define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */ 2053 #define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */ 2054 2055 /* 2056 * R1053 (0x41D) - Out Volume 4R 2057 */ 2058 #define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */ 2059 #define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */ 2060 #define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */ 2061 #define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */ 2062 #define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */ 2063 #define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */ 2064 #define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */ 2065 2066 /* 2067 * R1054 (0x41E) - DAC Volume Limit 5L 2068 */ 2069 #define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */ 2070 #define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */ 2071 #define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */ 2072 #define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */ 2073 #define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */ 2074 #define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */ 2075 #define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */ 2076 #define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */ 2077 #define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */ 2078 #define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */ 2079 #define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */ 2080 2081 /* 2082 * R1055 (0x41F) - DAC Volume Limit 5R 2083 */ 2084 #define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */ 2085 #define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */ 2086 #define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */ 2087 #define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */ 2088 #define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */ 2089 #define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */ 2090 #define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */ 2091 2092 /* 2093 * R1056 (0x420) - DAC Volume Limit 6L 2094 */ 2095 #define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */ 2096 #define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */ 2097 #define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */ 2098 #define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */ 2099 #define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */ 2100 #define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */ 2101 #define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */ 2102 #define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */ 2103 #define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */ 2104 #define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */ 2105 #define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */ 2106 2107 /* 2108 * R1057 (0x421) - DAC Volume Limit 6R 2109 */ 2110 #define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */ 2111 #define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */ 2112 #define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */ 2113 #define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */ 2114 #define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */ 2115 #define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */ 2116 #define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */ 2117 2118 /* 2119 * R1088 (0x440) - DAC AEC Control 1 2120 */ 2121 #define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */ 2122 #define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */ 2123 #define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */ 2124 #define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */ 2125 #define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */ 2126 #define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */ 2127 #define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */ 2128 #define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */ 2129 #define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */ 2130 #define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */ 2131 #define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 2132 2133 /* 2134 * R1089 (0x441) - Output Volume Ramp 2135 */ 2136 #define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 2137 #define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 2138 #define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 2139 #define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 2140 #define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 2141 #define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 2142 2143 /* 2144 * R1152 (0x480) - DAC Digital Volume 1L 2145 */ 2146 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2147 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2148 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2149 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2150 #define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 2151 #define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 2152 #define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 2153 #define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 2154 #define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 2155 #define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 2156 #define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 2157 2158 /* 2159 * R1153 (0x481) - DAC Digital Volume 1R 2160 */ 2161 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2162 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2163 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2164 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2165 #define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 2166 #define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 2167 #define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 2168 #define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 2169 #define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 2170 #define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 2171 #define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 2172 2173 /* 2174 * R1154 (0x482) - DAC Digital Volume 2L 2175 */ 2176 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2177 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2178 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2179 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2180 #define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 2181 #define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 2182 #define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 2183 #define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 2184 #define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 2185 #define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 2186 #define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 2187 2188 /* 2189 * R1155 (0x483) - DAC Digital Volume 2R 2190 */ 2191 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2192 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2193 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2194 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2195 #define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 2196 #define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 2197 #define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 2198 #define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 2199 #define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 2200 #define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 2201 #define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 2202 2203 /* 2204 * R1156 (0x484) - DAC Digital Volume 3L 2205 */ 2206 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2207 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2208 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2209 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2210 #define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */ 2211 #define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */ 2212 #define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */ 2213 #define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */ 2214 #define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */ 2215 #define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */ 2216 #define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */ 2217 2218 /* 2219 * R1157 (0x485) - DAC Digital Volume 3R 2220 */ 2221 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2222 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2223 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2224 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2225 #define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */ 2226 #define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */ 2227 #define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */ 2228 #define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */ 2229 #define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */ 2230 #define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */ 2231 #define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */ 2232 2233 /* 2234 * R1158 (0x486) - DAC Digital Volume 4L 2235 */ 2236 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2237 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2238 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2239 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2240 #define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */ 2241 #define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */ 2242 #define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */ 2243 #define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */ 2244 #define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */ 2245 #define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */ 2246 #define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */ 2247 2248 /* 2249 * R1159 (0x487) - DAC Digital Volume 4R 2250 */ 2251 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2252 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2253 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2254 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2255 #define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */ 2256 #define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */ 2257 #define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */ 2258 #define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */ 2259 #define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */ 2260 #define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */ 2261 #define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */ 2262 2263 /* 2264 * R1160 (0x488) - DAC Digital Volume 5L 2265 */ 2266 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2267 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2268 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2269 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2270 #define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */ 2271 #define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */ 2272 #define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */ 2273 #define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */ 2274 #define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */ 2275 #define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */ 2276 #define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */ 2277 2278 /* 2279 * R1161 (0x489) - DAC Digital Volume 5R 2280 */ 2281 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2282 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2283 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2284 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2285 #define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */ 2286 #define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */ 2287 #define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */ 2288 #define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */ 2289 #define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */ 2290 #define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */ 2291 #define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */ 2292 2293 /* 2294 * R1162 (0x48A) - DAC Digital Volume 6L 2295 */ 2296 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2297 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2298 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2299 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2300 #define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */ 2301 #define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */ 2302 #define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */ 2303 #define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */ 2304 #define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */ 2305 #define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */ 2306 #define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */ 2307 2308 /* 2309 * R1163 (0x48B) - DAC Digital Volume 6R 2310 */ 2311 #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2312 #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2313 #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2314 #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2315 #define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */ 2316 #define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */ 2317 #define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */ 2318 #define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */ 2319 #define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */ 2320 #define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */ 2321 #define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */ 2322 2323 /* 2324 * R1216 (0x4C0) - PDM SPK1 CTRL 1 2325 */ 2326 #define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 2327 #define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 2328 #define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 2329 #define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 2330 #define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 2331 #define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 2332 #define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 2333 #define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 2334 #define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 2335 #define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 2336 #define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 2337 #define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 2338 #define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 2339 #define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 2340 #define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 2341 2342 /* 2343 * R1217 (0x4C1) - PDM SPK1 CTRL 2 2344 */ 2345 #define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */ 2346 #define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 2347 #define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 2348 #define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 2349 2350 /* 2351 * R1218 (0x4C2) - PDM SPK2 CTRL 1 2352 */ 2353 #define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */ 2354 #define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */ 2355 #define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */ 2356 #define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 2357 #define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */ 2358 #define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */ 2359 #define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */ 2360 #define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 2361 #define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */ 2362 #define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */ 2363 #define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */ 2364 #define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */ 2365 #define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 2366 #define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 2367 #define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 2368 2369 /* 2370 * R1219 (0x4C3) - PDM SPK2 CTRL 2 2371 */ 2372 #define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */ 2373 #define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */ 2374 #define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ 2375 #define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ 2376 2377 /* 2378 * R1280 (0x500) - Audio IF 1_1 2379 */ 2380 #define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */ 2381 #define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */ 2382 #define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */ 2383 #define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2384 #define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */ 2385 #define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */ 2386 #define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */ 2387 #define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 2388 #define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */ 2389 #define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */ 2390 #define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */ 2391 #define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 2392 #define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */ 2393 #define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */ 2394 #define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */ 2395 2396 /* 2397 * R1281 (0x501) - Audio IF 1_2 2398 */ 2399 #define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 2400 #define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 2401 #define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 2402 #define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 2403 #define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 2404 #define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 2405 #define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 2406 #define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 2407 #define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 2408 #define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 2409 #define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 2410 #define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 2411 #define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 2412 #define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 2413 #define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 2414 #define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 2415 #define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 2416 #define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 2417 #define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 2418 #define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 2419 2420 /* 2421 * R1282 (0x502) - Audio IF 1_3 2422 */ 2423 #define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 2424 #define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 2425 #define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 2426 #define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 2427 #define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 2428 #define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 2429 #define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 2430 #define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 2431 #define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 2432 #define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 2433 #define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 2434 #define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 2435 2436 /* 2437 * R1283 (0x503) - Audio IF 1_4 2438 */ 2439 #define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */ 2440 #define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 2441 #define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 2442 #define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2443 #define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */ 2444 #define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */ 2445 #define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */ 2446 2447 /* 2448 * R1284 (0x504) - Audio IF 1_5 2449 */ 2450 #define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 2451 #define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 2452 #define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 2453 2454 /* 2455 * R1285 (0x505) - Audio IF 1_6 2456 */ 2457 #define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */ 2458 #define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */ 2459 #define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */ 2460 2461 /* 2462 * R1286 (0x506) - Audio IF 1_7 2463 */ 2464 #define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */ 2465 #define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */ 2466 #define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */ 2467 2468 /* 2469 * R1287 (0x507) - Audio IF 1_8 2470 */ 2471 #define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 2472 #define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 2473 #define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 2474 #define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 2475 #define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 2476 #define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 2477 2478 /* 2479 * R1288 (0x508) - Audio IF 1_9 2480 */ 2481 #define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 2482 #define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 2483 #define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 2484 #define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 2485 #define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 2486 #define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 2487 2488 /* 2489 * R1289 (0x509) - Audio IF 1_10 2490 */ 2491 #define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 2492 #define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 2493 #define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 2494 2495 /* 2496 * R1290 (0x50A) - Audio IF 1_11 2497 */ 2498 #define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 2499 #define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 2500 #define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 2501 2502 /* 2503 * R1291 (0x50B) - Audio IF 1_12 2504 */ 2505 #define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 2506 #define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 2507 #define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 2508 2509 /* 2510 * R1292 (0x50C) - Audio IF 1_13 2511 */ 2512 #define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 2513 #define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 2514 #define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 2515 2516 /* 2517 * R1293 (0x50D) - Audio IF 1_14 2518 */ 2519 #define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 2520 #define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 2521 #define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 2522 2523 /* 2524 * R1294 (0x50E) - Audio IF 1_15 2525 */ 2526 #define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 2527 #define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 2528 #define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 2529 2530 /* 2531 * R1295 (0x50F) - Audio IF 1_16 2532 */ 2533 #define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */ 2534 #define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */ 2535 #define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */ 2536 2537 /* 2538 * R1296 (0x510) - Audio IF 1_17 2539 */ 2540 #define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */ 2541 #define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */ 2542 #define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */ 2543 2544 /* 2545 * R1297 (0x511) - Audio IF 1_18 2546 */ 2547 #define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 2548 #define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 2549 #define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 2550 2551 /* 2552 * R1298 (0x512) - Audio IF 1_19 2553 */ 2554 #define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 2555 #define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 2556 #define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 2557 2558 /* 2559 * R1299 (0x513) - Audio IF 1_20 2560 */ 2561 #define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 2562 #define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 2563 #define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 2564 2565 /* 2566 * R1300 (0x514) - Audio IF 1_21 2567 */ 2568 #define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 2569 #define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 2570 #define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 2571 2572 /* 2573 * R1301 (0x515) - Audio IF 1_22 2574 */ 2575 #define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 2576 #define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 2577 #define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 2578 2579 /* 2580 * R1302 (0x516) - Audio IF 1_23 2581 */ 2582 #define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 2583 #define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 2584 #define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 2585 2586 /* 2587 * R1303 (0x517) - Audio IF 1_24 2588 */ 2589 #define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */ 2590 #define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */ 2591 #define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */ 2592 2593 /* 2594 * R1304 (0x518) - Audio IF 1_25 2595 */ 2596 #define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */ 2597 #define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */ 2598 #define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */ 2599 2600 /* 2601 * R1305 (0x519) - Audio IF 1_26 2602 */ 2603 #define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */ 2604 #define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */ 2605 #define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */ 2606 #define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */ 2607 #define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */ 2608 #define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */ 2609 #define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */ 2610 #define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */ 2611 #define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 2612 #define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 2613 #define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 2614 #define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 2615 #define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 2616 #define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 2617 #define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 2618 #define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 2619 #define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 2620 #define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 2621 #define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 2622 #define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 2623 #define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 2624 #define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 2625 #define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 2626 #define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 2627 #define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 2628 #define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 2629 #define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 2630 #define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 2631 #define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 2632 #define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 2633 #define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 2634 #define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 2635 2636 /* 2637 * R1306 (0x51A) - Audio IF 1_27 2638 */ 2639 #define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */ 2640 #define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */ 2641 #define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */ 2642 #define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */ 2643 #define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */ 2644 #define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */ 2645 #define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */ 2646 #define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */ 2647 #define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */ 2648 #define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */ 2649 #define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */ 2650 #define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 2651 #define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */ 2652 #define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */ 2653 #define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */ 2654 #define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 2655 #define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */ 2656 #define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */ 2657 #define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */ 2658 #define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 2659 #define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */ 2660 #define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */ 2661 #define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */ 2662 #define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 2663 #define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */ 2664 #define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */ 2665 #define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */ 2666 #define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 2667 #define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */ 2668 #define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */ 2669 #define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */ 2670 #define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 2671 2672 /* 2673 * R1344 (0x540) - Audio IF 2_1 2674 */ 2675 #define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */ 2676 #define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */ 2677 #define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */ 2678 #define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2679 #define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */ 2680 #define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */ 2681 #define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */ 2682 #define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 2683 #define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */ 2684 #define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */ 2685 #define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */ 2686 #define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 2687 #define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */ 2688 #define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */ 2689 #define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */ 2690 2691 /* 2692 * R1345 (0x541) - Audio IF 2_2 2693 */ 2694 #define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */ 2695 #define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */ 2696 #define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */ 2697 #define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 2698 #define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */ 2699 #define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */ 2700 #define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */ 2701 #define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */ 2702 #define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 2703 #define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 2704 #define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 2705 #define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 2706 #define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 2707 #define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 2708 #define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 2709 #define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 2710 #define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 2711 #define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 2712 #define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 2713 #define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 2714 2715 /* 2716 * R1346 (0x542) - Audio IF 2_3 2717 */ 2718 #define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 2719 #define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 2720 #define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 2721 #define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 2722 #define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 2723 #define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 2724 #define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 2725 #define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 2726 #define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 2727 #define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 2728 #define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 2729 #define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 2730 2731 /* 2732 * R1347 (0x543) - Audio IF 2_4 2733 */ 2734 #define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */ 2735 #define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */ 2736 #define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */ 2737 #define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2738 #define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */ 2739 #define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */ 2740 #define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */ 2741 2742 /* 2743 * R1348 (0x544) - Audio IF 2_5 2744 */ 2745 #define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */ 2746 #define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */ 2747 #define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */ 2748 2749 /* 2750 * R1349 (0x545) - Audio IF 2_6 2751 */ 2752 #define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */ 2753 #define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */ 2754 #define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */ 2755 2756 /* 2757 * R1350 (0x546) - Audio IF 2_7 2758 */ 2759 #define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */ 2760 #define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */ 2761 #define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */ 2762 2763 /* 2764 * R1351 (0x547) - Audio IF 2_8 2765 */ 2766 #define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */ 2767 #define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */ 2768 #define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */ 2769 #define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 2770 #define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 2771 #define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 2772 2773 /* 2774 * R1352 (0x548) - Audio IF 2_9 2775 */ 2776 #define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */ 2777 #define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */ 2778 #define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */ 2779 #define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 2780 #define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 2781 #define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 2782 2783 /* 2784 * R1353 (0x549) - Audio IF 2_10 2785 */ 2786 #define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */ 2787 #define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */ 2788 #define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */ 2789 2790 /* 2791 * R1354 (0x54A) - Audio IF 2_11 2792 */ 2793 #define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */ 2794 #define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */ 2795 #define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ 2796 2797 /* 2798 * R1361 (0x551) - Audio IF 2_18 2799 */ 2800 #define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ 2801 #define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */ 2802 #define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */ 2803 2804 /* 2805 * R1362 (0x552) - Audio IF 2_19 2806 */ 2807 #define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */ 2808 #define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */ 2809 #define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ 2810 2811 /* 2812 * R1369 (0x559) - Audio IF 2_26 2813 */ 2814 #define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ 2815 #define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ 2816 #define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ 2817 #define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */ 2818 #define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */ 2819 #define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */ 2820 #define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */ 2821 #define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */ 2822 2823 /* 2824 * R1370 (0x55A) - Audio IF 2_27 2825 */ 2826 #define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ 2827 #define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ 2828 #define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ 2829 #define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */ 2830 #define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */ 2831 #define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */ 2832 #define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */ 2833 #define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */ 2834 2835 /* 2836 * R1408 (0x580) - Audio IF 3_1 2837 */ 2838 #define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */ 2839 #define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */ 2840 #define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */ 2841 #define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */ 2842 #define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */ 2843 #define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */ 2844 #define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */ 2845 #define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */ 2846 #define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */ 2847 #define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */ 2848 #define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */ 2849 #define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */ 2850 #define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */ 2851 #define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */ 2852 #define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */ 2853 2854 /* 2855 * R1409 (0x581) - Audio IF 3_2 2856 */ 2857 #define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */ 2858 #define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */ 2859 #define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */ 2860 #define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */ 2861 #define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */ 2862 #define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */ 2863 #define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */ 2864 #define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */ 2865 #define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */ 2866 #define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */ 2867 #define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */ 2868 #define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */ 2869 #define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */ 2870 #define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */ 2871 #define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */ 2872 #define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */ 2873 #define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */ 2874 #define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */ 2875 #define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */ 2876 #define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */ 2877 2878 /* 2879 * R1410 (0x582) - Audio IF 3_3 2880 */ 2881 #define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */ 2882 #define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */ 2883 #define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */ 2884 #define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */ 2885 #define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */ 2886 #define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */ 2887 #define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */ 2888 #define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */ 2889 #define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */ 2890 #define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */ 2891 #define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */ 2892 #define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */ 2893 2894 /* 2895 * R1411 (0x583) - Audio IF 3_4 2896 */ 2897 #define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */ 2898 #define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */ 2899 #define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */ 2900 #define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 2901 #define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */ 2902 #define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */ 2903 #define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */ 2904 2905 /* 2906 * R1412 (0x584) - Audio IF 3_5 2907 */ 2908 #define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */ 2909 #define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */ 2910 #define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */ 2911 2912 /* 2913 * R1413 (0x585) - Audio IF 3_6 2914 */ 2915 #define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */ 2916 #define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */ 2917 #define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */ 2918 2919 /* 2920 * R1414 (0x586) - Audio IF 3_7 2921 */ 2922 #define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */ 2923 #define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */ 2924 #define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */ 2925 2926 /* 2927 * R1415 (0x587) - Audio IF 3_8 2928 */ 2929 #define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */ 2930 #define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */ 2931 #define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */ 2932 #define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */ 2933 #define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */ 2934 #define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */ 2935 2936 /* 2937 * R1416 (0x588) - Audio IF 3_9 2938 */ 2939 #define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */ 2940 #define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */ 2941 #define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */ 2942 #define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */ 2943 #define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */ 2944 #define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */ 2945 2946 /* 2947 * R1417 (0x589) - Audio IF 3_10 2948 */ 2949 #define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */ 2950 #define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */ 2951 #define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */ 2952 2953 /* 2954 * R1418 (0x58A) - Audio IF 3_11 2955 */ 2956 #define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */ 2957 #define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */ 2958 #define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */ 2959 2960 /* 2961 * R1425 (0x591) - Audio IF 3_18 2962 */ 2963 #define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */ 2964 #define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */ 2965 #define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */ 2966 2967 /* 2968 * R1426 (0x592) - Audio IF 3_19 2969 */ 2970 #define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */ 2971 #define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */ 2972 #define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */ 2973 2974 /* 2975 * R1433 (0x599) - Audio IF 3_26 2976 */ 2977 #define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */ 2978 #define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */ 2979 #define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */ 2980 #define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */ 2981 #define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */ 2982 #define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */ 2983 #define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */ 2984 #define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */ 2985 2986 /* 2987 * R1434 (0x59A) - Audio IF 3_27 2988 */ 2989 #define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */ 2990 #define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */ 2991 #define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */ 2992 #define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */ 2993 #define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */ 2994 #define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */ 2995 #define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */ 2996 #define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */ 2997 2998 #define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */ 2999 #define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */ 3000 #define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */ 3001 3002 /* 3003 * R3072 (0xC00) - GPIO CTRL 1 3004 */ 3005 #define WM5100_GP1_DIR 0x8000 /* GP1_DIR */ 3006 #define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 3007 #define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */ 3008 #define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */ 3009 #define WM5100_GP1_PU 0x4000 /* GP1_PU */ 3010 #define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */ 3011 #define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */ 3012 #define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */ 3013 #define WM5100_GP1_PD 0x2000 /* GP1_PD */ 3014 #define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */ 3015 #define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */ 3016 #define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */ 3017 #define WM5100_GP1_POL 0x0400 /* GP1_POL */ 3018 #define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */ 3019 #define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */ 3020 #define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */ 3021 #define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 3022 #define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 3023 #define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 3024 #define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 3025 #define WM5100_GP1_DB 0x0100 /* GP1_DB */ 3026 #define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */ 3027 #define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */ 3028 #define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */ 3029 #define WM5100_GP1_LVL 0x0040 /* GP1_LVL */ 3030 #define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 3031 #define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */ 3032 #define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */ 3033 #define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ 3034 #define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ 3035 #define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ 3036 3037 /* 3038 * R3073 (0xC01) - GPIO CTRL 2 3039 */ 3040 #define WM5100_GP2_DIR 0x8000 /* GP2_DIR */ 3041 #define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 3042 #define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */ 3043 #define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */ 3044 #define WM5100_GP2_PU 0x4000 /* GP2_PU */ 3045 #define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */ 3046 #define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */ 3047 #define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */ 3048 #define WM5100_GP2_PD 0x2000 /* GP2_PD */ 3049 #define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */ 3050 #define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */ 3051 #define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */ 3052 #define WM5100_GP2_POL 0x0400 /* GP2_POL */ 3053 #define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */ 3054 #define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */ 3055 #define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */ 3056 #define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 3057 #define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 3058 #define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 3059 #define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 3060 #define WM5100_GP2_DB 0x0100 /* GP2_DB */ 3061 #define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */ 3062 #define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */ 3063 #define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */ 3064 #define WM5100_GP2_LVL 0x0040 /* GP2_LVL */ 3065 #define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3066 #define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3067 #define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3068 #define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ 3069 #define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ 3070 #define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ 3071 3072 /* 3073 * R3074 (0xC02) - GPIO CTRL 3 3074 */ 3075 #define WM5100_GP3_DIR 0x8000 /* GP3_DIR */ 3076 #define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 3077 #define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */ 3078 #define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */ 3079 #define WM5100_GP3_PU 0x4000 /* GP3_PU */ 3080 #define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */ 3081 #define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */ 3082 #define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */ 3083 #define WM5100_GP3_PD 0x2000 /* GP3_PD */ 3084 #define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */ 3085 #define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */ 3086 #define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */ 3087 #define WM5100_GP3_POL 0x0400 /* GP3_POL */ 3088 #define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */ 3089 #define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */ 3090 #define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */ 3091 #define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3092 #define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3093 #define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3094 #define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3095 #define WM5100_GP3_DB 0x0100 /* GP3_DB */ 3096 #define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */ 3097 #define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */ 3098 #define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */ 3099 #define WM5100_GP3_LVL 0x0040 /* GP3_LVL */ 3100 #define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3101 #define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3102 #define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3103 #define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ 3104 #define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ 3105 #define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ 3106 3107 /* 3108 * R3075 (0xC03) - GPIO CTRL 4 3109 */ 3110 #define WM5100_GP4_DIR 0x8000 /* GP4_DIR */ 3111 #define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3112 #define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3113 #define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3114 #define WM5100_GP4_PU 0x4000 /* GP4_PU */ 3115 #define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */ 3116 #define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */ 3117 #define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */ 3118 #define WM5100_GP4_PD 0x2000 /* GP4_PD */ 3119 #define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */ 3120 #define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */ 3121 #define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */ 3122 #define WM5100_GP4_POL 0x0400 /* GP4_POL */ 3123 #define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */ 3124 #define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */ 3125 #define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */ 3126 #define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3127 #define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3128 #define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3129 #define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3130 #define WM5100_GP4_DB 0x0100 /* GP4_DB */ 3131 #define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */ 3132 #define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */ 3133 #define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */ 3134 #define WM5100_GP4_LVL 0x0040 /* GP4_LVL */ 3135 #define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3136 #define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3137 #define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3138 #define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ 3139 #define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ 3140 #define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ 3141 3142 /* 3143 * R3076 (0xC04) - GPIO CTRL 5 3144 */ 3145 #define WM5100_GP5_DIR 0x8000 /* GP5_DIR */ 3146 #define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3147 #define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3148 #define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3149 #define WM5100_GP5_PU 0x4000 /* GP5_PU */ 3150 #define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */ 3151 #define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */ 3152 #define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */ 3153 #define WM5100_GP5_PD 0x2000 /* GP5_PD */ 3154 #define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */ 3155 #define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */ 3156 #define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */ 3157 #define WM5100_GP5_POL 0x0400 /* GP5_POL */ 3158 #define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */ 3159 #define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */ 3160 #define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */ 3161 #define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3162 #define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3163 #define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3164 #define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3165 #define WM5100_GP5_DB 0x0100 /* GP5_DB */ 3166 #define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */ 3167 #define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */ 3168 #define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */ 3169 #define WM5100_GP5_LVL 0x0040 /* GP5_LVL */ 3170 #define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3171 #define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3172 #define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3173 #define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */ 3174 #define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */ 3175 #define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */ 3176 3177 /* 3178 * R3077 (0xC05) - GPIO CTRL 6 3179 */ 3180 #define WM5100_GP6_DIR 0x8000 /* GP6_DIR */ 3181 #define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3182 #define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3183 #define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3184 #define WM5100_GP6_PU 0x4000 /* GP6_PU */ 3185 #define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */ 3186 #define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */ 3187 #define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */ 3188 #define WM5100_GP6_PD 0x2000 /* GP6_PD */ 3189 #define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */ 3190 #define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */ 3191 #define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */ 3192 #define WM5100_GP6_POL 0x0400 /* GP6_POL */ 3193 #define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */ 3194 #define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */ 3195 #define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */ 3196 #define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3197 #define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3198 #define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3199 #define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3200 #define WM5100_GP6_DB 0x0100 /* GP6_DB */ 3201 #define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */ 3202 #define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */ 3203 #define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */ 3204 #define WM5100_GP6_LVL 0x0040 /* GP6_LVL */ 3205 #define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3206 #define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3207 #define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3208 #define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */ 3209 #define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */ 3210 #define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */ 3211 3212 /* 3213 * R3107 (0xC23) - Misc Pad Ctrl 1 3214 */ 3215 #define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 3216 #define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 3217 #define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 3218 #define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3219 #define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */ 3220 #define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 3221 #define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 3222 #define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3223 #define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */ 3224 #define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 3225 #define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 3226 #define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3227 #define WM5100_RESET_PU 0x0002 /* RESET_PU */ 3228 #define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */ 3229 #define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */ 3230 #define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */ 3231 #define WM5100_ADDR_PD 0x0001 /* ADDR_PD */ 3232 #define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 3233 #define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */ 3234 #define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */ 3235 3236 /* 3237 * R3108 (0xC24) - Misc Pad Ctrl 2 3238 */ 3239 #define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */ 3240 #define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */ 3241 #define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */ 3242 #define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */ 3243 #define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */ 3244 #define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */ 3245 #define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */ 3246 #define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 3247 #define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */ 3248 #define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */ 3249 #define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */ 3250 #define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3251 #define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */ 3252 #define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */ 3253 #define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */ 3254 #define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3255 3256 /* 3257 * R3109 (0xC25) - Misc Pad Ctrl 3 3258 */ 3259 #define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */ 3260 #define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */ 3261 #define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */ 3262 #define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */ 3263 #define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */ 3264 #define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */ 3265 #define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */ 3266 #define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */ 3267 #define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */ 3268 #define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */ 3269 #define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */ 3270 #define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */ 3271 #define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */ 3272 #define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */ 3273 #define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */ 3274 #define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */ 3275 #define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */ 3276 #define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */ 3277 #define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */ 3278 #define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */ 3279 #define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */ 3280 #define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */ 3281 #define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */ 3282 #define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */ 3283 3284 /* 3285 * R3110 (0xC26) - Misc Pad Ctrl 4 3286 */ 3287 #define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */ 3288 #define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */ 3289 #define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */ 3290 #define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */ 3291 #define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */ 3292 #define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */ 3293 #define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */ 3294 #define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */ 3295 #define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */ 3296 #define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */ 3297 #define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */ 3298 #define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */ 3299 #define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */ 3300 #define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */ 3301 #define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */ 3302 #define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */ 3303 #define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */ 3304 #define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */ 3305 #define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */ 3306 #define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */ 3307 #define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */ 3308 #define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */ 3309 #define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */ 3310 #define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */ 3311 3312 /* 3313 * R3111 (0xC27) - Misc Pad Ctrl 5 3314 */ 3315 #define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */ 3316 #define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */ 3317 #define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */ 3318 #define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */ 3319 #define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */ 3320 #define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */ 3321 #define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */ 3322 #define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */ 3323 #define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */ 3324 #define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */ 3325 #define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */ 3326 #define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */ 3327 #define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */ 3328 #define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */ 3329 #define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */ 3330 #define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */ 3331 #define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */ 3332 #define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */ 3333 #define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */ 3334 #define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */ 3335 #define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */ 3336 #define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */ 3337 #define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */ 3338 #define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */ 3339 3340 /* 3341 * R3112 (0xC28) - Misc GPIO 1 3342 */ 3343 #define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */ 3344 #define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */ 3345 #define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */ 3346 3347 /* 3348 * R3328 (0xD00) - Interrupt Status 1 3349 */ 3350 #define WM5100_GP6_EINT 0x0020 /* GP6_EINT */ 3351 #define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3352 #define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3353 #define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3354 #define WM5100_GP5_EINT 0x0010 /* GP5_EINT */ 3355 #define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3356 #define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3357 #define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3358 #define WM5100_GP4_EINT 0x0008 /* GP4_EINT */ 3359 #define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3360 #define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3361 #define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3362 #define WM5100_GP3_EINT 0x0004 /* GP3_EINT */ 3363 #define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3364 #define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3365 #define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3366 #define WM5100_GP2_EINT 0x0002 /* GP2_EINT */ 3367 #define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3368 #define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3369 #define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3370 #define WM5100_GP1_EINT 0x0001 /* GP1_EINT */ 3371 #define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3372 #define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3373 #define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3374 3375 /* 3376 * R3329 (0xD01) - Interrupt Status 2 3377 */ 3378 #define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */ 3379 #define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */ 3380 #define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */ 3381 #define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */ 3382 #define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */ 3383 #define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */ 3384 #define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */ 3385 #define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */ 3386 #define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */ 3387 #define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */ 3388 #define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */ 3389 #define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */ 3390 #define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */ 3391 #define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */ 3392 #define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */ 3393 #define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ 3394 #define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */ 3395 #define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */ 3396 #define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */ 3397 #define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ 3398 #define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */ 3399 #define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */ 3400 #define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */ 3401 #define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ 3402 3403 /* 3404 * R3330 (0xD02) - Interrupt Status 3 3405 */ 3406 #define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3407 #define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3408 #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */ 3409 #define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */ 3410 #define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */ 3411 #define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */ 3412 #define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */ 3413 #define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */ 3414 #define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */ 3415 #define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */ 3416 #define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */ 3417 #define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */ 3418 #define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */ 3419 #define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */ 3420 #define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */ 3421 #define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */ 3422 #define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */ 3423 #define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */ 3424 #define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */ 3425 #define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */ 3426 #define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */ 3427 #define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */ 3428 #define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */ 3429 #define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */ 3430 #define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */ 3431 #define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */ 3432 #define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */ 3433 #define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */ 3434 #define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 3435 #define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 3436 #define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 3437 #define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 3438 #define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 3439 #define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 3440 #define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 3441 #define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 3442 #define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */ 3443 #define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */ 3444 #define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */ 3445 #define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */ 3446 #define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3447 #define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3448 #define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */ 3449 #define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */ 3450 3451 /* 3452 * R3331 (0xD03) - Interrupt Status 4 3453 */ 3454 #define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */ 3455 #define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */ 3456 #define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */ 3457 #define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */ 3458 #define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */ 3459 #define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */ 3460 #define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */ 3461 #define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */ 3462 #define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */ 3463 #define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */ 3464 #define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */ 3465 #define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */ 3466 #define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */ 3467 #define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */ 3468 #define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */ 3469 #define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */ 3470 #define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3471 #define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3472 #define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */ 3473 #define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */ 3474 #define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3475 #define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3476 #define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */ 3477 #define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */ 3478 #define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */ 3479 #define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */ 3480 #define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */ 3481 #define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */ 3482 #define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3483 #define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3484 #define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */ 3485 #define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */ 3486 #define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3487 #define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3488 #define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */ 3489 #define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */ 3490 #define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3491 #define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3492 #define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */ 3493 #define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */ 3494 #define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3495 #define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3496 #define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */ 3497 #define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */ 3498 #define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3499 #define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3500 #define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */ 3501 #define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */ 3502 #define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3503 #define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3504 #define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */ 3505 #define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */ 3506 #define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3507 #define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3508 #define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */ 3509 #define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */ 3510 3511 /* 3512 * R3332 (0xD04) - Interrupt Raw Status 2 3513 */ 3514 #define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */ 3515 #define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */ 3516 #define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */ 3517 #define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */ 3518 #define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */ 3519 #define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */ 3520 #define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */ 3521 #define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */ 3522 #define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */ 3523 #define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */ 3524 #define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */ 3525 #define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */ 3526 #define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */ 3527 #define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */ 3528 #define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */ 3529 #define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */ 3530 #define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */ 3531 #define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */ 3532 #define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */ 3533 #define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */ 3534 #define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */ 3535 #define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */ 3536 #define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */ 3537 #define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */ 3538 3539 /* 3540 * R3333 (0xD05) - Interrupt Raw Status 3 3541 */ 3542 #define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3543 #define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3544 #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */ 3545 #define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */ 3546 #define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ 3547 #define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ 3548 #define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ 3549 #define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ 3550 #define WM5100_HPDET_STS 0x2000 /* HPDET_STS */ 3551 #define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */ 3552 #define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */ 3553 #define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */ 3554 #define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */ 3555 #define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */ 3556 #define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */ 3557 #define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */ 3558 #define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */ 3559 #define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */ 3560 #define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */ 3561 #define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */ 3562 #define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */ 3563 #define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */ 3564 #define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */ 3565 #define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */ 3566 #define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 3567 #define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 3568 #define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 3569 #define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 3570 #define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 3571 #define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 3572 #define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 3573 #define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 3574 #define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */ 3575 #define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */ 3576 #define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */ 3577 #define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */ 3578 #define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3579 #define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3580 #define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */ 3581 #define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */ 3582 3583 /* 3584 * R3334 (0xD06) - Interrupt Raw Status 4 3585 */ 3586 #define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */ 3587 #define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */ 3588 #define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */ 3589 #define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */ 3590 #define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */ 3591 #define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */ 3592 #define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */ 3593 #define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */ 3594 #define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */ 3595 #define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */ 3596 #define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */ 3597 #define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */ 3598 #define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */ 3599 #define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */ 3600 #define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */ 3601 #define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */ 3602 #define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3603 #define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3604 #define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */ 3605 #define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */ 3606 #define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3607 #define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3608 #define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */ 3609 #define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */ 3610 #define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */ 3611 #define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */ 3612 #define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */ 3613 #define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */ 3614 #define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3615 #define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3616 #define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */ 3617 #define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */ 3618 #define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3619 #define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3620 #define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */ 3621 #define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */ 3622 #define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3623 #define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3624 #define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */ 3625 #define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */ 3626 #define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3627 #define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3628 #define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */ 3629 #define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */ 3630 #define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */ 3631 #define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */ 3632 #define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */ 3633 #define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */ 3634 #define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */ 3635 #define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */ 3636 #define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */ 3637 #define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */ 3638 #define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3639 #define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3640 #define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */ 3641 #define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */ 3642 3643 /* 3644 * R3335 (0xD07) - Interrupt Status 1 Mask 3645 */ 3646 #define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 3647 #define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 3648 #define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 3649 #define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 3650 #define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3651 #define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3652 #define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3653 #define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3654 #define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 3655 #define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 3656 #define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 3657 #define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 3658 #define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 3659 #define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 3660 #define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 3661 #define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 3662 #define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 3663 #define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 3664 #define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 3665 #define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 3666 #define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 3667 #define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 3668 #define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 3669 #define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 3670 3671 /* 3672 * R3336 (0xD08) - Interrupt Status 2 Mask 3673 */ 3674 #define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */ 3675 #define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */ 3676 #define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */ 3677 #define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */ 3678 #define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */ 3679 #define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */ 3680 #define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */ 3681 #define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */ 3682 #define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */ 3683 #define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */ 3684 #define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */ 3685 #define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */ 3686 #define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */ 3687 #define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */ 3688 #define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */ 3689 #define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ 3690 #define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */ 3691 #define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */ 3692 #define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */ 3693 #define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ 3694 #define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */ 3695 #define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */ 3696 #define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */ 3697 #define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ 3698 3699 /* 3700 * R3337 (0xD09) - Interrupt Status 3 Mask 3701 */ 3702 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3703 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3704 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3705 #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3706 #define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3707 #define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3708 #define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */ 3709 #define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */ 3710 #define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */ 3711 #define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */ 3712 #define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */ 3713 #define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */ 3714 #define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */ 3715 #define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */ 3716 #define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */ 3717 #define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */ 3718 #define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */ 3719 #define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */ 3720 #define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */ 3721 #define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */ 3722 #define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */ 3723 #define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */ 3724 #define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */ 3725 #define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */ 3726 #define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */ 3727 #define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */ 3728 #define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */ 3729 #define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */ 3730 #define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 3731 #define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 3732 #define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 3733 #define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 3734 #define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 3735 #define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 3736 #define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 3737 #define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 3738 #define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */ 3739 #define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */ 3740 #define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */ 3741 #define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */ 3742 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3743 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3744 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3745 #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3746 3747 /* 3748 * R3338 (0xD0A) - Interrupt Status 4 Mask 3749 */ 3750 #define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */ 3751 #define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */ 3752 #define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */ 3753 #define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */ 3754 #define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */ 3755 #define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */ 3756 #define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */ 3757 #define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */ 3758 #define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */ 3759 #define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */ 3760 #define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */ 3761 #define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */ 3762 #define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */ 3763 #define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */ 3764 #define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */ 3765 #define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */ 3766 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3767 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3768 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3769 #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3770 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3771 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3772 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3773 #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3774 #define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3775 #define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3776 #define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */ 3777 #define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */ 3778 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3779 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3780 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */ 3781 #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */ 3782 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3783 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3784 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */ 3785 #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */ 3786 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3787 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3788 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */ 3789 #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */ 3790 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3791 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3792 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */ 3793 #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */ 3794 #define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3795 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3796 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */ 3797 #define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */ 3798 #define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3799 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3800 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3801 #define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3802 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3803 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3804 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */ 3805 #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */ 3806 3807 /* 3808 * R3359 (0xD1F) - Interrupt Control 3809 */ 3810 #define WM5100_IM_IRQ 0x0001 /* IM_IRQ */ 3811 #define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 3812 #define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */ 3813 #define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */ 3814 3815 /* 3816 * R3360 (0xD20) - IRQ Debounce 1 3817 */ 3818 #define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3819 #define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3820 #define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */ 3821 #define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */ 3822 #define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */ 3823 #define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */ 3824 #define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */ 3825 #define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */ 3826 #define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */ 3827 #define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */ 3828 #define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */ 3829 #define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */ 3830 #define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */ 3831 #define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */ 3832 #define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */ 3833 #define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */ 3834 #define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3835 #define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3836 #define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */ 3837 #define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */ 3838 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3839 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3840 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3841 #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3842 3843 /* 3844 * R3361 (0xD21) - IRQ Debounce 2 3845 */ 3846 #define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */ 3847 #define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */ 3848 #define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */ 3849 #define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */ 3850 3851 /* 3852 * R3584 (0xE00) - FX_Ctrl 3853 */ 3854 #define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */ 3855 #define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */ 3856 #define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */ 3857 #define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */ 3858 #define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */ 3859 #define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */ 3860 3861 /* 3862 * R3600 (0xE10) - EQ1_1 3863 */ 3864 #define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */ 3865 #define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */ 3866 #define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */ 3867 #define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */ 3868 #define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */ 3869 #define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */ 3870 #define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */ 3871 #define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */ 3872 #define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */ 3873 #define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */ 3874 #define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */ 3875 #define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */ 3876 #define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */ 3877 3878 /* 3879 * R3601 (0xE11) - EQ1_2 3880 */ 3881 #define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */ 3882 #define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */ 3883 #define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */ 3884 #define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */ 3885 #define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */ 3886 #define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */ 3887 3888 /* 3889 * R3602 (0xE12) - EQ1_3 3890 */ 3891 #define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */ 3892 #define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */ 3893 #define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */ 3894 3895 /* 3896 * R3603 (0xE13) - EQ1_4 3897 */ 3898 #define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */ 3899 #define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */ 3900 #define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */ 3901 3902 /* 3903 * R3604 (0xE14) - EQ1_5 3904 */ 3905 #define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */ 3906 #define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */ 3907 #define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */ 3908 3909 /* 3910 * R3605 (0xE15) - EQ1_6 3911 */ 3912 #define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */ 3913 #define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */ 3914 #define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */ 3915 3916 /* 3917 * R3606 (0xE16) - EQ1_7 3918 */ 3919 #define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */ 3920 #define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */ 3921 #define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */ 3922 3923 /* 3924 * R3607 (0xE17) - EQ1_8 3925 */ 3926 #define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */ 3927 #define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */ 3928 #define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */ 3929 3930 /* 3931 * R3608 (0xE18) - EQ1_9 3932 */ 3933 #define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */ 3934 #define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */ 3935 #define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */ 3936 3937 /* 3938 * R3609 (0xE19) - EQ1_10 3939 */ 3940 #define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */ 3941 #define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */ 3942 #define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */ 3943 3944 /* 3945 * R3610 (0xE1A) - EQ1_11 3946 */ 3947 #define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */ 3948 #define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */ 3949 #define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */ 3950 3951 /* 3952 * R3611 (0xE1B) - EQ1_12 3953 */ 3954 #define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */ 3955 #define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */ 3956 #define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */ 3957 3958 /* 3959 * R3612 (0xE1C) - EQ1_13 3960 */ 3961 #define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */ 3962 #define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */ 3963 #define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */ 3964 3965 /* 3966 * R3613 (0xE1D) - EQ1_14 3967 */ 3968 #define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */ 3969 #define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */ 3970 #define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */ 3971 3972 /* 3973 * R3614 (0xE1E) - EQ1_15 3974 */ 3975 #define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */ 3976 #define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */ 3977 #define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */ 3978 3979 /* 3980 * R3615 (0xE1F) - EQ1_16 3981 */ 3982 #define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */ 3983 #define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */ 3984 #define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */ 3985 3986 /* 3987 * R3616 (0xE20) - EQ1_17 3988 */ 3989 #define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */ 3990 #define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */ 3991 #define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */ 3992 3993 /* 3994 * R3617 (0xE21) - EQ1_18 3995 */ 3996 #define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */ 3997 #define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */ 3998 #define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */ 3999 4000 /* 4001 * R3618 (0xE22) - EQ1_19 4002 */ 4003 #define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */ 4004 #define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */ 4005 #define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */ 4006 4007 /* 4008 * R3619 (0xE23) - EQ1_20 4009 */ 4010 #define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */ 4011 #define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */ 4012 #define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */ 4013 4014 /* 4015 * R3622 (0xE26) - EQ2_1 4016 */ 4017 #define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */ 4018 #define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */ 4019 #define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */ 4020 #define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */ 4021 #define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */ 4022 #define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */ 4023 #define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */ 4024 #define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */ 4025 #define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */ 4026 #define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */ 4027 #define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */ 4028 #define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */ 4029 #define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */ 4030 4031 /* 4032 * R3623 (0xE27) - EQ2_2 4033 */ 4034 #define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */ 4035 #define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */ 4036 #define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */ 4037 #define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */ 4038 #define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */ 4039 #define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */ 4040 4041 /* 4042 * R3624 (0xE28) - EQ2_3 4043 */ 4044 #define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */ 4045 #define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */ 4046 #define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */ 4047 4048 /* 4049 * R3625 (0xE29) - EQ2_4 4050 */ 4051 #define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */ 4052 #define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */ 4053 #define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */ 4054 4055 /* 4056 * R3626 (0xE2A) - EQ2_5 4057 */ 4058 #define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */ 4059 #define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */ 4060 #define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */ 4061 4062 /* 4063 * R3627 (0xE2B) - EQ2_6 4064 */ 4065 #define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */ 4066 #define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */ 4067 #define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */ 4068 4069 /* 4070 * R3628 (0xE2C) - EQ2_7 4071 */ 4072 #define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */ 4073 #define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */ 4074 #define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */ 4075 4076 /* 4077 * R3629 (0xE2D) - EQ2_8 4078 */ 4079 #define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */ 4080 #define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */ 4081 #define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */ 4082 4083 /* 4084 * R3630 (0xE2E) - EQ2_9 4085 */ 4086 #define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */ 4087 #define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */ 4088 #define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */ 4089 4090 /* 4091 * R3631 (0xE2F) - EQ2_10 4092 */ 4093 #define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */ 4094 #define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */ 4095 #define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */ 4096 4097 /* 4098 * R3632 (0xE30) - EQ2_11 4099 */ 4100 #define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */ 4101 #define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */ 4102 #define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */ 4103 4104 /* 4105 * R3633 (0xE31) - EQ2_12 4106 */ 4107 #define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */ 4108 #define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */ 4109 #define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */ 4110 4111 /* 4112 * R3634 (0xE32) - EQ2_13 4113 */ 4114 #define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */ 4115 #define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */ 4116 #define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */ 4117 4118 /* 4119 * R3635 (0xE33) - EQ2_14 4120 */ 4121 #define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */ 4122 #define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */ 4123 #define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */ 4124 4125 /* 4126 * R3636 (0xE34) - EQ2_15 4127 */ 4128 #define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */ 4129 #define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */ 4130 #define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */ 4131 4132 /* 4133 * R3637 (0xE35) - EQ2_16 4134 */ 4135 #define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */ 4136 #define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */ 4137 #define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */ 4138 4139 /* 4140 * R3638 (0xE36) - EQ2_17 4141 */ 4142 #define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */ 4143 #define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */ 4144 #define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */ 4145 4146 /* 4147 * R3639 (0xE37) - EQ2_18 4148 */ 4149 #define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */ 4150 #define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */ 4151 #define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */ 4152 4153 /* 4154 * R3640 (0xE38) - EQ2_19 4155 */ 4156 #define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */ 4157 #define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */ 4158 #define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */ 4159 4160 /* 4161 * R3641 (0xE39) - EQ2_20 4162 */ 4163 #define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */ 4164 #define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */ 4165 #define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */ 4166 4167 /* 4168 * R3644 (0xE3C) - EQ3_1 4169 */ 4170 #define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */ 4171 #define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */ 4172 #define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */ 4173 #define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */ 4174 #define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */ 4175 #define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */ 4176 #define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */ 4177 #define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */ 4178 #define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */ 4179 #define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */ 4180 #define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */ 4181 #define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */ 4182 #define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */ 4183 4184 /* 4185 * R3645 (0xE3D) - EQ3_2 4186 */ 4187 #define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */ 4188 #define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */ 4189 #define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */ 4190 #define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */ 4191 #define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */ 4192 #define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */ 4193 4194 /* 4195 * R3646 (0xE3E) - EQ3_3 4196 */ 4197 #define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */ 4198 #define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */ 4199 #define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */ 4200 4201 /* 4202 * R3647 (0xE3F) - EQ3_4 4203 */ 4204 #define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */ 4205 #define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */ 4206 #define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */ 4207 4208 /* 4209 * R3648 (0xE40) - EQ3_5 4210 */ 4211 #define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */ 4212 #define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */ 4213 #define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */ 4214 4215 /* 4216 * R3649 (0xE41) - EQ3_6 4217 */ 4218 #define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */ 4219 #define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */ 4220 #define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */ 4221 4222 /* 4223 * R3650 (0xE42) - EQ3_7 4224 */ 4225 #define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */ 4226 #define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */ 4227 #define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */ 4228 4229 /* 4230 * R3651 (0xE43) - EQ3_8 4231 */ 4232 #define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */ 4233 #define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */ 4234 #define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */ 4235 4236 /* 4237 * R3652 (0xE44) - EQ3_9 4238 */ 4239 #define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */ 4240 #define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */ 4241 #define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */ 4242 4243 /* 4244 * R3653 (0xE45) - EQ3_10 4245 */ 4246 #define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */ 4247 #define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */ 4248 #define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */ 4249 4250 /* 4251 * R3654 (0xE46) - EQ3_11 4252 */ 4253 #define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */ 4254 #define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */ 4255 #define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */ 4256 4257 /* 4258 * R3655 (0xE47) - EQ3_12 4259 */ 4260 #define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */ 4261 #define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */ 4262 #define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */ 4263 4264 /* 4265 * R3656 (0xE48) - EQ3_13 4266 */ 4267 #define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */ 4268 #define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */ 4269 #define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */ 4270 4271 /* 4272 * R3657 (0xE49) - EQ3_14 4273 */ 4274 #define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */ 4275 #define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */ 4276 #define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */ 4277 4278 /* 4279 * R3658 (0xE4A) - EQ3_15 4280 */ 4281 #define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */ 4282 #define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */ 4283 #define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */ 4284 4285 /* 4286 * R3659 (0xE4B) - EQ3_16 4287 */ 4288 #define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */ 4289 #define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */ 4290 #define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */ 4291 4292 /* 4293 * R3660 (0xE4C) - EQ3_17 4294 */ 4295 #define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */ 4296 #define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */ 4297 #define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */ 4298 4299 /* 4300 * R3661 (0xE4D) - EQ3_18 4301 */ 4302 #define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */ 4303 #define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */ 4304 #define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */ 4305 4306 /* 4307 * R3662 (0xE4E) - EQ3_19 4308 */ 4309 #define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */ 4310 #define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */ 4311 #define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */ 4312 4313 /* 4314 * R3663 (0xE4F) - EQ3_20 4315 */ 4316 #define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */ 4317 #define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */ 4318 #define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */ 4319 4320 /* 4321 * R3666 (0xE52) - EQ4_1 4322 */ 4323 #define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */ 4324 #define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */ 4325 #define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */ 4326 #define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */ 4327 #define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */ 4328 #define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */ 4329 #define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */ 4330 #define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */ 4331 #define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */ 4332 #define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */ 4333 #define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */ 4334 #define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */ 4335 #define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */ 4336 4337 /* 4338 * R3667 (0xE53) - EQ4_2 4339 */ 4340 #define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */ 4341 #define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */ 4342 #define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */ 4343 #define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */ 4344 #define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */ 4345 #define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */ 4346 4347 /* 4348 * R3668 (0xE54) - EQ4_3 4349 */ 4350 #define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */ 4351 #define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */ 4352 #define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */ 4353 4354 /* 4355 * R3669 (0xE55) - EQ4_4 4356 */ 4357 #define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */ 4358 #define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */ 4359 #define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */ 4360 4361 /* 4362 * R3670 (0xE56) - EQ4_5 4363 */ 4364 #define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */ 4365 #define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */ 4366 #define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */ 4367 4368 /* 4369 * R3671 (0xE57) - EQ4_6 4370 */ 4371 #define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */ 4372 #define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */ 4373 #define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */ 4374 4375 /* 4376 * R3672 (0xE58) - EQ4_7 4377 */ 4378 #define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */ 4379 #define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */ 4380 #define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */ 4381 4382 /* 4383 * R3673 (0xE59) - EQ4_8 4384 */ 4385 #define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */ 4386 #define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */ 4387 #define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */ 4388 4389 /* 4390 * R3674 (0xE5A) - EQ4_9 4391 */ 4392 #define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */ 4393 #define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */ 4394 #define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */ 4395 4396 /* 4397 * R3675 (0xE5B) - EQ4_10 4398 */ 4399 #define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */ 4400 #define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */ 4401 #define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */ 4402 4403 /* 4404 * R3676 (0xE5C) - EQ4_11 4405 */ 4406 #define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */ 4407 #define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */ 4408 #define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */ 4409 4410 /* 4411 * R3677 (0xE5D) - EQ4_12 4412 */ 4413 #define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */ 4414 #define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */ 4415 #define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */ 4416 4417 /* 4418 * R3678 (0xE5E) - EQ4_13 4419 */ 4420 #define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */ 4421 #define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */ 4422 #define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */ 4423 4424 /* 4425 * R3679 (0xE5F) - EQ4_14 4426 */ 4427 #define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */ 4428 #define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */ 4429 #define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */ 4430 4431 /* 4432 * R3680 (0xE60) - EQ4_15 4433 */ 4434 #define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */ 4435 #define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */ 4436 #define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */ 4437 4438 /* 4439 * R3681 (0xE61) - EQ4_16 4440 */ 4441 #define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */ 4442 #define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */ 4443 #define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */ 4444 4445 /* 4446 * R3682 (0xE62) - EQ4_17 4447 */ 4448 #define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */ 4449 #define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */ 4450 #define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */ 4451 4452 /* 4453 * R3683 (0xE63) - EQ4_18 4454 */ 4455 #define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */ 4456 #define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */ 4457 #define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */ 4458 4459 /* 4460 * R3684 (0xE64) - EQ4_19 4461 */ 4462 #define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */ 4463 #define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */ 4464 #define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */ 4465 4466 /* 4467 * R3685 (0xE65) - EQ4_20 4468 */ 4469 #define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */ 4470 #define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */ 4471 #define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */ 4472 4473 /* 4474 * R3712 (0xE80) - DRC1 ctrl1 4475 */ 4476 #define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */ 4477 #define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */ 4478 #define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */ 4479 #define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */ 4480 #define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */ 4481 #define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */ 4482 #define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */ 4483 #define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */ 4484 #define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */ 4485 #define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */ 4486 #define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */ 4487 #define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */ 4488 #define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */ 4489 #define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */ 4490 #define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */ 4491 #define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */ 4492 #define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */ 4493 #define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */ 4494 #define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */ 4495 #define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */ 4496 #define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */ 4497 #define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */ 4498 #define WM5100_DRC_QR 0x0010 /* DRC_QR */ 4499 #define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */ 4500 #define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */ 4501 #define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */ 4502 #define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */ 4503 #define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */ 4504 #define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */ 4505 #define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 4506 #define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */ 4507 #define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */ 4508 #define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */ 4509 #define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */ 4510 #define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */ 4511 #define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */ 4512 #define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */ 4513 #define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */ 4514 4515 /* 4516 * R3713 (0xE81) - DRC1 ctrl2 4517 */ 4518 #define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */ 4519 #define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */ 4520 #define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */ 4521 #define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */ 4522 #define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */ 4523 #define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */ 4524 #define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */ 4525 #define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */ 4526 #define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */ 4527 #define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 4528 #define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 4529 #define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 4530 4531 /* 4532 * R3714 (0xE82) - DRC1 ctrl3 4533 */ 4534 #define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */ 4535 #define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */ 4536 #define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */ 4537 #define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */ 4538 #define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */ 4539 #define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */ 4540 #define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */ 4541 #define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */ 4542 #define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */ 4543 #define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */ 4544 #define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */ 4545 #define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */ 4546 #define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 4547 #define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 4548 #define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 4549 #define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 4550 #define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 4551 #define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 4552 4553 /* 4554 * R3715 (0xE83) - DRC1 ctrl4 4555 */ 4556 #define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 4557 #define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 4558 #define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 4559 #define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 4560 #define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 4561 #define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 4562 4563 /* 4564 * R3716 (0xE84) - DRC1 ctrl5 4565 */ 4566 #define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */ 4567 #define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */ 4568 #define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */ 4569 #define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */ 4570 #define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */ 4571 #define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */ 4572 4573 /* 4574 * R3776 (0xEC0) - HPLPF1_1 4575 */ 4576 #define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 4577 #define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 4578 #define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 4579 #define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 4580 #define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 4581 #define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 4582 #define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 4583 #define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 4584 4585 /* 4586 * R3777 (0xEC1) - HPLPF1_2 4587 */ 4588 #define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 4589 #define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 4590 #define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 4591 4592 /* 4593 * R3780 (0xEC4) - HPLPF2_1 4594 */ 4595 #define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 4596 #define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 4597 #define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 4598 #define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 4599 #define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 4600 #define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 4601 #define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 4602 #define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 4603 4604 /* 4605 * R3781 (0xEC5) - HPLPF2_2 4606 */ 4607 #define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 4608 #define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 4609 #define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 4610 4611 /* 4612 * R3784 (0xEC8) - HPLPF3_1 4613 */ 4614 #define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */ 4615 #define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */ 4616 #define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */ 4617 #define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */ 4618 #define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */ 4619 #define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */ 4620 #define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */ 4621 #define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */ 4622 4623 /* 4624 * R3785 (0xEC9) - HPLPF3_2 4625 */ 4626 #define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */ 4627 #define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */ 4628 #define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */ 4629 4630 /* 4631 * R3788 (0xECC) - HPLPF4_1 4632 */ 4633 #define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */ 4634 #define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */ 4635 #define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */ 4636 #define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */ 4637 #define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */ 4638 #define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */ 4639 #define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */ 4640 #define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */ 4641 4642 /* 4643 * R3789 (0xECD) - HPLPF4_2 4644 */ 4645 #define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */ 4646 #define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */ 4647 #define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ 4648 4649 /* 4650 * R4132 (0x1024) - DSP2 Control 30 4651 */ 4652 #define WM5100_DSP2_RATE_MASK 0xC000 /* DSP2_RATE - [15:14] */ 4653 #define WM5100_DSP2_RATE_SHIFT 14 /* DSP2_RATE - [15:14] */ 4654 #define WM5100_DSP2_RATE_WIDTH 2 /* DSP2_RATE - [15:14] */ 4655 #define WM5100_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */ 4656 #define WM5100_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */ 4657 #define WM5100_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */ 4658 #define WM5100_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */ 4659 #define WM5100_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */ 4660 #define WM5100_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */ 4661 #define WM5100_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */ 4662 #define WM5100_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */ 4663 #define WM5100_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */ 4664 #define WM5100_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */ 4665 #define WM5100_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */ 4666 #define WM5100_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */ 4667 #define WM5100_DSP2_START 0x0001 /* DSP2_START */ 4668 #define WM5100_DSP2_START_MASK 0x0001 /* DSP2_START */ 4669 #define WM5100_DSP2_START_SHIFT 0 /* DSP2_START */ 4670 #define WM5100_DSP2_START_WIDTH 1 /* DSP2_START */ 4671 4672 /* 4673 * R3876 (0xF24) - DSP1 Control 30 4674 */ 4675 #define WM5100_DSP1_RATE_MASK 0xC000 /* DSP1_RATE - [15:14] */ 4676 #define WM5100_DSP1_RATE_SHIFT 14 /* DSP1_RATE - [15:14] */ 4677 #define WM5100_DSP1_RATE_WIDTH 2 /* DSP1_RATE - [15:14] */ 4678 #define WM5100_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 4679 #define WM5100_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 4680 #define WM5100_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 4681 #define WM5100_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 4682 #define WM5100_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 4683 #define WM5100_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 4684 #define WM5100_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 4685 #define WM5100_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 4686 #define WM5100_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 4687 #define WM5100_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 4688 #define WM5100_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 4689 #define WM5100_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 4690 #define WM5100_DSP1_START 0x0001 /* DSP1_START */ 4691 #define WM5100_DSP1_START_MASK 0x0001 /* DSP1_START */ 4692 #define WM5100_DSP1_START_SHIFT 0 /* DSP1_START */ 4693 #define WM5100_DSP1_START_WIDTH 1 /* DSP1_START */ 4694 4695 /* 4696 * R4388 (0x1124) - DSP3 Control 30 4697 */ 4698 #define WM5100_DSP3_RATE_MASK 0xC000 /* DSP3_RATE - [15:14] */ 4699 #define WM5100_DSP3_RATE_SHIFT 14 /* DSP3_RATE - [15:14] */ 4700 #define WM5100_DSP3_RATE_WIDTH 2 /* DSP3_RATE - [15:14] */ 4701 #define WM5100_DSP3_DBG_CLK_ENA 0x0008 /* DSP3_DBG_CLK_ENA */ 4702 #define WM5100_DSP3_DBG_CLK_ENA_MASK 0x0008 /* DSP3_DBG_CLK_ENA */ 4703 #define WM5100_DSP3_DBG_CLK_ENA_SHIFT 3 /* DSP3_DBG_CLK_ENA */ 4704 #define WM5100_DSP3_DBG_CLK_ENA_WIDTH 1 /* DSP3_DBG_CLK_ENA */ 4705 #define WM5100_DSP3_SYS_ENA 0x0004 /* DSP3_SYS_ENA */ 4706 #define WM5100_DSP3_SYS_ENA_MASK 0x0004 /* DSP3_SYS_ENA */ 4707 #define WM5100_DSP3_SYS_ENA_SHIFT 2 /* DSP3_SYS_ENA */ 4708 #define WM5100_DSP3_SYS_ENA_WIDTH 1 /* DSP3_SYS_ENA */ 4709 #define WM5100_DSP3_CORE_ENA 0x0002 /* DSP3_CORE_ENA */ 4710 #define WM5100_DSP3_CORE_ENA_MASK 0x0002 /* DSP3_CORE_ENA */ 4711 #define WM5100_DSP3_CORE_ENA_SHIFT 1 /* DSP3_CORE_ENA */ 4712 #define WM5100_DSP3_CORE_ENA_WIDTH 1 /* DSP3_CORE_ENA */ 4713 #define WM5100_DSP3_START 0x0001 /* DSP3_START */ 4714 #define WM5100_DSP3_START_MASK 0x0001 /* DSP3_START */ 4715 #define WM5100_DSP3_START_SHIFT 0 /* DSP3_START */ 4716 #define WM5100_DSP3_START_WIDTH 1 /* DSP3_START */ 4717 4718 /* 4719 * R16384 (0x4000) - DSP1 DM 0 4720 */ 4721 #define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */ 4722 #define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */ 4723 #define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */ 4724 4725 /* 4726 * R16385 (0x4001) - DSP1 DM 1 4727 */ 4728 #define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */ 4729 #define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */ 4730 #define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */ 4731 4732 /* 4733 * R16386 (0x4002) - DSP1 DM 2 4734 */ 4735 #define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */ 4736 #define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */ 4737 #define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */ 4738 4739 /* 4740 * R16387 (0x4003) - DSP1 DM 3 4741 */ 4742 #define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */ 4743 #define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */ 4744 #define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */ 4745 4746 /* 4747 * R16892 (0x41FC) - DSP1 DM 508 4748 */ 4749 #define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */ 4750 #define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */ 4751 #define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */ 4752 4753 /* 4754 * R16893 (0x41FD) - DSP1 DM 509 4755 */ 4756 #define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */ 4757 #define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */ 4758 #define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */ 4759 4760 /* 4761 * R16894 (0x41FE) - DSP1 DM 510 4762 */ 4763 #define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */ 4764 #define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */ 4765 #define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */ 4766 4767 /* 4768 * R16895 (0x41FF) - DSP1 DM 511 4769 */ 4770 #define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */ 4771 #define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */ 4772 #define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */ 4773 4774 /* 4775 * R18432 (0x4800) - DSP1 PM 0 4776 */ 4777 #define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */ 4778 #define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */ 4779 #define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */ 4780 4781 /* 4782 * R18433 (0x4801) - DSP1 PM 1 4783 */ 4784 #define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4785 #define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4786 #define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4787 4788 /* 4789 * R18434 (0x4802) - DSP1 PM 2 4790 */ 4791 #define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4792 #define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4793 #define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4794 4795 /* 4796 * R18435 (0x4803) - DSP1 PM 3 4797 */ 4798 #define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */ 4799 #define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */ 4800 #define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */ 4801 4802 /* 4803 * R18436 (0x4804) - DSP1 PM 4 4804 */ 4805 #define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4806 #define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4807 #define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4808 4809 /* 4810 * R18437 (0x4805) - DSP1 PM 5 4811 */ 4812 #define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4813 #define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4814 #define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4815 4816 /* 4817 * R19962 (0x4DFA) - DSP1 PM 1530 4818 */ 4819 #define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */ 4820 #define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */ 4821 #define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */ 4822 4823 /* 4824 * R19963 (0x4DFB) - DSP1 PM 1531 4825 */ 4826 #define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4827 #define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4828 #define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4829 4830 /* 4831 * R19964 (0x4DFC) - DSP1 PM 1532 4832 */ 4833 #define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4834 #define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4835 #define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4836 4837 /* 4838 * R19965 (0x4DFD) - DSP1 PM 1533 4839 */ 4840 #define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */ 4841 #define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */ 4842 #define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */ 4843 4844 /* 4845 * R19966 (0x4DFE) - DSP1 PM 1534 4846 */ 4847 #define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4848 #define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4849 #define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4850 4851 /* 4852 * R19967 (0x4DFF) - DSP1 PM 1535 4853 */ 4854 #define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4855 #define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4856 #define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4857 4858 /* 4859 * R20480 (0x5000) - DSP1 ZM 0 4860 */ 4861 #define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */ 4862 #define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */ 4863 #define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */ 4864 4865 /* 4866 * R20481 (0x5001) - DSP1 ZM 1 4867 */ 4868 #define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */ 4869 #define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */ 4870 #define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */ 4871 4872 /* 4873 * R20482 (0x5002) - DSP1 ZM 2 4874 */ 4875 #define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */ 4876 #define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */ 4877 #define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */ 4878 4879 /* 4880 * R20483 (0x5003) - DSP1 ZM 3 4881 */ 4882 #define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */ 4883 #define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */ 4884 #define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */ 4885 4886 /* 4887 * R22524 (0x57FC) - DSP1 ZM 2044 4888 */ 4889 #define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */ 4890 #define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */ 4891 #define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */ 4892 4893 /* 4894 * R22525 (0x57FD) - DSP1 ZM 2045 4895 */ 4896 #define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */ 4897 #define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */ 4898 #define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */ 4899 4900 /* 4901 * R22526 (0x57FE) - DSP1 ZM 2046 4902 */ 4903 #define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */ 4904 #define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */ 4905 #define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */ 4906 4907 /* 4908 * R22527 (0x57FF) - DSP1 ZM 2047 4909 */ 4910 #define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */ 4911 #define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */ 4912 #define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */ 4913 4914 /* 4915 * R24576 (0x6000) - DSP2 DM 0 4916 */ 4917 #define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */ 4918 #define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */ 4919 #define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */ 4920 4921 /* 4922 * R24577 (0x6001) - DSP2 DM 1 4923 */ 4924 #define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */ 4925 #define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */ 4926 #define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */ 4927 4928 /* 4929 * R24578 (0x6002) - DSP2 DM 2 4930 */ 4931 #define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */ 4932 #define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */ 4933 #define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */ 4934 4935 /* 4936 * R24579 (0x6003) - DSP2 DM 3 4937 */ 4938 #define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */ 4939 #define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */ 4940 #define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */ 4941 4942 /* 4943 * R25084 (0x61FC) - DSP2 DM 508 4944 */ 4945 #define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */ 4946 #define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */ 4947 #define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */ 4948 4949 /* 4950 * R25085 (0x61FD) - DSP2 DM 509 4951 */ 4952 #define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */ 4953 #define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */ 4954 #define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */ 4955 4956 /* 4957 * R25086 (0x61FE) - DSP2 DM 510 4958 */ 4959 #define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */ 4960 #define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */ 4961 #define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */ 4962 4963 /* 4964 * R25087 (0x61FF) - DSP2 DM 511 4965 */ 4966 #define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */ 4967 #define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */ 4968 #define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */ 4969 4970 /* 4971 * R26624 (0x6800) - DSP2 PM 0 4972 */ 4973 #define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */ 4974 #define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */ 4975 #define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */ 4976 4977 /* 4978 * R26625 (0x6801) - DSP2 PM 1 4979 */ 4980 #define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4981 #define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4982 #define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4983 4984 /* 4985 * R26626 (0x6802) - DSP2 PM 2 4986 */ 4987 #define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4988 #define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4989 #define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4990 4991 /* 4992 * R26627 (0x6803) - DSP2 PM 3 4993 */ 4994 #define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */ 4995 #define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */ 4996 #define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */ 4997 4998 /* 4999 * R26628 (0x6804) - DSP2 PM 4 5000 */ 5001 #define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 5002 #define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 5003 #define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 5004 5005 /* 5006 * R26629 (0x6805) - DSP2 PM 5 5007 */ 5008 #define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 5009 #define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 5010 #define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 5011 5012 /* 5013 * R28154 (0x6DFA) - DSP2 PM 1530 5014 */ 5015 #define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */ 5016 #define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */ 5017 #define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */ 5018 5019 /* 5020 * R28155 (0x6DFB) - DSP2 PM 1531 5021 */ 5022 #define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 5023 #define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 5024 #define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 5025 5026 /* 5027 * R28156 (0x6DFC) - DSP2 PM 1532 5028 */ 5029 #define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 5030 #define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 5031 #define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 5032 5033 /* 5034 * R28157 (0x6DFD) - DSP2 PM 1533 5035 */ 5036 #define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */ 5037 #define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */ 5038 #define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */ 5039 5040 /* 5041 * R28158 (0x6DFE) - DSP2 PM 1534 5042 */ 5043 #define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 5044 #define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */ 5045 #define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */ 5046 5047 /* 5048 * R28159 (0x6DFF) - DSP2 PM 1535 5049 */ 5050 #define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 5051 #define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */ 5052 #define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */ 5053 5054 /* 5055 * R28672 (0x7000) - DSP2 ZM 0 5056 */ 5057 #define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */ 5058 #define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */ 5059 #define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */ 5060 5061 /* 5062 * R28673 (0x7001) - DSP2 ZM 1 5063 */ 5064 #define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */ 5065 #define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */ 5066 #define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */ 5067 5068 /* 5069 * R28674 (0x7002) - DSP2 ZM 2 5070 */ 5071 #define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */ 5072 #define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */ 5073 #define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */ 5074 5075 /* 5076 * R28675 (0x7003) - DSP2 ZM 3 5077 */ 5078 #define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */ 5079 #define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */ 5080 #define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */ 5081 5082 /* 5083 * R30716 (0x77FC) - DSP2 ZM 2044 5084 */ 5085 #define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */ 5086 #define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */ 5087 #define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */ 5088 5089 /* 5090 * R30717 (0x77FD) - DSP2 ZM 2045 5091 */ 5092 #define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */ 5093 #define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */ 5094 #define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */ 5095 5096 /* 5097 * R30718 (0x77FE) - DSP2 ZM 2046 5098 */ 5099 #define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */ 5100 #define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */ 5101 #define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */ 5102 5103 /* 5104 * R30719 (0x77FF) - DSP2 ZM 2047 5105 */ 5106 #define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */ 5107 #define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */ 5108 #define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */ 5109 5110 /* 5111 * R32768 (0x8000) - DSP3 DM 0 5112 */ 5113 #define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */ 5114 #define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */ 5115 #define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */ 5116 5117 /* 5118 * R32769 (0x8001) - DSP3 DM 1 5119 */ 5120 #define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */ 5121 #define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */ 5122 #define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */ 5123 5124 /* 5125 * R32770 (0x8002) - DSP3 DM 2 5126 */ 5127 #define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */ 5128 #define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */ 5129 #define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */ 5130 5131 /* 5132 * R32771 (0x8003) - DSP3 DM 3 5133 */ 5134 #define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */ 5135 #define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */ 5136 #define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */ 5137 5138 /* 5139 * R33276 (0x81FC) - DSP3 DM 508 5140 */ 5141 #define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */ 5142 #define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */ 5143 #define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */ 5144 5145 /* 5146 * R33277 (0x81FD) - DSP3 DM 509 5147 */ 5148 #define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */ 5149 #define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */ 5150 #define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */ 5151 5152 /* 5153 * R33278 (0x81FE) - DSP3 DM 510 5154 */ 5155 #define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */ 5156 #define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */ 5157 #define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */ 5158 5159 /* 5160 * R33279 (0x81FF) - DSP3 DM 511 5161 */ 5162 #define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */ 5163 #define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */ 5164 #define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */ 5165 5166 /* 5167 * R34816 (0x8800) - DSP3 PM 0 5168 */ 5169 #define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */ 5170 #define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */ 5171 #define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */ 5172 5173 /* 5174 * R34817 (0x8801) - DSP3 PM 1 5175 */ 5176 #define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5177 #define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5178 #define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5179 5180 /* 5181 * R34818 (0x8802) - DSP3 PM 2 5182 */ 5183 #define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5184 #define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5185 #define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5186 5187 /* 5188 * R34819 (0x8803) - DSP3 PM 3 5189 */ 5190 #define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */ 5191 #define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */ 5192 #define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */ 5193 5194 /* 5195 * R34820 (0x8804) - DSP3 PM 4 5196 */ 5197 #define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5198 #define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5199 #define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5200 5201 /* 5202 * R34821 (0x8805) - DSP3 PM 5 5203 */ 5204 #define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5205 #define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5206 #define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5207 5208 /* 5209 * R36346 (0x8DFA) - DSP3 PM 1530 5210 */ 5211 #define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */ 5212 #define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */ 5213 #define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */ 5214 5215 /* 5216 * R36347 (0x8DFB) - DSP3 PM 1531 5217 */ 5218 #define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5219 #define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5220 #define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5221 5222 /* 5223 * R36348 (0x8DFC) - DSP3 PM 1532 5224 */ 5225 #define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5226 #define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5227 #define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5228 5229 /* 5230 * R36349 (0x8DFD) - DSP3 PM 1533 5231 */ 5232 #define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */ 5233 #define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */ 5234 #define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */ 5235 5236 /* 5237 * R36350 (0x8DFE) - DSP3 PM 1534 5238 */ 5239 #define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5240 #define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5241 #define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5242 5243 /* 5244 * R36351 (0x8DFF) - DSP3 PM 1535 5245 */ 5246 #define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5247 #define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5248 #define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5249 5250 /* 5251 * R36864 (0x9000) - DSP3 ZM 0 5252 */ 5253 #define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */ 5254 #define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */ 5255 #define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */ 5256 5257 /* 5258 * R36865 (0x9001) - DSP3 ZM 1 5259 */ 5260 #define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */ 5261 #define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */ 5262 #define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */ 5263 5264 /* 5265 * R36866 (0x9002) - DSP3 ZM 2 5266 */ 5267 #define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */ 5268 #define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */ 5269 #define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */ 5270 5271 /* 5272 * R36867 (0x9003) - DSP3 ZM 3 5273 */ 5274 #define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */ 5275 #define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */ 5276 #define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */ 5277 5278 /* 5279 * R38908 (0x97FC) - DSP3 ZM 2044 5280 */ 5281 #define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */ 5282 #define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */ 5283 #define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */ 5284 5285 /* 5286 * R38909 (0x97FD) - DSP3 ZM 2045 5287 */ 5288 #define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */ 5289 #define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */ 5290 #define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */ 5291 5292 /* 5293 * R38910 (0x97FE) - DSP3 ZM 2046 5294 */ 5295 #define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */ 5296 #define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */ 5297 #define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */ 5298 5299 /* 5300 * R38911 (0x97FF) - DSP3 ZM 2047 5301 */ 5302 #define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */ 5303 #define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */ 5304 #define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */ 5305 5306 bool wm5100_readable_register(struct device *dev, unsigned int reg); 5307 bool wm5100_volatile_register(struct device *dev, unsigned int reg); 5308 5309 extern struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT]; 5310 5311 #endif 5312
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