1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * wm8993.c -- WM8993 ALSA SoC audio driver
4 *
5 * Copyright 2009-12 Wolfson Microelectronics plc
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 */
9
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/spi/spi.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/tlv.h>
24 #include <sound/soc.h>
25 #include <sound/initval.h>
26 #include <sound/wm8993.h>
27
28 #include "wm8993.h"
29 #include "wm_hubs.h"
30
31 #define WM8993_NUM_SUPPLIES 6
32 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
33 "DCVDD",
34 "DBVDD",
35 "AVDD1",
36 "AVDD2",
37 "CPVDD",
38 "SPKVDD",
39 };
40
41 static const struct reg_default wm8993_reg_defaults[] = {
42 { 1, 0x0000 }, /* R1 - Power Management (1) */
43 { 2, 0x6000 }, /* R2 - Power Management (2) */
44 { 3, 0x0000 }, /* R3 - Power Management (3) */
45 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
46 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
47 { 6, 0x01C8 }, /* R6 - Clocking 1 */
48 { 7, 0x0000 }, /* R7 - Clocking 2 */
49 { 8, 0x0000 }, /* R8 - Audio Interface (3) */
50 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
51 { 10, 0x0004 }, /* R10 - DAC CTRL */
52 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
53 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
54 { 13, 0x0000 }, /* R13 - Digital Side Tone */
55 { 14, 0x0300 }, /* R14 - ADC CTRL */
56 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
57 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
58 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
59 { 19, 0x0010 }, /* R19 - GPIO1 */
60 { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */
61 { 21, 0x0000 }, /* R21 - Inputs Clamp */
62 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
63 { 23, 0x0800 }, /* R23 - GPIO_POL */
64 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
65 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
66 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
67 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
68 { 28, 0x006D }, /* R28 - Left Output Volume */
69 { 29, 0x006D }, /* R29 - Right Output Volume */
70 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
71 { 31, 0x0020 }, /* R31 - HPOUT2 Volume */
72 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
73 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
74 { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */
75 { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */
76 { 36, 0x0011 }, /* R36 - SPKOUT Mixers */
77 { 37, 0x0100 }, /* R37 - SPKOUT Boost */
78 { 38, 0x0079 }, /* R38 - Speaker Volume Left */
79 { 39, 0x0079 }, /* R39 - Speaker Volume Right */
80 { 40, 0x0000 }, /* R40 - Input Mixer2 */
81 { 41, 0x0000 }, /* R41 - Input Mixer3 */
82 { 42, 0x0000 }, /* R42 - Input Mixer4 */
83 { 43, 0x0000 }, /* R43 - Input Mixer5 */
84 { 44, 0x0000 }, /* R44 - Input Mixer6 */
85 { 45, 0x0000 }, /* R45 - Output Mixer1 */
86 { 46, 0x0000 }, /* R46 - Output Mixer2 */
87 { 47, 0x0000 }, /* R47 - Output Mixer3 */
88 { 48, 0x0000 }, /* R48 - Output Mixer4 */
89 { 49, 0x0000 }, /* R49 - Output Mixer5 */
90 { 50, 0x0000 }, /* R50 - Output Mixer6 */
91 { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */
92 { 52, 0x0000 }, /* R52 - Line Mixer1 */
93 { 53, 0x0000 }, /* R53 - Line Mixer2 */
94 { 54, 0x0000 }, /* R54 - Speaker Mixer */
95 { 55, 0x0000 }, /* R55 - Additional Control */
96 { 56, 0x0000 }, /* R56 - AntiPOP1 */
97 { 57, 0x0000 }, /* R57 - AntiPOP2 */
98 { 58, 0x0000 }, /* R58 - MICBIAS */
99 { 60, 0x0000 }, /* R60 - FLL Control 1 */
100 { 61, 0x0000 }, /* R61 - FLL Control 2 */
101 { 62, 0x0000 }, /* R62 - FLL Control 3 */
102 { 63, 0x2EE0 }, /* R63 - FLL Control 4 */
103 { 64, 0x0002 }, /* R64 - FLL Control 5 */
104 { 65, 0x2287 }, /* R65 - Clocking 3 */
105 { 66, 0x025F }, /* R66 - Clocking 4 */
106 { 67, 0x0000 }, /* R67 - MW Slave Control */
107 { 69, 0x0002 }, /* R69 - Bus Control 1 */
108 { 70, 0x0000 }, /* R70 - Write Sequencer 0 */
109 { 71, 0x0000 }, /* R71 - Write Sequencer 1 */
110 { 72, 0x0000 }, /* R72 - Write Sequencer 2 */
111 { 73, 0x0000 }, /* R73 - Write Sequencer 3 */
112 { 74, 0x0000 }, /* R74 - Write Sequencer 4 */
113 { 75, 0x0000 }, /* R75 - Write Sequencer 5 */
114 { 76, 0x1F25 }, /* R76 - Charge Pump 1 */
115 { 81, 0x0000 }, /* R81 - Class W 0 */
116 { 85, 0x054A }, /* R85 - DC Servo 1 */
117 { 87, 0x0000 }, /* R87 - DC Servo 3 */
118 { 96, 0x0100 }, /* R96 - Analogue HP 0 */
119 { 98, 0x0000 }, /* R98 - EQ1 */
120 { 99, 0x000C }, /* R99 - EQ2 */
121 { 100, 0x000C }, /* R100 - EQ3 */
122 { 101, 0x000C }, /* R101 - EQ4 */
123 { 102, 0x000C }, /* R102 - EQ5 */
124 { 103, 0x000C }, /* R103 - EQ6 */
125 { 104, 0x0FCA }, /* R104 - EQ7 */
126 { 105, 0x0400 }, /* R105 - EQ8 */
127 { 106, 0x00D8 }, /* R106 - EQ9 */
128 { 107, 0x1EB5 }, /* R107 - EQ10 */
129 { 108, 0xF145 }, /* R108 - EQ11 */
130 { 109, 0x0B75 }, /* R109 - EQ12 */
131 { 110, 0x01C5 }, /* R110 - EQ13 */
132 { 111, 0x1C58 }, /* R111 - EQ14 */
133 { 112, 0xF373 }, /* R112 - EQ15 */
134 { 113, 0x0A54 }, /* R113 - EQ16 */
135 { 114, 0x0558 }, /* R114 - EQ17 */
136 { 115, 0x168E }, /* R115 - EQ18 */
137 { 116, 0xF829 }, /* R116 - EQ19 */
138 { 117, 0x07AD }, /* R117 - EQ20 */
139 { 118, 0x1103 }, /* R118 - EQ21 */
140 { 119, 0x0564 }, /* R119 - EQ22 */
141 { 120, 0x0559 }, /* R120 - EQ23 */
142 { 121, 0x4000 }, /* R121 - EQ24 */
143 { 122, 0x0000 }, /* R122 - Digital Pulls */
144 { 123, 0x0F08 }, /* R123 - DRC Control 1 */
145 { 124, 0x0000 }, /* R124 - DRC Control 2 */
146 { 125, 0x0080 }, /* R125 - DRC Control 3 */
147 { 126, 0x0000 }, /* R126 - DRC Control 4 */
148 };
149
150 static struct {
151 int ratio;
152 int clk_sys_rate;
153 } clk_sys_rates[] = {
154 { 64, 0 },
155 { 128, 1 },
156 { 192, 2 },
157 { 256, 3 },
158 { 384, 4 },
159 { 512, 5 },
160 { 768, 6 },
161 { 1024, 7 },
162 { 1408, 8 },
163 { 1536, 9 },
164 };
165
166 static struct {
167 int rate;
168 int sample_rate;
169 } sample_rates[] = {
170 { 8000, 0 },
171 { 11025, 1 },
172 { 12000, 1 },
173 { 16000, 2 },
174 { 22050, 3 },
175 { 24000, 3 },
176 { 32000, 4 },
177 { 44100, 5 },
178 { 48000, 5 },
179 };
180
181 static struct {
182 int div; /* *10 due to .5s */
183 int bclk_div;
184 } bclk_divs[] = {
185 { 10, 0 },
186 { 15, 1 },
187 { 20, 2 },
188 { 30, 3 },
189 { 40, 4 },
190 { 55, 5 },
191 { 60, 6 },
192 { 80, 7 },
193 { 110, 8 },
194 { 120, 9 },
195 { 160, 10 },
196 { 220, 11 },
197 { 240, 12 },
198 { 320, 13 },
199 { 440, 14 },
200 { 480, 15 },
201 };
202
203 struct wm8993_priv {
204 struct wm_hubs_data hubs_data;
205 struct device *dev;
206 struct regmap *regmap;
207 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
208 struct wm8993_platform_data pdata;
209 struct completion fll_lock;
210 int master;
211 int sysclk_source;
212 int tdm_slots;
213 int tdm_width;
214 unsigned int mclk_rate;
215 unsigned int sysclk_rate;
216 unsigned int fs;
217 unsigned int bclk;
218 unsigned int fll_fref;
219 unsigned int fll_fout;
220 int fll_src;
221 };
222
223 static bool wm8993_volatile(struct device *dev, unsigned int reg)
224 {
225 switch (reg) {
226 case WM8993_SOFTWARE_RESET:
227 case WM8993_GPIO_CTRL_1:
228 case WM8993_DC_SERVO_0:
229 case WM8993_DC_SERVO_READBACK_0:
230 case WM8993_DC_SERVO_READBACK_1:
231 case WM8993_DC_SERVO_READBACK_2:
232 return true;
233 default:
234 return false;
235 }
236 }
237
238 static bool wm8993_readable(struct device *dev, unsigned int reg)
239 {
240 switch (reg) {
241 case WM8993_SOFTWARE_RESET:
242 case WM8993_POWER_MANAGEMENT_1:
243 case WM8993_POWER_MANAGEMENT_2:
244 case WM8993_POWER_MANAGEMENT_3:
245 case WM8993_AUDIO_INTERFACE_1:
246 case WM8993_AUDIO_INTERFACE_2:
247 case WM8993_CLOCKING_1:
248 case WM8993_CLOCKING_2:
249 case WM8993_AUDIO_INTERFACE_3:
250 case WM8993_AUDIO_INTERFACE_4:
251 case WM8993_DAC_CTRL:
252 case WM8993_LEFT_DAC_DIGITAL_VOLUME:
253 case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
254 case WM8993_DIGITAL_SIDE_TONE:
255 case WM8993_ADC_CTRL:
256 case WM8993_LEFT_ADC_DIGITAL_VOLUME:
257 case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
258 case WM8993_GPIO_CTRL_1:
259 case WM8993_GPIO1:
260 case WM8993_IRQ_DEBOUNCE:
261 case WM8993_GPIOCTRL_2:
262 case WM8993_GPIO_POL:
263 case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
264 case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
265 case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
266 case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
267 case WM8993_LEFT_OUTPUT_VOLUME:
268 case WM8993_RIGHT_OUTPUT_VOLUME:
269 case WM8993_LINE_OUTPUTS_VOLUME:
270 case WM8993_HPOUT2_VOLUME:
271 case WM8993_LEFT_OPGA_VOLUME:
272 case WM8993_RIGHT_OPGA_VOLUME:
273 case WM8993_SPKMIXL_ATTENUATION:
274 case WM8993_SPKMIXR_ATTENUATION:
275 case WM8993_SPKOUT_MIXERS:
276 case WM8993_SPKOUT_BOOST:
277 case WM8993_SPEAKER_VOLUME_LEFT:
278 case WM8993_SPEAKER_VOLUME_RIGHT:
279 case WM8993_INPUT_MIXER2:
280 case WM8993_INPUT_MIXER3:
281 case WM8993_INPUT_MIXER4:
282 case WM8993_INPUT_MIXER5:
283 case WM8993_INPUT_MIXER6:
284 case WM8993_OUTPUT_MIXER1:
285 case WM8993_OUTPUT_MIXER2:
286 case WM8993_OUTPUT_MIXER3:
287 case WM8993_OUTPUT_MIXER4:
288 case WM8993_OUTPUT_MIXER5:
289 case WM8993_OUTPUT_MIXER6:
290 case WM8993_HPOUT2_MIXER:
291 case WM8993_LINE_MIXER1:
292 case WM8993_LINE_MIXER2:
293 case WM8993_SPEAKER_MIXER:
294 case WM8993_ADDITIONAL_CONTROL:
295 case WM8993_ANTIPOP1:
296 case WM8993_ANTIPOP2:
297 case WM8993_MICBIAS:
298 case WM8993_FLL_CONTROL_1:
299 case WM8993_FLL_CONTROL_2:
300 case WM8993_FLL_CONTROL_3:
301 case WM8993_FLL_CONTROL_4:
302 case WM8993_FLL_CONTROL_5:
303 case WM8993_CLOCKING_3:
304 case WM8993_CLOCKING_4:
305 case WM8993_MW_SLAVE_CONTROL:
306 case WM8993_BUS_CONTROL_1:
307 case WM8993_WRITE_SEQUENCER_0:
308 case WM8993_WRITE_SEQUENCER_1:
309 case WM8993_WRITE_SEQUENCER_2:
310 case WM8993_WRITE_SEQUENCER_3:
311 case WM8993_WRITE_SEQUENCER_4:
312 case WM8993_WRITE_SEQUENCER_5:
313 case WM8993_CHARGE_PUMP_1:
314 case WM8993_CLASS_W_0:
315 case WM8993_DC_SERVO_0:
316 case WM8993_DC_SERVO_1:
317 case WM8993_DC_SERVO_3:
318 case WM8993_DC_SERVO_READBACK_0:
319 case WM8993_DC_SERVO_READBACK_1:
320 case WM8993_DC_SERVO_READBACK_2:
321 case WM8993_ANALOGUE_HP_0:
322 case WM8993_EQ1:
323 case WM8993_EQ2:
324 case WM8993_EQ3:
325 case WM8993_EQ4:
326 case WM8993_EQ5:
327 case WM8993_EQ6:
328 case WM8993_EQ7:
329 case WM8993_EQ8:
330 case WM8993_EQ9:
331 case WM8993_EQ10:
332 case WM8993_EQ11:
333 case WM8993_EQ12:
334 case WM8993_EQ13:
335 case WM8993_EQ14:
336 case WM8993_EQ15:
337 case WM8993_EQ16:
338 case WM8993_EQ17:
339 case WM8993_EQ18:
340 case WM8993_EQ19:
341 case WM8993_EQ20:
342 case WM8993_EQ21:
343 case WM8993_EQ22:
344 case WM8993_EQ23:
345 case WM8993_EQ24:
346 case WM8993_DIGITAL_PULLS:
347 case WM8993_DRC_CONTROL_1:
348 case WM8993_DRC_CONTROL_2:
349 case WM8993_DRC_CONTROL_3:
350 case WM8993_DRC_CONTROL_4:
351 return true;
352 default:
353 return false;
354 }
355 }
356
357 struct _fll_div {
358 u16 fll_fratio;
359 u16 fll_outdiv;
360 u16 fll_clk_ref_div;
361 u16 n;
362 u16 k;
363 };
364
365 /* The size in bits of the FLL divide multiplied by 10
366 * to allow rounding later */
367 #define FIXED_FLL_SIZE ((1 << 16) * 10)
368
369 static struct {
370 unsigned int min;
371 unsigned int max;
372 u16 fll_fratio;
373 int ratio;
374 } fll_fratios[] = {
375 { 0, 64000, 4, 16 },
376 { 64000, 128000, 3, 8 },
377 { 128000, 256000, 2, 4 },
378 { 256000, 1000000, 1, 2 },
379 { 1000000, 13500000, 0, 1 },
380 };
381
382 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
383 unsigned int Fout)
384 {
385 u64 Kpart;
386 unsigned int K, Ndiv, Nmod, target;
387 unsigned int div;
388 int i;
389
390 /* Fref must be <=13.5MHz */
391 div = 1;
392 fll_div->fll_clk_ref_div = 0;
393 while ((Fref / div) > 13500000) {
394 div *= 2;
395 fll_div->fll_clk_ref_div++;
396
397 if (div > 8) {
398 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
399 Fref);
400 return -EINVAL;
401 }
402 }
403
404 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
405
406 /* Apply the division for our remaining calculations */
407 Fref /= div;
408
409 /* Fvco should be 90-100MHz; don't check the upper bound */
410 div = 0;
411 target = Fout * 2;
412 while (target < 90000000) {
413 div++;
414 target *= 2;
415 if (div > 7) {
416 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
417 Fout);
418 return -EINVAL;
419 }
420 }
421 fll_div->fll_outdiv = div;
422
423 pr_debug("Fvco=%dHz\n", target);
424
425 /* Find an appropriate FLL_FRATIO and factor it out of the target */
426 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
427 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
428 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
429 target /= fll_fratios[i].ratio;
430 break;
431 }
432 }
433 if (i == ARRAY_SIZE(fll_fratios)) {
434 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
435 return -EINVAL;
436 }
437
438 /* Now, calculate N.K */
439 Ndiv = target / Fref;
440
441 fll_div->n = Ndiv;
442 Nmod = target % Fref;
443 pr_debug("Nmod=%d\n", Nmod);
444
445 /* Calculate fractional part - scale up so we can round. */
446 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
447
448 do_div(Kpart, Fref);
449
450 K = Kpart & 0xFFFFFFFF;
451
452 if ((K % 10) >= 5)
453 K += 5;
454
455 /* Move down to proper range now rounding is done */
456 fll_div->k = K / 10;
457
458 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
459 fll_div->n, fll_div->k,
460 fll_div->fll_fratio, fll_div->fll_outdiv,
461 fll_div->fll_clk_ref_div);
462
463 return 0;
464 }
465
466 static int _wm8993_set_fll(struct snd_soc_component *component, int fll_id, int source,
467 unsigned int Fref, unsigned int Fout)
468 {
469 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
470 struct i2c_client *i2c = to_i2c_client(component->dev);
471 u16 reg1, reg4, reg5;
472 struct _fll_div fll_div;
473 unsigned long time_left;
474 int ret;
475
476 /* Any change? */
477 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
478 return 0;
479
480 /* Disable the FLL */
481 if (Fout == 0) {
482 dev_dbg(component->dev, "FLL disabled\n");
483 wm8993->fll_fref = 0;
484 wm8993->fll_fout = 0;
485
486 reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
487 reg1 &= ~WM8993_FLL_ENA;
488 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
489
490 return 0;
491 }
492
493 ret = fll_factors(&fll_div, Fref, Fout);
494 if (ret != 0)
495 return ret;
496
497 reg5 = snd_soc_component_read(component, WM8993_FLL_CONTROL_5);
498 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
499
500 switch (fll_id) {
501 case WM8993_FLL_MCLK:
502 break;
503
504 case WM8993_FLL_LRCLK:
505 reg5 |= 1;
506 break;
507
508 case WM8993_FLL_BCLK:
509 reg5 |= 2;
510 break;
511
512 default:
513 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
514 return -EINVAL;
515 }
516
517 /* Any FLL configuration change requires that the FLL be
518 * disabled first. */
519 reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
520 reg1 &= ~WM8993_FLL_ENA;
521 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
522
523 /* Apply the configuration */
524 if (fll_div.k)
525 reg1 |= WM8993_FLL_FRAC_MASK;
526 else
527 reg1 &= ~WM8993_FLL_FRAC_MASK;
528 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
529
530 snd_soc_component_write(component, WM8993_FLL_CONTROL_2,
531 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
532 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
533 snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k);
534
535 reg4 = snd_soc_component_read(component, WM8993_FLL_CONTROL_4);
536 reg4 &= ~WM8993_FLL_N_MASK;
537 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
538 snd_soc_component_write(component, WM8993_FLL_CONTROL_4, reg4);
539
540 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
541 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
542 snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5);
543
544 /* If we've got an interrupt wired up make sure we get it */
545 if (i2c->irq)
546 time_left = msecs_to_jiffies(20);
547 else if (Fref < 1000000)
548 time_left = msecs_to_jiffies(3);
549 else
550 time_left = msecs_to_jiffies(1);
551
552 try_wait_for_completion(&wm8993->fll_lock);
553
554 /* Enable the FLL */
555 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
556
557 time_left = wait_for_completion_timeout(&wm8993->fll_lock, time_left);
558 if (i2c->irq && !time_left)
559 dev_warn(component->dev, "Timed out waiting for FLL\n");
560
561 dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
562
563 wm8993->fll_fref = Fref;
564 wm8993->fll_fout = Fout;
565 wm8993->fll_src = source;
566
567 return 0;
568 }
569
570 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
571 unsigned int Fref, unsigned int Fout)
572 {
573 return _wm8993_set_fll(dai->component, fll_id, source, Fref, Fout);
574 }
575
576 static int configure_clock(struct snd_soc_component *component)
577 {
578 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
579 unsigned int reg;
580
581 /* This should be done on init() for bypass paths */
582 switch (wm8993->sysclk_source) {
583 case WM8993_SYSCLK_MCLK:
584 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
585
586 reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
587 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
588 if (wm8993->mclk_rate > 13500000) {
589 reg |= WM8993_MCLK_DIV;
590 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
591 } else {
592 reg &= ~WM8993_MCLK_DIV;
593 wm8993->sysclk_rate = wm8993->mclk_rate;
594 }
595 snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
596 break;
597
598 case WM8993_SYSCLK_FLL:
599 dev_dbg(component->dev, "Using %dHz FLL clock\n",
600 wm8993->fll_fout);
601
602 reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
603 reg |= WM8993_SYSCLK_SRC;
604 if (wm8993->fll_fout > 13500000) {
605 reg |= WM8993_MCLK_DIV;
606 wm8993->sysclk_rate = wm8993->fll_fout / 2;
607 } else {
608 reg &= ~WM8993_MCLK_DIV;
609 wm8993->sysclk_rate = wm8993->fll_fout;
610 }
611 snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
612 break;
613
614 default:
615 dev_err(component->dev, "System clock not configured\n");
616 return -EINVAL;
617 }
618
619 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
620
621 return 0;
622 }
623
624 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
625 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
626 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
627 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
628 static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
629 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
630 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
631 );
632 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
633 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
634 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
635 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
636 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
637
638 static const char *dac_deemph_text[] = {
639 "None",
640 "32kHz",
641 "44.1kHz",
642 "48kHz",
643 };
644
645 static SOC_ENUM_SINGLE_DECL(dac_deemph,
646 WM8993_DAC_CTRL, 4, dac_deemph_text);
647
648 static const char *adc_hpf_text[] = {
649 "Hi-Fi",
650 "Voice 1",
651 "Voice 2",
652 "Voice 3",
653 };
654
655 static SOC_ENUM_SINGLE_DECL(adc_hpf,
656 WM8993_ADC_CTRL, 5, adc_hpf_text);
657
658 static const char *drc_path_text[] = {
659 "ADC",
660 "DAC"
661 };
662
663 static SOC_ENUM_SINGLE_DECL(drc_path,
664 WM8993_DRC_CONTROL_1, 14, drc_path_text);
665
666 static const char *drc_r0_text[] = {
667 "1",
668 "1/2",
669 "1/4",
670 "1/8",
671 "1/16",
672 "",
673 };
674
675 static SOC_ENUM_SINGLE_DECL(drc_r0,
676 WM8993_DRC_CONTROL_3, 8, drc_r0_text);
677
678 static const char *drc_r1_text[] = {
679 "1",
680 "1/2",
681 "1/4",
682 "1/8",
683 "",
684 };
685
686 static SOC_ENUM_SINGLE_DECL(drc_r1,
687 WM8993_DRC_CONTROL_4, 13, drc_r1_text);
688
689 static const char *drc_attack_text[] = {
690 "Reserved",
691 "181us",
692 "363us",
693 "726us",
694 "1.45ms",
695 "2.9ms",
696 "5.8ms",
697 "11.6ms",
698 "23.2ms",
699 "46.4ms",
700 "92.8ms",
701 "185.6ms",
702 };
703
704 static SOC_ENUM_SINGLE_DECL(drc_attack,
705 WM8993_DRC_CONTROL_2, 12, drc_attack_text);
706
707 static const char *drc_decay_text[] = {
708 "186ms",
709 "372ms",
710 "743ms",
711 "1.49s",
712 "2.97ms",
713 "5.94ms",
714 "11.89ms",
715 "23.78ms",
716 "47.56ms",
717 };
718
719 static SOC_ENUM_SINGLE_DECL(drc_decay,
720 WM8993_DRC_CONTROL_2, 8, drc_decay_text);
721
722 static const char *drc_ff_text[] = {
723 "5 samples",
724 "9 samples",
725 };
726
727 static SOC_ENUM_SINGLE_DECL(drc_ff,
728 WM8993_DRC_CONTROL_3, 7, drc_ff_text);
729
730 static const char *drc_qr_rate_text[] = {
731 "0.725ms",
732 "1.45ms",
733 "5.8ms",
734 };
735
736 static SOC_ENUM_SINGLE_DECL(drc_qr_rate,
737 WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text);
738
739 static const char *drc_smooth_text[] = {
740 "Low",
741 "Medium",
742 "High",
743 };
744
745 static SOC_ENUM_SINGLE_DECL(drc_smooth,
746 WM8993_DRC_CONTROL_1, 4, drc_smooth_text);
747
748 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
749 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
750 5, 9, 12, 0, sidetone_tlv),
751
752 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
753 SOC_ENUM("DRC Path", drc_path),
754 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
755 2, 60, 1, drc_comp_threash),
756 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
757 11, 30, 1, drc_comp_amp),
758 SOC_ENUM("DRC R0", drc_r0),
759 SOC_ENUM("DRC R1", drc_r1),
760 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
761 drc_min_tlv),
762 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
763 drc_max_tlv),
764 SOC_ENUM("DRC Attack Rate", drc_attack),
765 SOC_ENUM("DRC Decay Rate", drc_decay),
766 SOC_ENUM("DRC FF Delay", drc_ff),
767 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
768 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
769 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
770 drc_qr_tlv),
771 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
772 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
773 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
774 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
775 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
776 drc_startup_tlv),
777
778 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
779
780 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
781 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
782 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
783 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
784
785 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
786 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
787 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
788 dac_boost_tlv),
789 SOC_ENUM("DAC Deemphasis", dac_deemph),
790
791 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
792 2, 1, 1, wm_hubs_spkmix_tlv),
793
794 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
795 2, 1, 1, wm_hubs_spkmix_tlv),
796 };
797
798 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
799 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
800 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
801 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
802 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
803 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
804 };
805
806 static int clk_sys_event(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808 {
809 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
810
811 switch (event) {
812 case SND_SOC_DAPM_PRE_PMU:
813 return configure_clock(component);
814
815 case SND_SOC_DAPM_POST_PMD:
816 break;
817 }
818
819 return 0;
820 }
821
822 static const struct snd_kcontrol_new left_speaker_mixer[] = {
823 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
824 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
825 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
826 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
827 };
828
829 static const struct snd_kcontrol_new right_speaker_mixer[] = {
830 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
831 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
832 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
833 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
834 };
835
836 static const char *aif_text[] = {
837 "Left", "Right"
838 };
839
840 static SOC_ENUM_SINGLE_DECL(aifoutl_enum,
841 WM8993_AUDIO_INTERFACE_1, 15, aif_text);
842
843 static const struct snd_kcontrol_new aifoutl_mux =
844 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
845
846 static SOC_ENUM_SINGLE_DECL(aifoutr_enum,
847 WM8993_AUDIO_INTERFACE_1, 14, aif_text);
848
849 static const struct snd_kcontrol_new aifoutr_mux =
850 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
851
852 static SOC_ENUM_SINGLE_DECL(aifinl_enum,
853 WM8993_AUDIO_INTERFACE_2, 15, aif_text);
854
855 static const struct snd_kcontrol_new aifinl_mux =
856 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
857
858 static SOC_ENUM_SINGLE_DECL(aifinr_enum,
859 WM8993_AUDIO_INTERFACE_2, 14, aif_text);
860
861 static const struct snd_kcontrol_new aifinr_mux =
862 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
863
864 static const char *sidetone_text[] = {
865 "None", "Left", "Right"
866 };
867
868 static SOC_ENUM_SINGLE_DECL(sidetonel_enum,
869 WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text);
870
871 static const struct snd_kcontrol_new sidetonel_mux =
872 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
873
874 static SOC_ENUM_SINGLE_DECL(sidetoner_enum,
875 WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text);
876
877 static const struct snd_kcontrol_new sidetoner_mux =
878 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
879
880 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
881 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
883 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
884 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
885 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
886
887 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
888 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
889
890 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
891 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
892
893 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
894 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
895
896 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
897 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
898
899 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
900 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
901
902 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
903 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
904
905 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
906 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
907
908 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
909 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
910
911 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
912 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
913 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
914 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
915 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
916 };
917
918 static const struct snd_soc_dapm_route routes[] = {
919 { "MICBIAS1", NULL, "VMID" },
920 { "MICBIAS2", NULL, "VMID" },
921
922 { "ADCL", NULL, "CLK_SYS" },
923 { "ADCL", NULL, "CLK_DSP" },
924 { "ADCR", NULL, "CLK_SYS" },
925 { "ADCR", NULL, "CLK_DSP" },
926
927 { "AIFOUTL Mux", "Left", "ADCL" },
928 { "AIFOUTL Mux", "Right", "ADCR" },
929 { "AIFOUTR Mux", "Left", "ADCL" },
930 { "AIFOUTR Mux", "Right", "ADCR" },
931
932 { "AIFOUTL", NULL, "AIFOUTL Mux" },
933 { "AIFOUTR", NULL, "AIFOUTR Mux" },
934
935 { "DACL Mux", "Left", "AIFINL" },
936 { "DACL Mux", "Right", "AIFINR" },
937 { "DACR Mux", "Left", "AIFINL" },
938 { "DACR Mux", "Right", "AIFINR" },
939
940 { "DACL Sidetone", "Left", "ADCL" },
941 { "DACL Sidetone", "Right", "ADCR" },
942 { "DACR Sidetone", "Left", "ADCL" },
943 { "DACR Sidetone", "Right", "ADCR" },
944
945 { "DACL", NULL, "CLK_SYS" },
946 { "DACL", NULL, "CLK_DSP" },
947 { "DACL", NULL, "DACL Mux" },
948 { "DACL", NULL, "DACL Sidetone" },
949 { "DACR", NULL, "CLK_SYS" },
950 { "DACR", NULL, "CLK_DSP" },
951 { "DACR", NULL, "DACR Mux" },
952 { "DACR", NULL, "DACR Sidetone" },
953
954 { "Left Output Mixer", "DAC Switch", "DACL" },
955
956 { "Right Output Mixer", "DAC Switch", "DACR" },
957
958 { "Left Output PGA", NULL, "CLK_SYS" },
959
960 { "Right Output PGA", NULL, "CLK_SYS" },
961
962 { "SPKL", "DAC Switch", "DACL" },
963 { "SPKL", NULL, "CLK_SYS" },
964
965 { "SPKR", "DAC Switch", "DACR" },
966 { "SPKR", NULL, "CLK_SYS" },
967
968 { "Left Headphone Mux", "DAC", "DACL" },
969 { "Right Headphone Mux", "DAC", "DACR" },
970 };
971
972 static int wm8993_set_bias_level(struct snd_soc_component *component,
973 enum snd_soc_bias_level level)
974 {
975 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
976 int ret;
977
978 wm_hubs_set_bias_level(component, level);
979
980 switch (level) {
981 case SND_SOC_BIAS_ON:
982 case SND_SOC_BIAS_PREPARE:
983 /* VMID=2*40k */
984 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
985 WM8993_VMID_SEL_MASK, 0x2);
986 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
987 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
988 break;
989
990 case SND_SOC_BIAS_STANDBY:
991 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
992 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
993 wm8993->supplies);
994 if (ret != 0)
995 return ret;
996
997 regcache_cache_only(wm8993->regmap, false);
998 regcache_sync(wm8993->regmap);
999
1000 wm_hubs_vmid_ena(component);
1001
1002 /* Bring up VMID with fast soft start */
1003 snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1004 WM8993_STARTUP_BIAS_ENA |
1005 WM8993_VMID_BUF_ENA |
1006 WM8993_VMID_RAMP_MASK |
1007 WM8993_BIAS_SRC,
1008 WM8993_STARTUP_BIAS_ENA |
1009 WM8993_VMID_BUF_ENA |
1010 WM8993_VMID_RAMP_MASK |
1011 WM8993_BIAS_SRC);
1012
1013 /* If either line output is single ended we
1014 * need the VMID buffer */
1015 if (!wm8993->pdata.lineout1_diff ||
1016 !wm8993->pdata.lineout2_diff)
1017 snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1018 WM8993_LINEOUT_VMID_BUF_ENA,
1019 WM8993_LINEOUT_VMID_BUF_ENA);
1020
1021 /* VMID=2*40k */
1022 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1023 WM8993_VMID_SEL_MASK |
1024 WM8993_BIAS_ENA,
1025 WM8993_BIAS_ENA | 0x2);
1026 msleep(32);
1027
1028 /* Switch to normal bias */
1029 snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1030 WM8993_BIAS_SRC |
1031 WM8993_STARTUP_BIAS_ENA, 0);
1032 }
1033
1034 /* VMID=2*240k */
1035 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1036 WM8993_VMID_SEL_MASK, 0x4);
1037
1038 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
1039 WM8993_TSHUT_ENA, 0);
1040 break;
1041
1042 case SND_SOC_BIAS_OFF:
1043 snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1044 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1045
1046 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1047 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1048 0);
1049
1050 snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1051 WM8993_STARTUP_BIAS_ENA |
1052 WM8993_VMID_BUF_ENA |
1053 WM8993_VMID_RAMP_MASK |
1054 WM8993_BIAS_SRC, 0);
1055
1056 regcache_cache_only(wm8993->regmap, true);
1057 regcache_mark_dirty(wm8993->regmap);
1058
1059 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1060 wm8993->supplies);
1061 break;
1062 }
1063
1064 return 0;
1065 }
1066
1067 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1068 int clk_id, unsigned int freq, int dir)
1069 {
1070 struct snd_soc_component *component = codec_dai->component;
1071 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1072
1073 switch (clk_id) {
1074 case WM8993_SYSCLK_MCLK:
1075 wm8993->mclk_rate = freq;
1076 fallthrough;
1077 case WM8993_SYSCLK_FLL:
1078 wm8993->sysclk_source = clk_id;
1079 break;
1080
1081 default:
1082 return -EINVAL;
1083 }
1084
1085 return 0;
1086 }
1087
1088 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1089 unsigned int fmt)
1090 {
1091 struct snd_soc_component *component = dai->component;
1092 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1093 unsigned int aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
1094 unsigned int aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
1095
1096 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1097 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1098 aif4 &= ~WM8993_LRCLK_DIR;
1099
1100 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1101 case SND_SOC_DAIFMT_CBS_CFS:
1102 wm8993->master = 0;
1103 break;
1104 case SND_SOC_DAIFMT_CBS_CFM:
1105 aif4 |= WM8993_LRCLK_DIR;
1106 wm8993->master = 1;
1107 break;
1108 case SND_SOC_DAIFMT_CBM_CFS:
1109 aif1 |= WM8993_BCLK_DIR;
1110 wm8993->master = 1;
1111 break;
1112 case SND_SOC_DAIFMT_CBM_CFM:
1113 aif1 |= WM8993_BCLK_DIR;
1114 aif4 |= WM8993_LRCLK_DIR;
1115 wm8993->master = 1;
1116 break;
1117 default:
1118 return -EINVAL;
1119 }
1120
1121 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1122 case SND_SOC_DAIFMT_DSP_B:
1123 aif1 |= WM8993_AIF_LRCLK_INV;
1124 fallthrough;
1125 case SND_SOC_DAIFMT_DSP_A:
1126 aif1 |= 0x18;
1127 break;
1128 case SND_SOC_DAIFMT_I2S:
1129 aif1 |= 0x10;
1130 break;
1131 case SND_SOC_DAIFMT_RIGHT_J:
1132 break;
1133 case SND_SOC_DAIFMT_LEFT_J:
1134 aif1 |= 0x8;
1135 break;
1136 default:
1137 return -EINVAL;
1138 }
1139
1140 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1141 case SND_SOC_DAIFMT_DSP_A:
1142 case SND_SOC_DAIFMT_DSP_B:
1143 /* frame inversion not valid for DSP modes */
1144 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1145 case SND_SOC_DAIFMT_NB_NF:
1146 break;
1147 case SND_SOC_DAIFMT_IB_NF:
1148 aif1 |= WM8993_AIF_BCLK_INV;
1149 break;
1150 default:
1151 return -EINVAL;
1152 }
1153 break;
1154
1155 case SND_SOC_DAIFMT_I2S:
1156 case SND_SOC_DAIFMT_RIGHT_J:
1157 case SND_SOC_DAIFMT_LEFT_J:
1158 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1159 case SND_SOC_DAIFMT_NB_NF:
1160 break;
1161 case SND_SOC_DAIFMT_IB_IF:
1162 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1163 break;
1164 case SND_SOC_DAIFMT_IB_NF:
1165 aif1 |= WM8993_AIF_BCLK_INV;
1166 break;
1167 case SND_SOC_DAIFMT_NB_IF:
1168 aif1 |= WM8993_AIF_LRCLK_INV;
1169 break;
1170 default:
1171 return -EINVAL;
1172 }
1173 break;
1174 default:
1175 return -EINVAL;
1176 }
1177
1178 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
1179 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
1180
1181 return 0;
1182 }
1183
1184 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1185 struct snd_pcm_hw_params *params,
1186 struct snd_soc_dai *dai)
1187 {
1188 struct snd_soc_component *component = dai->component;
1189 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1190 int ret, i, best, best_val, cur_val;
1191 unsigned int clocking1, clocking3, aif1, aif4;
1192
1193 clocking1 = snd_soc_component_read(component, WM8993_CLOCKING_1);
1194 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1195
1196 clocking3 = snd_soc_component_read(component, WM8993_CLOCKING_3);
1197 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1198
1199 aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
1200 aif1 &= ~WM8993_AIF_WL_MASK;
1201
1202 aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
1203 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1204
1205 /* What BCLK do we need? */
1206 wm8993->fs = params_rate(params);
1207 wm8993->bclk = 2 * wm8993->fs;
1208 if (wm8993->tdm_slots) {
1209 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1210 wm8993->tdm_slots, wm8993->tdm_width);
1211 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1212 } else {
1213 switch (params_width(params)) {
1214 case 16:
1215 wm8993->bclk *= 16;
1216 break;
1217 case 20:
1218 wm8993->bclk *= 20;
1219 aif1 |= 0x8;
1220 break;
1221 case 24:
1222 wm8993->bclk *= 24;
1223 aif1 |= 0x10;
1224 break;
1225 case 32:
1226 wm8993->bclk *= 32;
1227 aif1 |= 0x18;
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232 }
1233
1234 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1235
1236 ret = configure_clock(component);
1237 if (ret != 0)
1238 return ret;
1239
1240 /* Select nearest CLK_SYS_RATE */
1241 best = 0;
1242 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1243 - wm8993->fs);
1244 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1245 cur_val = abs((wm8993->sysclk_rate /
1246 clk_sys_rates[i].ratio) - wm8993->fs);
1247 if (cur_val < best_val) {
1248 best = i;
1249 best_val = cur_val;
1250 }
1251 }
1252 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1253 clk_sys_rates[best].ratio);
1254 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1255 << WM8993_CLK_SYS_RATE_SHIFT);
1256
1257 /* SAMPLE_RATE */
1258 best = 0;
1259 best_val = abs(wm8993->fs - sample_rates[0].rate);
1260 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1261 /* Closest match */
1262 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1263 if (cur_val < best_val) {
1264 best = i;
1265 best_val = cur_val;
1266 }
1267 }
1268 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1269 sample_rates[best].rate);
1270 clocking3 |= (sample_rates[best].sample_rate
1271 << WM8993_SAMPLE_RATE_SHIFT);
1272
1273 /* BCLK_DIV */
1274 best = 0;
1275 best_val = INT_MAX;
1276 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1277 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1278 - wm8993->bclk;
1279 if (cur_val < 0) /* Table is sorted */
1280 break;
1281 if (cur_val < best_val) {
1282 best = i;
1283 best_val = cur_val;
1284 }
1285 }
1286 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1287 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1288 bclk_divs[best].div, wm8993->bclk);
1289 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1290
1291 /* LRCLK is a simple fraction of BCLK */
1292 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1293 aif4 |= wm8993->bclk / wm8993->fs;
1294
1295 snd_soc_component_write(component, WM8993_CLOCKING_1, clocking1);
1296 snd_soc_component_write(component, WM8993_CLOCKING_3, clocking3);
1297 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
1298 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
1299
1300 /* ReTune Mobile? */
1301 if (wm8993->pdata.num_retune_configs) {
1302 u16 eq1 = snd_soc_component_read(component, WM8993_EQ1);
1303 struct wm8993_retune_mobile_setting *s;
1304
1305 best = 0;
1306 best_val = abs(wm8993->pdata.retune_configs[0].rate
1307 - wm8993->fs);
1308 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1309 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1310 - wm8993->fs);
1311 if (cur_val < best_val) {
1312 best_val = cur_val;
1313 best = i;
1314 }
1315 }
1316 s = &wm8993->pdata.retune_configs[best];
1317
1318 dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
1319 s->name, s->rate);
1320
1321 /* Disable EQ while we reconfigure */
1322 snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, 0);
1323
1324 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1325 snd_soc_component_write(component, WM8993_EQ1 + i, s->config[i]);
1326
1327 snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1328 }
1329
1330 return 0;
1331 }
1332
1333 static int wm8993_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1334 {
1335 struct snd_soc_component *component = codec_dai->component;
1336 unsigned int reg;
1337
1338 reg = snd_soc_component_read(component, WM8993_DAC_CTRL);
1339
1340 if (mute)
1341 reg |= WM8993_DAC_MUTE;
1342 else
1343 reg &= ~WM8993_DAC_MUTE;
1344
1345 snd_soc_component_write(component, WM8993_DAC_CTRL, reg);
1346
1347 return 0;
1348 }
1349
1350 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1351 unsigned int rx_mask, int slots, int slot_width)
1352 {
1353 struct snd_soc_component *component = dai->component;
1354 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1355 int aif1 = 0;
1356 int aif2 = 0;
1357
1358 /* Don't need to validate anything if we're turning off TDM */
1359 if (slots == 0) {
1360 wm8993->tdm_slots = 0;
1361 goto out;
1362 }
1363
1364 /* Note that we allow configurations we can't handle ourselves -
1365 * for example, we can generate clocks for slots 2 and up even if
1366 * we can't use those slots ourselves.
1367 */
1368 aif1 |= WM8993_AIFADC_TDM;
1369 aif2 |= WM8993_AIFDAC_TDM;
1370
1371 switch (rx_mask) {
1372 case 3:
1373 break;
1374 case 0xc:
1375 aif1 |= WM8993_AIFADC_TDM_CHAN;
1376 break;
1377 default:
1378 return -EINVAL;
1379 }
1380
1381
1382 switch (tx_mask) {
1383 case 3:
1384 break;
1385 case 0xc:
1386 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1387 break;
1388 default:
1389 return -EINVAL;
1390 }
1391
1392 out:
1393 wm8993->tdm_width = slot_width;
1394 wm8993->tdm_slots = slots / 2;
1395
1396 snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_1,
1397 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1398 snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_2,
1399 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1400
1401 return 0;
1402 }
1403
1404 static irqreturn_t wm8993_irq(int irq, void *data)
1405 {
1406 struct wm8993_priv *wm8993 = data;
1407 int mask, val, ret;
1408
1409 ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
1410 if (ret != 0) {
1411 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
1412 ret);
1413 return IRQ_NONE;
1414 }
1415
1416 ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
1417 if (ret != 0) {
1418 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
1419 ret);
1420 return IRQ_NONE;
1421 }
1422
1423 /* The IRQ pin status is visible in the register too */
1424 val &= ~(mask | WM8993_IRQ);
1425 if (!val)
1426 return IRQ_NONE;
1427
1428 if (val & WM8993_TEMPOK_EINT)
1429 dev_crit(wm8993->dev, "Thermal warning\n");
1430
1431 if (val & WM8993_FLL_LOCK_EINT) {
1432 dev_dbg(wm8993->dev, "FLL locked\n");
1433 complete(&wm8993->fll_lock);
1434 }
1435
1436 ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
1437 if (ret != 0)
1438 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
1439
1440 return IRQ_HANDLED;
1441 }
1442
1443 static const struct snd_soc_dai_ops wm8993_ops = {
1444 .set_sysclk = wm8993_set_sysclk,
1445 .set_fmt = wm8993_set_dai_fmt,
1446 .hw_params = wm8993_hw_params,
1447 .mute_stream = wm8993_mute,
1448 .set_pll = wm8993_set_fll,
1449 .set_tdm_slot = wm8993_set_tdm_slot,
1450 .no_capture_mute = 1,
1451 };
1452
1453 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1454
1455 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1456 SNDRV_PCM_FMTBIT_S20_3LE |\
1457 SNDRV_PCM_FMTBIT_S24_LE |\
1458 SNDRV_PCM_FMTBIT_S32_LE)
1459
1460 static struct snd_soc_dai_driver wm8993_dai = {
1461 .name = "wm8993-hifi",
1462 .playback = {
1463 .stream_name = "Playback",
1464 .channels_min = 1,
1465 .channels_max = 2,
1466 .rates = WM8993_RATES,
1467 .formats = WM8993_FORMATS,
1468 .sig_bits = 24,
1469 },
1470 .capture = {
1471 .stream_name = "Capture",
1472 .channels_min = 1,
1473 .channels_max = 2,
1474 .rates = WM8993_RATES,
1475 .formats = WM8993_FORMATS,
1476 .sig_bits = 24,
1477 },
1478 .ops = &wm8993_ops,
1479 .symmetric_rate = 1,
1480 };
1481
1482 static int wm8993_probe(struct snd_soc_component *component)
1483 {
1484 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1485 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1486
1487 wm8993->hubs_data.hp_startup_mode = 1;
1488 wm8993->hubs_data.dcs_codes_l = -2;
1489 wm8993->hubs_data.dcs_codes_r = -2;
1490 wm8993->hubs_data.series_startup = 1;
1491
1492 /* Latch volume update bits and default ZC on */
1493 snd_soc_component_update_bits(component, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1494 WM8993_DAC_VU, WM8993_DAC_VU);
1495 snd_soc_component_update_bits(component, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1496 WM8993_ADC_VU, WM8993_ADC_VU);
1497
1498 /* Manualy manage the HPOUT sequencing for independent stereo
1499 * control. */
1500 snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
1501 WM8993_HPOUT1_AUTO_PU, 0);
1502
1503 /* Use automatic clock configuration */
1504 snd_soc_component_update_bits(component, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1505
1506 wm_hubs_handle_analogue_pdata(component, wm8993->pdata.lineout1_diff,
1507 wm8993->pdata.lineout2_diff,
1508 wm8993->pdata.lineout1fb,
1509 wm8993->pdata.lineout2fb,
1510 wm8993->pdata.jd_scthr,
1511 wm8993->pdata.jd_thr,
1512 wm8993->pdata.micbias1_delay,
1513 wm8993->pdata.micbias2_delay,
1514 wm8993->pdata.micbias1_lvl,
1515 wm8993->pdata.micbias2_lvl);
1516
1517 snd_soc_add_component_controls(component, wm8993_snd_controls,
1518 ARRAY_SIZE(wm8993_snd_controls));
1519 if (wm8993->pdata.num_retune_configs != 0) {
1520 dev_dbg(component->dev, "Using ReTune Mobile\n");
1521 } else {
1522 dev_dbg(component->dev, "No ReTune Mobile, using normal EQ\n");
1523 snd_soc_add_component_controls(component, wm8993_eq_controls,
1524 ARRAY_SIZE(wm8993_eq_controls));
1525 }
1526
1527 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1528 ARRAY_SIZE(wm8993_dapm_widgets));
1529 wm_hubs_add_analogue_controls(component);
1530
1531 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1532 wm_hubs_add_analogue_routes(component, wm8993->pdata.lineout1_diff,
1533 wm8993->pdata.lineout2_diff);
1534
1535 /* If the line outputs are differential then we aren't presenting
1536 * VMID as an output and can disable it.
1537 */
1538 if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
1539 dapm->idle_bias_off = 1;
1540
1541 return 0;
1542
1543 }
1544
1545 #ifdef CONFIG_PM
1546 static int wm8993_suspend(struct snd_soc_component *component)
1547 {
1548 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1549 int fll_fout = wm8993->fll_fout;
1550 int fll_fref = wm8993->fll_fref;
1551 int ret;
1552
1553 /* Stop the FLL in an orderly fashion */
1554 ret = _wm8993_set_fll(component, 0, 0, 0, 0);
1555 if (ret != 0) {
1556 dev_err(component->dev, "Failed to stop FLL\n");
1557 return ret;
1558 }
1559
1560 wm8993->fll_fout = fll_fout;
1561 wm8993->fll_fref = fll_fref;
1562
1563 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1564
1565 return 0;
1566 }
1567
1568 static int wm8993_resume(struct snd_soc_component *component)
1569 {
1570 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1571 int ret;
1572
1573 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1574
1575 /* Restart the FLL? */
1576 if (wm8993->fll_fout) {
1577 int fll_fout = wm8993->fll_fout;
1578 int fll_fref = wm8993->fll_fref;
1579
1580 wm8993->fll_fref = 0;
1581 wm8993->fll_fout = 0;
1582
1583 ret = _wm8993_set_fll(component, 0, wm8993->fll_src,
1584 fll_fref, fll_fout);
1585 if (ret != 0)
1586 dev_err(component->dev, "Failed to restart FLL\n");
1587 }
1588
1589 return 0;
1590 }
1591 #else
1592 #define wm8993_suspend NULL
1593 #define wm8993_resume NULL
1594 #endif
1595
1596 /* Tune DC servo configuration */
1597 static const struct reg_sequence wm8993_regmap_patch[] = {
1598 { 0x44, 3 },
1599 { 0x56, 3 },
1600 { 0x44, 0 },
1601 };
1602
1603 static const struct regmap_config wm8993_regmap = {
1604 .reg_bits = 8,
1605 .val_bits = 16,
1606
1607 .max_register = WM8993_MAX_REGISTER,
1608 .volatile_reg = wm8993_volatile,
1609 .readable_reg = wm8993_readable,
1610
1611 .cache_type = REGCACHE_MAPLE,
1612 .reg_defaults = wm8993_reg_defaults,
1613 .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
1614 };
1615
1616 static const struct snd_soc_component_driver soc_component_dev_wm8993 = {
1617 .probe = wm8993_probe,
1618 .suspend = wm8993_suspend,
1619 .resume = wm8993_resume,
1620 .set_bias_level = wm8993_set_bias_level,
1621 .idle_bias_on = 1,
1622 .use_pmdown_time = 1,
1623 .endianness = 1,
1624 };
1625
1626 static int wm8993_i2c_probe(struct i2c_client *i2c)
1627 {
1628 struct wm8993_priv *wm8993;
1629 unsigned int reg;
1630 int ret, i;
1631
1632 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1633 GFP_KERNEL);
1634 if (wm8993 == NULL)
1635 return -ENOMEM;
1636
1637 wm8993->dev = &i2c->dev;
1638 init_completion(&wm8993->fll_lock);
1639
1640 wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap);
1641 if (IS_ERR(wm8993->regmap)) {
1642 ret = PTR_ERR(wm8993->regmap);
1643 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1644 return ret;
1645 }
1646
1647 i2c_set_clientdata(i2c, wm8993);
1648
1649 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1650 wm8993->supplies[i].supply = wm8993_supply_names[i];
1651
1652 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
1653 wm8993->supplies);
1654 if (ret != 0) {
1655 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1656 return ret;
1657 }
1658
1659 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1660 wm8993->supplies);
1661 if (ret != 0) {
1662 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1663 return ret;
1664 }
1665
1666 ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®);
1667 if (ret != 0) {
1668 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1669 goto err_enable;
1670 }
1671
1672 if (reg != 0x8993) {
1673 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
1674 ret = -EINVAL;
1675 goto err_enable;
1676 }
1677
1678 ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
1679 if (ret != 0)
1680 goto err_enable;
1681
1682 ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
1683 ARRAY_SIZE(wm8993_regmap_patch));
1684 if (ret != 0)
1685 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
1686 ret);
1687
1688 if (i2c->irq) {
1689 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
1690 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
1691 WM8993_GPIO1_PD |
1692 WM8993_GPIO1_SEL_MASK, 7);
1693 if (ret != 0)
1694 goto err_enable;
1695
1696 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
1697 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1698 "wm8993", wm8993);
1699 if (ret != 0)
1700 goto err_enable;
1701
1702 }
1703
1704 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1705
1706 regcache_cache_only(wm8993->regmap, true);
1707
1708 ret = devm_snd_soc_register_component(&i2c->dev,
1709 &soc_component_dev_wm8993, &wm8993_dai, 1);
1710 if (ret != 0) {
1711 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1712 goto err_irq;
1713 }
1714
1715 return 0;
1716
1717 err_irq:
1718 if (i2c->irq)
1719 free_irq(i2c->irq, wm8993);
1720 err_enable:
1721 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1722 return ret;
1723 }
1724
1725 static void wm8993_i2c_remove(struct i2c_client *i2c)
1726 {
1727 struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
1728
1729 if (i2c->irq)
1730 free_irq(i2c->irq, wm8993);
1731 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1732 }
1733
1734 static const struct i2c_device_id wm8993_i2c_id[] = {
1735 { "wm8993" },
1736 { }
1737 };
1738 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1739
1740 static struct i2c_driver wm8993_i2c_driver = {
1741 .driver = {
1742 .name = "wm8993",
1743 },
1744 .probe = wm8993_i2c_probe,
1745 .remove = wm8993_i2c_remove,
1746 .id_table = wm8993_i2c_id,
1747 };
1748
1749 module_i2c_driver(wm8993_i2c_driver);
1750
1751 MODULE_DESCRIPTION("ASoC WM8993 driver");
1752 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1753 MODULE_LICENSE("GPL");
1754
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