1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
4 //
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/pinctrl/consumer.h>
13 #include <linux/pm_qos.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/time.h>
18 #include <sound/core.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
23
24 #include "fsl_sai.h"
25 #include "fsl_utils.h"
26 #include "imx-pcm.h"
27
28 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
29 FSL_SAI_CSR_FEIE)
30
31 static const unsigned int fsl_sai_rates[] = {
32 8000, 11025, 12000, 16000, 22050,
33 24000, 32000, 44100, 48000, 64000,
34 88200, 96000, 176400, 192000, 352800,
35 384000, 705600, 768000, 1411200, 2822400,
36 };
37
38 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
39 .count = ARRAY_SIZE(fsl_sai_rates),
40 .list = fsl_sai_rates,
41 };
42
43 /**
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
45 *
46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
47 * or Receiver's for both streams. This function is used to check if clocks of
48 * the stream's are synced by the opposite stream.
49 *
50 * @sai: SAI context
51 * @dir: stream direction
52 */
53 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
54 {
55 int adir = (dir == TX) ? RX : TX;
56
57 /* current dir in async mode while opposite dir in sync mode */
58 return !sai->synchronous[dir] && sai->synchronous[adir];
59 }
60
61 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
62 {
63 struct pinctrl_state *state = NULL;
64
65 if (sai->is_pdm_mode) {
66 /* DSD512@44.1kHz, DSD512@48kHz */
67 if (bclk >= 22579200)
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
69
70 /* Get default DSD state */
71 if (IS_ERR_OR_NULL(state))
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd");
73 } else {
74 /* 706k32b2c, 768k32b2c, etc */
75 if (bclk >= 45158400)
76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
77 }
78
79 /* Get default state */
80 if (IS_ERR_OR_NULL(state))
81 state = pinctrl_lookup_state(sai->pinctrl, "default");
82
83 return state;
84 }
85
86 static irqreturn_t fsl_sai_isr(int irq, void *devid)
87 {
88 struct fsl_sai *sai = (struct fsl_sai *)devid;
89 unsigned int ofs = sai->soc_data->reg_offset;
90 struct device *dev = &sai->pdev->dev;
91 u32 flags, xcsr, mask;
92 irqreturn_t iret = IRQ_NONE;
93
94 /*
95 * Both IRQ status bits and IRQ mask bits are in the xCSR but
96 * different shifts. And we here create a mask only for those
97 * IRQs that we activated.
98 */
99 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
100
101 /* Tx IRQ */
102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
103 flags = xcsr & mask;
104
105 if (flags)
106 iret = IRQ_HANDLED;
107 else
108 goto irq_rx;
109
110 if (flags & FSL_SAI_CSR_WSF)
111 dev_dbg(dev, "isr: Start of Tx word detected\n");
112
113 if (flags & FSL_SAI_CSR_SEF)
114 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
115
116 if (flags & FSL_SAI_CSR_FEF)
117 dev_dbg(dev, "isr: Transmit underrun detected\n");
118
119 if (flags & FSL_SAI_CSR_FWF)
120 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
121
122 if (flags & FSL_SAI_CSR_FRF)
123 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
124
125 flags &= FSL_SAI_CSR_xF_W_MASK;
126 xcsr &= ~FSL_SAI_CSR_xF_MASK;
127
128 if (flags)
129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
130
131 irq_rx:
132 /* Rx IRQ */
133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
134 flags = xcsr & mask;
135
136 if (flags)
137 iret = IRQ_HANDLED;
138 else
139 goto out;
140
141 if (flags & FSL_SAI_CSR_WSF)
142 dev_dbg(dev, "isr: Start of Rx word detected\n");
143
144 if (flags & FSL_SAI_CSR_SEF)
145 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
146
147 if (flags & FSL_SAI_CSR_FEF)
148 dev_dbg(dev, "isr: Receive overflow detected\n");
149
150 if (flags & FSL_SAI_CSR_FWF)
151 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
152
153 if (flags & FSL_SAI_CSR_FRF)
154 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
155
156 flags &= FSL_SAI_CSR_xF_W_MASK;
157 xcsr &= ~FSL_SAI_CSR_xF_MASK;
158
159 if (flags)
160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
161
162 out:
163 return iret;
164 }
165
166 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
167 u32 rx_mask, int slots, int slot_width)
168 {
169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
170
171 sai->slots = slots;
172 sai->slot_width = slot_width;
173
174 return 0;
175 }
176
177 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
178 unsigned int ratio)
179 {
180 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
181
182 sai->bclk_ratio = ratio;
183
184 return 0;
185 }
186
187 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
188 int clk_id, unsigned int freq, bool tx)
189 {
190 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
191 unsigned int ofs = sai->soc_data->reg_offset;
192 u32 val_cr2 = 0;
193
194 switch (clk_id) {
195 case FSL_SAI_CLK_BUS:
196 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
197 break;
198 case FSL_SAI_CLK_MAST1:
199 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
200 break;
201 case FSL_SAI_CLK_MAST2:
202 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
203 break;
204 case FSL_SAI_CLK_MAST3:
205 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
212 FSL_SAI_CR2_MSEL_MASK, val_cr2);
213
214 return 0;
215 }
216
217 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
218 {
219 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
220 int ret;
221
222 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
223 sai->pll8k_clk, sai->pll11k_clk, freq);
224
225 ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
226 if (ret < 0)
227 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
228
229 return ret;
230 }
231
232 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
233 int clk_id, unsigned int freq, int dir)
234 {
235 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
236 int ret;
237
238 if (dir == SND_SOC_CLOCK_IN)
239 return 0;
240
241 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) {
242 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
243 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
244 return -EINVAL;
245 }
246
247 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
248 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
249 return -EINVAL;
250 }
251
252 if (sai->mclk_streams == 0) {
253 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
254 if (ret < 0)
255 return ret;
256 }
257 }
258
259 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
260 if (ret) {
261 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
262 return ret;
263 }
264
265 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
266 if (ret)
267 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
268
269 return ret;
270 }
271
272 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
273 unsigned int fmt, bool tx)
274 {
275 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
276 unsigned int ofs = sai->soc_data->reg_offset;
277 u32 val_cr2 = 0, val_cr4 = 0;
278
279 if (!sai->is_lsb_first)
280 val_cr4 |= FSL_SAI_CR4_MF;
281
282 sai->is_pdm_mode = false;
283 sai->is_dsp_mode = false;
284 /* DAI mode */
285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
286 case SND_SOC_DAIFMT_I2S:
287 /*
288 * Frame low, 1clk before data, one word length for frame sync,
289 * frame sync starts one serial clock cycle earlier,
290 * that is, together with the last bit of the previous
291 * data word.
292 */
293 val_cr2 |= FSL_SAI_CR2_BCP;
294 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
295 break;
296 case SND_SOC_DAIFMT_LEFT_J:
297 /*
298 * Frame high, one word length for frame sync,
299 * frame sync asserts with the first bit of the frame.
300 */
301 val_cr2 |= FSL_SAI_CR2_BCP;
302 break;
303 case SND_SOC_DAIFMT_DSP_A:
304 /*
305 * Frame high, 1clk before data, one bit for frame sync,
306 * frame sync starts one serial clock cycle earlier,
307 * that is, together with the last bit of the previous
308 * data word.
309 */
310 val_cr2 |= FSL_SAI_CR2_BCP;
311 val_cr4 |= FSL_SAI_CR4_FSE;
312 sai->is_dsp_mode = true;
313 break;
314 case SND_SOC_DAIFMT_DSP_B:
315 /*
316 * Frame high, one bit for frame sync,
317 * frame sync asserts with the first bit of the frame.
318 */
319 val_cr2 |= FSL_SAI_CR2_BCP;
320 sai->is_dsp_mode = true;
321 break;
322 case SND_SOC_DAIFMT_PDM:
323 val_cr2 |= FSL_SAI_CR2_BCP;
324 val_cr4 &= ~FSL_SAI_CR4_MF;
325 sai->is_pdm_mode = true;
326 break;
327 case SND_SOC_DAIFMT_RIGHT_J:
328 /* To be done */
329 default:
330 return -EINVAL;
331 }
332
333 /* DAI clock inversion */
334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
335 case SND_SOC_DAIFMT_IB_IF:
336 /* Invert both clocks */
337 val_cr2 ^= FSL_SAI_CR2_BCP;
338 val_cr4 ^= FSL_SAI_CR4_FSP;
339 break;
340 case SND_SOC_DAIFMT_IB_NF:
341 /* Invert bit clock */
342 val_cr2 ^= FSL_SAI_CR2_BCP;
343 break;
344 case SND_SOC_DAIFMT_NB_IF:
345 /* Invert frame clock */
346 val_cr4 ^= FSL_SAI_CR4_FSP;
347 break;
348 case SND_SOC_DAIFMT_NB_NF:
349 /* Nothing to do for both normal cases */
350 break;
351 default:
352 return -EINVAL;
353 }
354
355 /* DAI clock provider masks */
356 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
357 case SND_SOC_DAIFMT_BP_FP:
358 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
359 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
360 sai->is_consumer_mode[tx] = false;
361 break;
362 case SND_SOC_DAIFMT_BC_FC:
363 sai->is_consumer_mode[tx] = true;
364 break;
365 case SND_SOC_DAIFMT_BP_FC:
366 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
367 sai->is_consumer_mode[tx] = false;
368 break;
369 case SND_SOC_DAIFMT_BC_FP:
370 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
371 sai->is_consumer_mode[tx] = true;
372 break;
373 default:
374 return -EINVAL;
375 }
376
377 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
378 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
379 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
380 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
381 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
382
383 return 0;
384 }
385
386 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
387 {
388 int ret;
389
390 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
391 if (ret) {
392 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
393 return ret;
394 }
395
396 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
397 if (ret)
398 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
399
400 return ret;
401 }
402
403 static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt)
404 {
405 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
406 }
407
408 static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt)
409 {
410 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
411 }
412
413 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
414 {
415 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
416 unsigned int reg, ofs = sai->soc_data->reg_offset;
417 unsigned long clk_rate;
418 u32 savediv = 0, ratio, bestdiff = freq;
419 int adir = tx ? RX : TX;
420 int dir = tx ? TX : RX;
421 u32 id;
422 bool support_1_1_ratio = sai->verid.version >= 0x0301;
423
424 /* Don't apply to consumer mode */
425 if (sai->is_consumer_mode[tx])
426 return 0;
427
428 /*
429 * There is no point in polling MCLK0 if it is identical to MCLK1.
430 * And given that MQS use case has to use MCLK1 though two clocks
431 * are the same, we simply skip MCLK0 and start to find from MCLK1.
432 */
433 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
434
435 for (; id < FSL_SAI_MCLK_MAX; id++) {
436 int diff;
437
438 clk_rate = clk_get_rate(sai->mclk_clk[id]);
439 if (!clk_rate)
440 continue;
441
442 ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
443 if (!ratio || ratio > 512)
444 continue;
445 if (ratio == 1 && !support_1_1_ratio)
446 continue;
447 if ((ratio & 1) && ratio > 1)
448 continue;
449
450 diff = abs((long)clk_rate - ratio * freq);
451
452 /*
453 * Drop the source that can not be
454 * divided into the required rate.
455 */
456 if (diff != 0 && clk_rate / diff < 1000)
457 continue;
458
459 dev_dbg(dai->dev,
460 "ratio %d for freq %dHz based on clock %ldHz\n",
461 ratio, freq, clk_rate);
462
463
464 if (diff < bestdiff) {
465 savediv = ratio;
466 sai->mclk_id[tx] = id;
467 bestdiff = diff;
468 }
469
470 if (diff == 0)
471 break;
472 }
473
474 if (savediv == 0) {
475 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
476 tx ? 'T' : 'R', freq);
477 return -EINVAL;
478 }
479
480 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
481 sai->mclk_id[tx], savediv, bestdiff);
482
483 /*
484 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
485 * set TCR2 register for playback.
486 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
487 * and capture.
488 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
489 * and capture.
490 * 4) For Tx and Rx are both Synchronous with another SAI, we just
491 * ignore it.
492 */
493 if (fsl_sai_dir_is_synced(sai, adir))
494 reg = FSL_SAI_xCR2(!tx, ofs);
495 else if (!sai->synchronous[dir])
496 reg = FSL_SAI_xCR2(tx, ofs);
497 else
498 return 0;
499
500 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
501 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
502
503 if (savediv == 1) {
504 regmap_update_bits(sai->regmap, reg,
505 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
506 FSL_SAI_CR2_BYP);
507 if (fsl_sai_dir_is_synced(sai, adir))
508 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
509 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
510 else
511 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
512 FSL_SAI_CR2_BCI, 0);
513 } else {
514 regmap_update_bits(sai->regmap, reg,
515 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
516 savediv / 2 - 1);
517 }
518
519 return 0;
520 }
521
522 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
523 struct snd_pcm_hw_params *params,
524 struct snd_soc_dai *cpu_dai)
525 {
526 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
527 unsigned int ofs = sai->soc_data->reg_offset;
528 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
529 unsigned int channels = params_channels(params);
530 struct snd_dmaengine_dai_dma_data *dma_params;
531 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
532 u32 word_width = params_width(params);
533 int trce_mask = 0, dl_cfg_idx = 0;
534 int dl_cfg_cnt = sai->dl_cfg_cnt;
535 u32 dl_type = FSL_SAI_DL_I2S;
536 u32 val_cr4 = 0, val_cr5 = 0;
537 u32 slots = (channels == 1) ? 2 : channels;
538 u32 slot_width = word_width;
539 int adir = tx ? RX : TX;
540 u32 pins, bclk;
541 u32 watermark;
542 int ret, i;
543
544 if (sai->slot_width)
545 slot_width = sai->slot_width;
546
547 if (sai->slots)
548 slots = sai->slots;
549 else if (sai->bclk_ratio)
550 slots = sai->bclk_ratio / slot_width;
551
552 pins = DIV_ROUND_UP(channels, slots);
553
554 /*
555 * PDM mode, channels are independent
556 * each channels are on one dataline/FIFO.
557 */
558 if (sai->is_pdm_mode) {
559 pins = channels;
560 dl_type = FSL_SAI_DL_PDM;
561 }
562
563 for (i = 0; i < dl_cfg_cnt; i++) {
564 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
565 dl_cfg_idx = i;
566 break;
567 }
568 }
569
570 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
571 dev_err(cpu_dai->dev, "channel not supported\n");
572 return -EINVAL;
573 }
574
575 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
576
577 if (!IS_ERR_OR_NULL(sai->pinctrl)) {
578 sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
579 if (!IS_ERR_OR_NULL(sai->pins_state)) {
580 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
581 if (ret) {
582 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
583 return ret;
584 }
585 }
586 }
587
588 if (!sai->is_consumer_mode[tx]) {
589 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
590 if (ret)
591 return ret;
592
593 /* Do not enable the clock if it is already enabled */
594 if (!(sai->mclk_streams & BIT(substream->stream))) {
595 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
596 if (ret)
597 return ret;
598
599 sai->mclk_streams |= BIT(substream->stream);
600 }
601 }
602
603 if (!sai->is_dsp_mode && !sai->is_pdm_mode)
604 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
605
606 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
607 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
608
609 if (sai->is_lsb_first || sai->is_pdm_mode)
610 val_cr5 |= FSL_SAI_CR5_FBT(0);
611 else
612 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
613
614 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
615
616 /* Set to output mode to avoid tri-stated data pins */
617 if (tx)
618 val_cr4 |= FSL_SAI_CR4_CHMOD;
619
620 /*
621 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
622 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
623 * RCR5(TCR5) for playback(capture), or there will be sync error.
624 */
625
626 if (!sai->is_consumer_mode[tx] && fsl_sai_dir_is_synced(sai, adir)) {
627 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
628 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
629 FSL_SAI_CR4_CHMOD_MASK,
630 val_cr4);
631 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
632 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
633 FSL_SAI_CR5_FBT_MASK, val_cr5);
634 }
635
636 /*
637 * Combine mode has limation:
638 * - Can't used for singel dataline/FIFO case except the FIFO0
639 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
640 * are successive and start from FIFO0
641 *
642 * So for common usage, all multi fifo case disable the combine mode.
643 */
644 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
645 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
646 FSL_SAI_CR4_FCOMB_MASK, 0);
647 else
648 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
649 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
650
651 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
652 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
653 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
654
655 if (sai->is_multi_fifo_dma) {
656 sai->audio_config[tx].words_per_fifo = min(slots, channels);
657 if (tx) {
658 sai->audio_config[tx].n_fifos_dst = pins;
659 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
660 } else {
661 sai->audio_config[tx].n_fifos_src = pins;
662 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
663 }
664 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
665 dma_params->peripheral_config = &sai->audio_config[tx];
666 dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
667
668 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
669 (dma_params->maxburst - 1);
670 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
671 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
672 watermark);
673 }
674
675 /* Find a proper tcre setting */
676 for (i = 0; i < sai->soc_data->pins; i++) {
677 trce_mask = (1 << (i + 1)) - 1;
678 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
679 break;
680 }
681
682 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
683 FSL_SAI_CR3_TRCE_MASK,
684 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
685
686 /*
687 * When the TERE and FSD_MSTR enabled before configuring the word width
688 * There will be no frame sync clock issue, because word width impact
689 * the generation of frame sync clock.
690 *
691 * TERE enabled earlier only for i.MX8MP case for the hardware limitation,
692 * We need to disable FSD_MSTR before configuring word width, then enable
693 * FSD_MSTR bit for this specific case.
694 */
695 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
696 !sai->is_consumer_mode[tx])
697 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
698 FSL_SAI_CR4_FSD_MSTR, 0);
699
700 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
701 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
702 FSL_SAI_CR4_CHMOD_MASK,
703 val_cr4);
704 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
705 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
706 FSL_SAI_CR5_FBT_MASK, val_cr5);
707
708 /* Enable FSD_MSTR after configuring word width */
709 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
710 !sai->is_consumer_mode[tx])
711 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
712 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR);
713
714 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
715 ~0UL - ((1 << min(channels, slots)) - 1));
716
717 return 0;
718 }
719
720 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
721 struct snd_soc_dai *cpu_dai)
722 {
723 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
724 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
725 unsigned int ofs = sai->soc_data->reg_offset;
726
727 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */
728 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0);
729
730 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
731 FSL_SAI_CR3_TRCE_MASK, 0);
732
733 if (!sai->is_consumer_mode[tx] &&
734 sai->mclk_streams & BIT(substream->stream)) {
735 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
736 sai->mclk_streams &= ~BIT(substream->stream);
737 }
738
739 return 0;
740 }
741
742 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
743 {
744 unsigned int ofs = sai->soc_data->reg_offset;
745 bool tx = dir == TX;
746 u32 xcsr, count = 100, mask;
747
748 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
749 mask = FSL_SAI_CSR_TERE;
750 else
751 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
752
753 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
754 mask, 0);
755
756 /* TERE will remain set till the end of current frame */
757 do {
758 udelay(10);
759 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
760 } while (--count && xcsr & FSL_SAI_CSR_TERE);
761
762 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
763 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
764
765 /*
766 * For sai master mode, after several open/close sai,
767 * there will be no frame clock, and can't recover
768 * anymore. Add software reset to fix this issue.
769 * This is a hardware bug, and will be fix in the
770 * next sai version.
771 */
772 if (!sai->is_consumer_mode[tx]) {
773 /* Software Reset */
774 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
775 /* Clear SR bit to finish the reset */
776 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
777 }
778 }
779
780 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
781 struct snd_soc_dai *cpu_dai)
782 {
783 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
784 unsigned int ofs = sai->soc_data->reg_offset;
785
786 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
787 int adir = tx ? RX : TX;
788 int dir = tx ? TX : RX;
789 u32 xcsr;
790
791 /*
792 * Asynchronous mode: Clear SYNC for both Tx and Rx.
793 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
794 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
795 */
796 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
797 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
798 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
799 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
800
801 /*
802 * It is recommended that the transmitter is the last enabled
803 * and the first disabled.
804 */
805 switch (cmd) {
806 case SNDRV_PCM_TRIGGER_START:
807 case SNDRV_PCM_TRIGGER_RESUME:
808 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
809 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
810 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
811
812 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
813 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
814 /*
815 * Enable the opposite direction for synchronous mode
816 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
817 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
818 *
819 * RM recommends to enable RE after TE for case 1 and to enable
820 * TE after RE for case 2, but we here may not always guarantee
821 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
822 * TE after RE, which is against what RM recommends but should
823 * be safe to do, judging by years of testing results.
824 */
825 if (fsl_sai_dir_is_synced(sai, adir))
826 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
827 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
828
829 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
830 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
831 break;
832 case SNDRV_PCM_TRIGGER_STOP:
833 case SNDRV_PCM_TRIGGER_SUSPEND:
834 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
835 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
836 FSL_SAI_CSR_FRDE, 0);
837 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
838 FSL_SAI_CSR_xIE_MASK, 0);
839
840 /* Check if the opposite FRDE is also disabled */
841 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
842
843 /*
844 * If opposite stream provides clocks for synchronous mode and
845 * it is inactive, disable it before disabling the current one
846 */
847 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
848 fsl_sai_config_disable(sai, adir);
849
850 /*
851 * Disable current stream if either of:
852 * 1. current stream doesn't provide clocks for synchronous mode
853 * 2. current stream provides clocks for synchronous mode but no
854 * more stream is active.
855 */
856 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
857 fsl_sai_config_disable(sai, dir);
858
859 break;
860 default:
861 return -EINVAL;
862 }
863
864 return 0;
865 }
866
867 static int fsl_sai_startup(struct snd_pcm_substream *substream,
868 struct snd_soc_dai *cpu_dai)
869 {
870 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
871 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
872 int ret;
873
874 /*
875 * EDMA controller needs period size to be a multiple of
876 * tx/rx maxburst
877 */
878 if (sai->soc_data->use_edma)
879 snd_pcm_hw_constraint_step(substream->runtime, 0,
880 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
881 tx ? sai->dma_params_tx.maxburst :
882 sai->dma_params_rx.maxburst);
883
884 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
885 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
886
887 return ret;
888 }
889
890 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
891 {
892 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
893 unsigned int ofs = sai->soc_data->reg_offset;
894
895 /* Software Reset for both Tx and Rx */
896 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
897 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
898 /* Clear SR bit to finish the reset */
899 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
900 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
901
902 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
903 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
904 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
905 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
906 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
907 sai->dma_params_rx.maxburst - 1);
908
909 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
910 &sai->dma_params_rx);
911
912 return 0;
913 }
914
915 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
916 .probe = fsl_sai_dai_probe,
917 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
918 .set_sysclk = fsl_sai_set_dai_sysclk,
919 .set_fmt = fsl_sai_set_dai_fmt,
920 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
921 .hw_params = fsl_sai_hw_params,
922 .hw_free = fsl_sai_hw_free,
923 .trigger = fsl_sai_trigger,
924 .startup = fsl_sai_startup,
925 };
926
927 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = {
928 .probe = fsl_sai_dai_probe,
929 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
930 .set_sysclk = fsl_sai_set_dai_sysclk,
931 .set_fmt = fsl_sai_set_dai_fmt_tx,
932 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
933 .hw_params = fsl_sai_hw_params,
934 .hw_free = fsl_sai_hw_free,
935 .trigger = fsl_sai_trigger,
936 .startup = fsl_sai_startup,
937 };
938
939 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = {
940 .probe = fsl_sai_dai_probe,
941 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
942 .set_sysclk = fsl_sai_set_dai_sysclk,
943 .set_fmt = fsl_sai_set_dai_fmt_rx,
944 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
945 .hw_params = fsl_sai_hw_params,
946 .hw_free = fsl_sai_hw_free,
947 .trigger = fsl_sai_trigger,
948 .startup = fsl_sai_startup,
949 };
950
951 static int fsl_sai_dai_resume(struct snd_soc_component *component)
952 {
953 struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
954 struct device *dev = &sai->pdev->dev;
955 int ret;
956
957 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
958 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
959 if (ret) {
960 dev_err(dev, "failed to set proper pins state: %d\n", ret);
961 return ret;
962 }
963 }
964
965 return 0;
966 }
967
968 static struct snd_soc_dai_driver fsl_sai_dai_template[] = {
969 {
970 .name = "sai-tx-rx",
971 .playback = {
972 .stream_name = "CPU-Playback",
973 .channels_min = 1,
974 .channels_max = 32,
975 .rate_min = 8000,
976 .rate_max = 2822400,
977 .rates = SNDRV_PCM_RATE_KNOT,
978 .formats = FSL_SAI_FORMATS,
979 },
980 .capture = {
981 .stream_name = "CPU-Capture",
982 .channels_min = 1,
983 .channels_max = 32,
984 .rate_min = 8000,
985 .rate_max = 2822400,
986 .rates = SNDRV_PCM_RATE_KNOT,
987 .formats = FSL_SAI_FORMATS,
988 },
989 .ops = &fsl_sai_pcm_dai_ops,
990 },
991 {
992 .name = "sai-tx",
993 .playback = {
994 .stream_name = "CPU-Playback",
995 .channels_min = 1,
996 .channels_max = 32,
997 .rate_min = 8000,
998 .rate_max = 2822400,
999 .rates = SNDRV_PCM_RATE_KNOT,
1000 .formats = FSL_SAI_FORMATS,
1001 },
1002 .ops = &fsl_sai_pcm_dai_tx_ops,
1003 },
1004 {
1005 .name = "sai-rx",
1006 .capture = {
1007 .stream_name = "CPU-Capture",
1008 .channels_min = 1,
1009 .channels_max = 32,
1010 .rate_min = 8000,
1011 .rate_max = 2822400,
1012 .rates = SNDRV_PCM_RATE_KNOT,
1013 .formats = FSL_SAI_FORMATS,
1014 },
1015 .ops = &fsl_sai_pcm_dai_rx_ops,
1016 },
1017 };
1018
1019 static const struct snd_soc_component_driver fsl_component = {
1020 .name = "fsl-sai",
1021 .resume = fsl_sai_dai_resume,
1022 .legacy_dai_naming = 1,
1023 };
1024
1025 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
1026 {FSL_SAI_TCR1(0), 0},
1027 {FSL_SAI_TCR2(0), 0},
1028 {FSL_SAI_TCR3(0), 0},
1029 {FSL_SAI_TCR4(0), 0},
1030 {FSL_SAI_TCR5(0), 0},
1031 {FSL_SAI_TDR0, 0},
1032 {FSL_SAI_TDR1, 0},
1033 {FSL_SAI_TDR2, 0},
1034 {FSL_SAI_TDR3, 0},
1035 {FSL_SAI_TDR4, 0},
1036 {FSL_SAI_TDR5, 0},
1037 {FSL_SAI_TDR6, 0},
1038 {FSL_SAI_TDR7, 0},
1039 {FSL_SAI_TMR, 0},
1040 {FSL_SAI_RCR1(0), 0},
1041 {FSL_SAI_RCR2(0), 0},
1042 {FSL_SAI_RCR3(0), 0},
1043 {FSL_SAI_RCR4(0), 0},
1044 {FSL_SAI_RCR5(0), 0},
1045 {FSL_SAI_RMR, 0},
1046 };
1047
1048 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
1049 {FSL_SAI_TCR1(8), 0},
1050 {FSL_SAI_TCR2(8), 0},
1051 {FSL_SAI_TCR3(8), 0},
1052 {FSL_SAI_TCR4(8), 0},
1053 {FSL_SAI_TCR5(8), 0},
1054 {FSL_SAI_TDR0, 0},
1055 {FSL_SAI_TDR1, 0},
1056 {FSL_SAI_TDR2, 0},
1057 {FSL_SAI_TDR3, 0},
1058 {FSL_SAI_TDR4, 0},
1059 {FSL_SAI_TDR5, 0},
1060 {FSL_SAI_TDR6, 0},
1061 {FSL_SAI_TDR7, 0},
1062 {FSL_SAI_TMR, 0},
1063 {FSL_SAI_RCR1(8), 0},
1064 {FSL_SAI_RCR2(8), 0},
1065 {FSL_SAI_RCR3(8), 0},
1066 {FSL_SAI_RCR4(8), 0},
1067 {FSL_SAI_RCR5(8), 0},
1068 {FSL_SAI_RMR, 0},
1069 {FSL_SAI_MCTL, 0},
1070 {FSL_SAI_MDIV, 0},
1071 };
1072
1073 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
1074 {
1075 struct fsl_sai *sai = dev_get_drvdata(dev);
1076 unsigned int ofs = sai->soc_data->reg_offset;
1077
1078 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1079 return true;
1080
1081 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1082 return true;
1083
1084 switch (reg) {
1085 case FSL_SAI_TFR0:
1086 case FSL_SAI_TFR1:
1087 case FSL_SAI_TFR2:
1088 case FSL_SAI_TFR3:
1089 case FSL_SAI_TFR4:
1090 case FSL_SAI_TFR5:
1091 case FSL_SAI_TFR6:
1092 case FSL_SAI_TFR7:
1093 case FSL_SAI_TMR:
1094 case FSL_SAI_RDR0:
1095 case FSL_SAI_RDR1:
1096 case FSL_SAI_RDR2:
1097 case FSL_SAI_RDR3:
1098 case FSL_SAI_RDR4:
1099 case FSL_SAI_RDR5:
1100 case FSL_SAI_RDR6:
1101 case FSL_SAI_RDR7:
1102 case FSL_SAI_RFR0:
1103 case FSL_SAI_RFR1:
1104 case FSL_SAI_RFR2:
1105 case FSL_SAI_RFR3:
1106 case FSL_SAI_RFR4:
1107 case FSL_SAI_RFR5:
1108 case FSL_SAI_RFR6:
1109 case FSL_SAI_RFR7:
1110 case FSL_SAI_RMR:
1111 case FSL_SAI_MCTL:
1112 case FSL_SAI_MDIV:
1113 case FSL_SAI_VERID:
1114 case FSL_SAI_PARAM:
1115 case FSL_SAI_TTCTN:
1116 case FSL_SAI_RTCTN:
1117 case FSL_SAI_TTCTL:
1118 case FSL_SAI_TBCTN:
1119 case FSL_SAI_TTCAP:
1120 case FSL_SAI_RTCTL:
1121 case FSL_SAI_RBCTN:
1122 case FSL_SAI_RTCAP:
1123 return true;
1124 default:
1125 return false;
1126 }
1127 }
1128
1129 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
1130 {
1131 struct fsl_sai *sai = dev_get_drvdata(dev);
1132 unsigned int ofs = sai->soc_data->reg_offset;
1133
1134 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
1135 return true;
1136
1137 /* Set VERID and PARAM be volatile for reading value in probe */
1138 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
1139 return true;
1140
1141 switch (reg) {
1142 case FSL_SAI_TFR0:
1143 case FSL_SAI_TFR1:
1144 case FSL_SAI_TFR2:
1145 case FSL_SAI_TFR3:
1146 case FSL_SAI_TFR4:
1147 case FSL_SAI_TFR5:
1148 case FSL_SAI_TFR6:
1149 case FSL_SAI_TFR7:
1150 case FSL_SAI_RFR0:
1151 case FSL_SAI_RFR1:
1152 case FSL_SAI_RFR2:
1153 case FSL_SAI_RFR3:
1154 case FSL_SAI_RFR4:
1155 case FSL_SAI_RFR5:
1156 case FSL_SAI_RFR6:
1157 case FSL_SAI_RFR7:
1158 case FSL_SAI_RDR0:
1159 case FSL_SAI_RDR1:
1160 case FSL_SAI_RDR2:
1161 case FSL_SAI_RDR3:
1162 case FSL_SAI_RDR4:
1163 case FSL_SAI_RDR5:
1164 case FSL_SAI_RDR6:
1165 case FSL_SAI_RDR7:
1166 return true;
1167 default:
1168 return false;
1169 }
1170 }
1171
1172 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
1173 {
1174 struct fsl_sai *sai = dev_get_drvdata(dev);
1175 unsigned int ofs = sai->soc_data->reg_offset;
1176
1177 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1178 return true;
1179
1180 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1181 return true;
1182
1183 switch (reg) {
1184 case FSL_SAI_TDR0:
1185 case FSL_SAI_TDR1:
1186 case FSL_SAI_TDR2:
1187 case FSL_SAI_TDR3:
1188 case FSL_SAI_TDR4:
1189 case FSL_SAI_TDR5:
1190 case FSL_SAI_TDR6:
1191 case FSL_SAI_TDR7:
1192 case FSL_SAI_TMR:
1193 case FSL_SAI_RMR:
1194 case FSL_SAI_MCTL:
1195 case FSL_SAI_MDIV:
1196 case FSL_SAI_TTCTL:
1197 case FSL_SAI_RTCTL:
1198 return true;
1199 default:
1200 return false;
1201 }
1202 }
1203
1204 static struct regmap_config fsl_sai_regmap_config = {
1205 .reg_bits = 32,
1206 .reg_stride = 4,
1207 .val_bits = 32,
1208 .fast_io = true,
1209
1210 .max_register = FSL_SAI_RMR,
1211 .reg_defaults = fsl_sai_reg_defaults_ofs0,
1212 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
1213 .readable_reg = fsl_sai_readable_reg,
1214 .volatile_reg = fsl_sai_volatile_reg,
1215 .writeable_reg = fsl_sai_writeable_reg,
1216 .cache_type = REGCACHE_FLAT,
1217 };
1218
1219 static int fsl_sai_check_version(struct device *dev)
1220 {
1221 struct fsl_sai *sai = dev_get_drvdata(dev);
1222 unsigned char ofs = sai->soc_data->reg_offset;
1223 unsigned int val;
1224 int ret;
1225
1226 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
1227 return 0;
1228
1229 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1230 if (ret < 0)
1231 return ret;
1232
1233 dev_dbg(dev, "VERID: 0x%016X\n", val);
1234
1235 sai->verid.version = val &
1236 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
1237 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1238 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1239
1240 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1241 if (ret < 0)
1242 return ret;
1243
1244 dev_dbg(dev, "PARAM: 0x%016X\n", val);
1245
1246 /* Max slots per frame, power of 2 */
1247 sai->param.slot_num = 1 <<
1248 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
1249
1250 /* Words per fifo, power of 2 */
1251 sai->param.fifo_depth = 1 <<
1252 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
1253
1254 /* Number of datalines implemented */
1255 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1256
1257 return 0;
1258 }
1259
1260 /*
1261 * Calculate the offset between first two datalines, don't
1262 * different offset in one case.
1263 */
1264 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
1265 {
1266 int fbidx, nbidx, offset;
1267
1268 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1269 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
1270 offset = nbidx - fbidx - 1;
1271
1272 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1273 }
1274
1275 /*
1276 * read the fsl,dataline property from dts file.
1277 * It has 3 value for each configuration, first one means the type:
1278 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
1279 * dataline mask for 'tx'. for example
1280 *
1281 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
1282 *
1283 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1284 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1285 *
1286 */
1287 static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
1288 {
1289 struct platform_device *pdev = sai->pdev;
1290 struct device_node *np = pdev->dev.of_node;
1291 struct device *dev = &pdev->dev;
1292 int ret, elems, i, index, num_cfg;
1293 char *propname = "fsl,dataline";
1294 struct fsl_sai_dl_cfg *cfg;
1295 unsigned long dl_mask;
1296 unsigned int soc_dl;
1297 u32 rx, tx, type;
1298
1299 elems = of_property_count_u32_elems(np, propname);
1300
1301 if (elems <= 0) {
1302 elems = 0;
1303 } else if (elems % 3) {
1304 dev_err(dev, "Number of elements must be divisible to 3.\n");
1305 return -EINVAL;
1306 }
1307
1308 num_cfg = elems / 3;
1309 /* Add one more for default value */
1310 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
1311 if (!cfg)
1312 return -ENOMEM;
1313
1314 /* Consider default value "0 0xFF 0xFF" if property is missing */
1315 soc_dl = BIT(sai->soc_data->pins) - 1;
1316 cfg[0].type = FSL_SAI_DL_DEFAULT;
1317 cfg[0].pins[0] = sai->soc_data->pins;
1318 cfg[0].mask[0] = soc_dl;
1319 cfg[0].start_off[0] = 0;
1320 cfg[0].next_off[0] = 0;
1321
1322 cfg[0].pins[1] = sai->soc_data->pins;
1323 cfg[0].mask[1] = soc_dl;
1324 cfg[0].start_off[1] = 0;
1325 cfg[0].next_off[1] = 0;
1326 for (i = 1, index = 0; i < num_cfg + 1; i++) {
1327 /*
1328 * type of dataline
1329 * 0 means default mode
1330 * 1 means I2S mode
1331 * 2 means PDM mode
1332 */
1333 ret = of_property_read_u32_index(np, propname, index++, &type);
1334 if (ret)
1335 return -EINVAL;
1336
1337 ret = of_property_read_u32_index(np, propname, index++, &rx);
1338 if (ret)
1339 return -EINVAL;
1340
1341 ret = of_property_read_u32_index(np, propname, index++, &tx);
1342 if (ret)
1343 return -EINVAL;
1344
1345 if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
1346 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
1347 return -EINVAL;
1348 }
1349
1350 rx = rx & soc_dl;
1351 tx = tx & soc_dl;
1352
1353 cfg[i].type = type;
1354 cfg[i].pins[0] = hweight8(rx);
1355 cfg[i].mask[0] = rx;
1356 dl_mask = rx;
1357 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1358 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
1359
1360 cfg[i].pins[1] = hweight8(tx);
1361 cfg[i].mask[1] = tx;
1362 dl_mask = tx;
1363 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1364 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
1365 }
1366
1367 sai->dl_cfg = cfg;
1368 sai->dl_cfg_cnt = num_cfg + 1;
1369 return 0;
1370 }
1371
1372 static int fsl_sai_runtime_suspend(struct device *dev);
1373 static int fsl_sai_runtime_resume(struct device *dev);
1374
1375 static int fsl_sai_probe(struct platform_device *pdev)
1376 {
1377 struct device_node *np = pdev->dev.of_node;
1378 struct device *dev = &pdev->dev;
1379 struct fsl_sai *sai;
1380 struct regmap *gpr;
1381 void __iomem *base;
1382 char tmp[8];
1383 int irq, ret, i;
1384 int index;
1385 u32 dmas[4];
1386
1387 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
1388 if (!sai)
1389 return -ENOMEM;
1390
1391 sai->pdev = pdev;
1392 sai->soc_data = of_device_get_match_data(dev);
1393
1394 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1395
1396 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1397 if (IS_ERR(base))
1398 return PTR_ERR(base);
1399
1400 if (sai->soc_data->reg_offset == 8) {
1401 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1402 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1403 fsl_sai_regmap_config.num_reg_defaults =
1404 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1405 }
1406
1407 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1408 if (IS_ERR(sai->regmap)) {
1409 dev_err(dev, "regmap init failed\n");
1410 return PTR_ERR(sai->regmap);
1411 }
1412
1413 sai->bus_clk = devm_clk_get(dev, "bus");
1414 /* Compatible with old DTB cases */
1415 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1416 sai->bus_clk = devm_clk_get(dev, "sai");
1417 if (IS_ERR(sai->bus_clk)) {
1418 dev_err(dev, "failed to get bus clock: %ld\n",
1419 PTR_ERR(sai->bus_clk));
1420 /* -EPROBE_DEFER */
1421 return PTR_ERR(sai->bus_clk);
1422 }
1423
1424 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1425 sprintf(tmp, "mclk%d", i);
1426 sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1427 if (IS_ERR(sai->mclk_clk[i])) {
1428 dev_err(dev, "failed to get mclk%d clock: %ld\n",
1429 i, PTR_ERR(sai->mclk_clk[i]));
1430 sai->mclk_clk[i] = NULL;
1431 }
1432 }
1433
1434 if (sai->soc_data->mclk0_is_mclk1)
1435 sai->mclk_clk[0] = sai->mclk_clk[1];
1436 else
1437 sai->mclk_clk[0] = sai->bus_clk;
1438
1439 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1440 &sai->pll11k_clk);
1441
1442 /* Use Multi FIFO mode depending on the support from SDMA script */
1443 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1444 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1445 sai->is_multi_fifo_dma = true;
1446
1447 /* read dataline mask for rx and tx*/
1448 ret = fsl_sai_read_dlcfg(sai);
1449 if (ret < 0) {
1450 dev_err(dev, "failed to read dlcfg %d\n", ret);
1451 return ret;
1452 }
1453
1454 irq = platform_get_irq(pdev, 0);
1455 if (irq < 0)
1456 return irq;
1457
1458 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
1459 np->name, sai);
1460 if (ret) {
1461 dev_err(dev, "failed to claim irq %u\n", irq);
1462 return ret;
1463 }
1464
1465 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template,
1466 sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template));
1467
1468 /* Sync Tx with Rx as default by following old DT binding */
1469 sai->synchronous[RX] = true;
1470 sai->synchronous[TX] = false;
1471 sai->cpu_dai_drv[0].symmetric_rate = 1;
1472 sai->cpu_dai_drv[0].symmetric_channels = 1;
1473 sai->cpu_dai_drv[0].symmetric_sample_bits = 1;
1474
1475 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1476 of_property_read_bool(np, "fsl,sai-asynchronous")) {
1477 /* error out if both synchronous and asynchronous are present */
1478 dev_err(dev, "invalid binding for synchronous mode\n");
1479 return -EINVAL;
1480 }
1481
1482 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1483 /* Sync Rx with Tx */
1484 sai->synchronous[RX] = false;
1485 sai->synchronous[TX] = true;
1486 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1487 /* Discard all settings for asynchronous mode */
1488 sai->synchronous[RX] = false;
1489 sai->synchronous[TX] = false;
1490 sai->cpu_dai_drv[0].symmetric_rate = 0;
1491 sai->cpu_dai_drv[0].symmetric_channels = 0;
1492 sai->cpu_dai_drv[0].symmetric_sample_bits = 0;
1493 }
1494
1495 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1496
1497 if (sai->mclk_direction_output &&
1498 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1499 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1500 if (IS_ERR(gpr)) {
1501 dev_err(dev, "cannot find iomuxc registers\n");
1502 return PTR_ERR(gpr);
1503 }
1504
1505 index = of_alias_get_id(np, "sai");
1506 if (index < 0)
1507 return index;
1508
1509 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1510 MCLK_DIR(index));
1511 }
1512
1513 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1514 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1515 sai->dma_params_rx.maxburst =
1516 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1517 sai->dma_params_tx.maxburst =
1518 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1519
1520 sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1521
1522 platform_set_drvdata(pdev, sai);
1523 pm_runtime_enable(dev);
1524 if (!pm_runtime_enabled(dev)) {
1525 ret = fsl_sai_runtime_resume(dev);
1526 if (ret)
1527 goto err_pm_disable;
1528 }
1529
1530 ret = pm_runtime_resume_and_get(dev);
1531 if (ret < 0)
1532 goto err_pm_get_sync;
1533
1534 /* Get sai version */
1535 ret = fsl_sai_check_version(dev);
1536 if (ret < 0)
1537 dev_warn(dev, "Error reading SAI version: %d\n", ret);
1538
1539 /* Select MCLK direction */
1540 if (sai->mclk_direction_output &&
1541 sai->soc_data->max_register >= FSL_SAI_MCTL) {
1542 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1543 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1544 }
1545
1546 ret = pm_runtime_put_sync(dev);
1547 if (ret < 0 && ret != -ENOSYS)
1548 goto err_pm_get_sync;
1549
1550 /*
1551 * Register platform component before registering cpu dai for there
1552 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1553 */
1554 if (sai->soc_data->use_imx_pcm) {
1555 ret = imx_pcm_dma_init(pdev);
1556 if (ret) {
1557 dev_err_probe(dev, ret, "PCM DMA init failed\n");
1558 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
1559 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1560 goto err_pm_get_sync;
1561 }
1562 } else {
1563 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1564 if (ret) {
1565 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
1566 goto err_pm_get_sync;
1567 }
1568 }
1569
1570 ret = devm_snd_soc_register_component(dev, &fsl_component,
1571 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template));
1572 if (ret)
1573 goto err_pm_get_sync;
1574
1575 return ret;
1576
1577 err_pm_get_sync:
1578 if (!pm_runtime_status_suspended(dev))
1579 fsl_sai_runtime_suspend(dev);
1580 err_pm_disable:
1581 pm_runtime_disable(dev);
1582
1583 return ret;
1584 }
1585
1586 static void fsl_sai_remove(struct platform_device *pdev)
1587 {
1588 pm_runtime_disable(&pdev->dev);
1589 if (!pm_runtime_status_suspended(&pdev->dev))
1590 fsl_sai_runtime_suspend(&pdev->dev);
1591 }
1592
1593 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1594 .use_imx_pcm = false,
1595 .use_edma = false,
1596 .fifo_depth = 32,
1597 .pins = 1,
1598 .reg_offset = 0,
1599 .mclk0_is_mclk1 = false,
1600 .flags = 0,
1601 .max_register = FSL_SAI_RMR,
1602 };
1603
1604 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1605 .use_imx_pcm = true,
1606 .use_edma = false,
1607 .fifo_depth = 32,
1608 .pins = 1,
1609 .reg_offset = 0,
1610 .mclk0_is_mclk1 = true,
1611 .flags = 0,
1612 .max_register = FSL_SAI_RMR,
1613 };
1614
1615 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1616 .use_imx_pcm = true,
1617 .use_edma = false,
1618 .fifo_depth = 16,
1619 .pins = 2,
1620 .reg_offset = 8,
1621 .mclk0_is_mclk1 = false,
1622 .flags = PMQOS_CPU_LATENCY,
1623 .max_register = FSL_SAI_RMR,
1624 };
1625
1626 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1627 .use_imx_pcm = true,
1628 .use_edma = false,
1629 .fifo_depth = 128,
1630 .pins = 8,
1631 .reg_offset = 8,
1632 .mclk0_is_mclk1 = false,
1633 .flags = 0,
1634 .max_register = FSL_SAI_RMR,
1635 };
1636
1637 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1638 .use_imx_pcm = true,
1639 .use_edma = true,
1640 .fifo_depth = 64,
1641 .pins = 4,
1642 .reg_offset = 0,
1643 .mclk0_is_mclk1 = false,
1644 .flags = 0,
1645 .max_register = FSL_SAI_RMR,
1646 };
1647
1648 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
1649 .use_imx_pcm = true,
1650 .use_edma = false,
1651 .fifo_depth = 128,
1652 .reg_offset = 8,
1653 .mclk0_is_mclk1 = false,
1654 .pins = 8,
1655 .flags = 0,
1656 .max_register = FSL_SAI_MCTL,
1657 };
1658
1659 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
1660 .use_imx_pcm = true,
1661 .use_edma = false,
1662 .fifo_depth = 128,
1663 .reg_offset = 8,
1664 .mclk0_is_mclk1 = false,
1665 .pins = 8,
1666 .flags = 0,
1667 .max_register = FSL_SAI_MDIV,
1668 };
1669
1670 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
1671 .use_imx_pcm = true,
1672 .use_edma = false,
1673 .fifo_depth = 128,
1674 .reg_offset = 8,
1675 .mclk0_is_mclk1 = false,
1676 .pins = 8,
1677 .flags = 0,
1678 .max_register = FSL_SAI_MDIV,
1679 .mclk_with_tere = true,
1680 };
1681
1682 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
1683 .use_imx_pcm = true,
1684 .use_edma = true,
1685 .fifo_depth = 16,
1686 .reg_offset = 8,
1687 .mclk0_is_mclk1 = false,
1688 .pins = 4,
1689 .flags = PMQOS_CPU_LATENCY,
1690 .max_register = FSL_SAI_RTCAP,
1691 };
1692
1693 static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
1694 .use_imx_pcm = true,
1695 .use_edma = true,
1696 .fifo_depth = 128,
1697 .reg_offset = 8,
1698 .mclk0_is_mclk1 = false,
1699 .pins = 4,
1700 .flags = 0,
1701 .max_register = FSL_SAI_MCTL,
1702 .max_burst = {8, 8},
1703 };
1704
1705 static const struct fsl_sai_soc_data fsl_sai_imx95_data = {
1706 .use_imx_pcm = true,
1707 .use_edma = true,
1708 .fifo_depth = 128,
1709 .reg_offset = 8,
1710 .mclk0_is_mclk1 = false,
1711 .pins = 8,
1712 .flags = 0,
1713 .max_register = FSL_SAI_MCTL,
1714 .max_burst = {8, 8},
1715 };
1716
1717 static const struct of_device_id fsl_sai_ids[] = {
1718 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1719 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1720 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1721 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1722 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1723 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1724 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1725 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1726 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1727 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1728 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1729 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data },
1730 { /* sentinel */ }
1731 };
1732 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1733
1734 static int fsl_sai_runtime_suspend(struct device *dev)
1735 {
1736 struct fsl_sai *sai = dev_get_drvdata(dev);
1737
1738 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1739 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1740
1741 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1742 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1743
1744 clk_disable_unprepare(sai->bus_clk);
1745
1746 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1747 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1748
1749 regcache_cache_only(sai->regmap, true);
1750
1751 return 0;
1752 }
1753
1754 static int fsl_sai_runtime_resume(struct device *dev)
1755 {
1756 struct fsl_sai *sai = dev_get_drvdata(dev);
1757 unsigned int ofs = sai->soc_data->reg_offset;
1758 int ret;
1759
1760 ret = clk_prepare_enable(sai->bus_clk);
1761 if (ret) {
1762 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1763 return ret;
1764 }
1765
1766 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1767 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1768 if (ret)
1769 goto disable_bus_clk;
1770 }
1771
1772 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1773 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1774 if (ret)
1775 goto disable_tx_clk;
1776 }
1777
1778 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1779 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1780
1781 regcache_cache_only(sai->regmap, false);
1782 regcache_mark_dirty(sai->regmap);
1783 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1784 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1785 usleep_range(1000, 2000);
1786 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1787 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1788
1789 ret = regcache_sync(sai->regmap);
1790 if (ret)
1791 goto disable_rx_clk;
1792
1793 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1794 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1795 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
1796
1797 return 0;
1798
1799 disable_rx_clk:
1800 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1801 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1802 disable_tx_clk:
1803 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1804 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1805 disable_bus_clk:
1806 clk_disable_unprepare(sai->bus_clk);
1807
1808 return ret;
1809 }
1810
1811 static const struct dev_pm_ops fsl_sai_pm_ops = {
1812 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1813 fsl_sai_runtime_resume, NULL)
1814 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1815 pm_runtime_force_resume)
1816 };
1817
1818 static struct platform_driver fsl_sai_driver = {
1819 .probe = fsl_sai_probe,
1820 .remove_new = fsl_sai_remove,
1821 .driver = {
1822 .name = "fsl-sai",
1823 .pm = &fsl_sai_pm_ops,
1824 .of_match_table = fsl_sai_ids,
1825 },
1826 };
1827 module_platform_driver(fsl_sai_driver);
1828
1829 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1830 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1831 MODULE_ALIAS("platform:fsl-sai");
1832 MODULE_LICENSE("GPL");
1833
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.