1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
4 *
5 * Author: Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2007-2008 Freescale Semiconductor, Inc.
8 */
9
10 #ifndef _MPC8610_I2S_H
11 #define _MPC8610_I2S_H
12
13 /* -- SSI Register Map -- */
14
15 /* SSI Transmit Data Register 0 */
16 #define REG_SSI_STX0 0x00
17 /* SSI Transmit Data Register 1 */
18 #define REG_SSI_STX1 0x04
19 /* SSI Receive Data Register 0 */
20 #define REG_SSI_SRX0 0x08
21 /* SSI Receive Data Register 1 */
22 #define REG_SSI_SRX1 0x0c
23 /* SSI Control Register */
24 #define REG_SSI_SCR 0x10
25 /* SSI Interrupt Status Register */
26 #define REG_SSI_SISR 0x14
27 /* SSI Interrupt Enable Register */
28 #define REG_SSI_SIER 0x18
29 /* SSI Transmit Configuration Register */
30 #define REG_SSI_STCR 0x1c
31 /* SSI Receive Configuration Register */
32 #define REG_SSI_SRCR 0x20
33 #define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
34 /* SSI Transmit Clock Control Register */
35 #define REG_SSI_STCCR 0x24
36 /* SSI Receive Clock Control Register */
37 #define REG_SSI_SRCCR 0x28
38 #define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
39 /* SSI FIFO Control/Status Register */
40 #define REG_SSI_SFCSR 0x2c
41 /*
42 * SSI Test Register (Intended for debugging purposes only)
43 *
44 * Note: STR is not documented in recent IMX datasheet, but
45 * is described in IMX51 reference manual at section 56.3.3.14
46 */
47 #define REG_SSI_STR 0x30
48 /*
49 * SSI Option Register (Intended for internal use only)
50 *
51 * Note: SOR is not documented in recent IMX datasheet, but
52 * is described in IMX51 reference manual at section 56.3.3.15
53 */
54 #define REG_SSI_SOR 0x34
55 /* SSI AC97 Control Register */
56 #define REG_SSI_SACNT 0x38
57 /* SSI AC97 Command Address Register */
58 #define REG_SSI_SACADD 0x3c
59 /* SSI AC97 Command Data Register */
60 #define REG_SSI_SACDAT 0x40
61 /* SSI AC97 Tag Register */
62 #define REG_SSI_SATAG 0x44
63 /* SSI Transmit Time Slot Mask Register */
64 #define REG_SSI_STMSK 0x48
65 /* SSI Receive Time Slot Mask Register */
66 #define REG_SSI_SRMSK 0x4c
67 #define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
68 /*
69 * SSI AC97 Channel Status Register
70 *
71 * The status could be changed by:
72 * 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST
73 * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
74 * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
75 */
76 #define REG_SSI_SACCST 0x50
77 /* SSI AC97 Channel Enable Register -- Set bits in SACCST */
78 #define REG_SSI_SACCEN 0x54
79 /* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
80 #define REG_SSI_SACCDIS 0x58
81
82 /* -- SSI Register Field Maps -- */
83
84 /* SSI Control Register -- REG_SSI_SCR 0x10 */
85 #define SSI_SCR_SYNC_TX_FS 0x00001000
86 #define SSI_SCR_RFR_CLK_DIS 0x00000800
87 #define SSI_SCR_TFR_CLK_DIS 0x00000400
88 #define SSI_SCR_TCH_EN 0x00000100
89 #define SSI_SCR_SYS_CLK_EN 0x00000080
90 #define SSI_SCR_I2S_MODE_MASK 0x00000060
91 #define SSI_SCR_I2S_MODE_NORMAL 0x00000000
92 #define SSI_SCR_I2S_MODE_MASTER 0x00000020
93 #define SSI_SCR_I2S_MODE_SLAVE 0x00000040
94 #define SSI_SCR_SYN 0x00000010
95 #define SSI_SCR_NET 0x00000008
96 #define SSI_SCR_I2S_NET_MASK (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK)
97 #define SSI_SCR_RE 0x00000004
98 #define SSI_SCR_TE 0x00000002
99 #define SSI_SCR_SSIEN 0x00000001
100
101 /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
102 #define SSI_SISR_RFRC 0x01000000
103 #define SSI_SISR_TFRC 0x00800000
104 #define SSI_SISR_CMDAU 0x00040000
105 #define SSI_SISR_CMDDU 0x00020000
106 #define SSI_SISR_RXT 0x00010000
107 #define SSI_SISR_RDR1 0x00008000
108 #define SSI_SISR_RDR0 0x00004000
109 #define SSI_SISR_TDE1 0x00002000
110 #define SSI_SISR_TDE0 0x00001000
111 #define SSI_SISR_ROE1 0x00000800
112 #define SSI_SISR_ROE0 0x00000400
113 #define SSI_SISR_TUE1 0x00000200
114 #define SSI_SISR_TUE0 0x00000100
115 #define SSI_SISR_TFS 0x00000080
116 #define SSI_SISR_RFS 0x00000040
117 #define SSI_SISR_TLS 0x00000020
118 #define SSI_SISR_RLS 0x00000010
119 #define SSI_SISR_RFF1 0x00000008
120 #define SSI_SISR_RFF0 0x00000004
121 #define SSI_SISR_TFE1 0x00000002
122 #define SSI_SISR_TFE0 0x00000001
123
124 /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
125 #define SSI_SIER_RFRC_EN 0x01000000
126 #define SSI_SIER_TFRC_EN 0x00800000
127 #define SSI_SIER_RDMAE 0x00400000
128 #define SSI_SIER_RIE 0x00200000
129 #define SSI_SIER_TDMAE 0x00100000
130 #define SSI_SIER_TIE 0x00080000
131 #define SSI_SIER_CMDAU_EN 0x00040000
132 #define SSI_SIER_CMDDU_EN 0x00020000
133 #define SSI_SIER_RXT_EN 0x00010000
134 #define SSI_SIER_RDR1_EN 0x00008000
135 #define SSI_SIER_RDR0_EN 0x00004000
136 #define SSI_SIER_TDE1_EN 0x00002000
137 #define SSI_SIER_TDE0_EN 0x00001000
138 #define SSI_SIER_ROE1_EN 0x00000800
139 #define SSI_SIER_ROE0_EN 0x00000400
140 #define SSI_SIER_TUE1_EN 0x00000200
141 #define SSI_SIER_TUE0_EN 0x00000100
142 #define SSI_SIER_TFS_EN 0x00000080
143 #define SSI_SIER_RFS_EN 0x00000040
144 #define SSI_SIER_TLS_EN 0x00000020
145 #define SSI_SIER_RLS_EN 0x00000010
146 #define SSI_SIER_RFF1_EN 0x00000008
147 #define SSI_SIER_RFF0_EN 0x00000004
148 #define SSI_SIER_TFE1_EN 0x00000002
149 #define SSI_SIER_TFE0_EN 0x00000001
150
151 /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
152 #define SSI_STCR_TXBIT0 0x00000200
153 #define SSI_STCR_TFEN1 0x00000100
154 #define SSI_STCR_TFEN0 0x00000080
155 #define SSI_STCR_TFDIR 0x00000040
156 #define SSI_STCR_TXDIR 0x00000020
157 #define SSI_STCR_TSHFD 0x00000010
158 #define SSI_STCR_TSCKP 0x00000008
159 #define SSI_STCR_TFSI 0x00000004
160 #define SSI_STCR_TFSL 0x00000002
161 #define SSI_STCR_TEFS 0x00000001
162
163 /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
164 #define SSI_SRCR_RXEXT 0x00000400
165 #define SSI_SRCR_RXBIT0 0x00000200
166 #define SSI_SRCR_RFEN1 0x00000100
167 #define SSI_SRCR_RFEN0 0x00000080
168 #define SSI_SRCR_RFDIR 0x00000040
169 #define SSI_SRCR_RXDIR 0x00000020
170 #define SSI_SRCR_RSHFD 0x00000010
171 #define SSI_SRCR_RSCKP 0x00000008
172 #define SSI_SRCR_RFSI 0x00000004
173 #define SSI_SRCR_RFSL 0x00000002
174 #define SSI_SRCR_REFS 0x00000001
175
176 /*
177 * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
178 * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
179 */
180 #define SSI_SxCCR_DIV2_SHIFT 18
181 #define SSI_SxCCR_DIV2 0x00040000
182 #define SSI_SxCCR_PSR_SHIFT 17
183 #define SSI_SxCCR_PSR 0x00020000
184 #define SSI_SxCCR_WL_SHIFT 13
185 #define SSI_SxCCR_WL_MASK 0x0001E000
186 #define SSI_SxCCR_WL(x) \
187 (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
188 #define SSI_SxCCR_DC_SHIFT 8
189 #define SSI_SxCCR_DC_MASK 0x00001F00
190 #define SSI_SxCCR_DC(x) \
191 ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
192 #define SSI_SxCCR_PM_SHIFT 0
193 #define SSI_SxCCR_PM_MASK 0x000000FF
194 #define SSI_SxCCR_PM(x) \
195 ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
196
197 /*
198 * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
199 *
200 * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
201 * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
202 */
203 #define SSI_SFCSR_RFCNT1_SHIFT 28
204 #define SSI_SFCSR_RFCNT1_MASK 0xF0000000
205 #define SSI_SFCSR_RFCNT1(x) \
206 (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
207 #define SSI_SFCSR_TFCNT1_SHIFT 24
208 #define SSI_SFCSR_TFCNT1_MASK 0x0F000000
209 #define SSI_SFCSR_TFCNT1(x) \
210 (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
211 #define SSI_SFCSR_RFWM1_SHIFT 20
212 #define SSI_SFCSR_RFWM1_MASK 0x00F00000
213 #define SSI_SFCSR_RFWM1(x) \
214 (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
215 #define SSI_SFCSR_TFWM1_SHIFT 16
216 #define SSI_SFCSR_TFWM1_MASK 0x000F0000
217 #define SSI_SFCSR_TFWM1(x) \
218 (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
219 #define SSI_SFCSR_RFCNT0_SHIFT 12
220 #define SSI_SFCSR_RFCNT0_MASK 0x0000F000
221 #define SSI_SFCSR_RFCNT0(x) \
222 (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
223 #define SSI_SFCSR_TFCNT0_SHIFT 8
224 #define SSI_SFCSR_TFCNT0_MASK 0x00000F00
225 #define SSI_SFCSR_TFCNT0(x) \
226 (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
227 #define SSI_SFCSR_RFWM0_SHIFT 4
228 #define SSI_SFCSR_RFWM0_MASK 0x000000F0
229 #define SSI_SFCSR_RFWM0(x) \
230 (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
231 #define SSI_SFCSR_TFWM0_SHIFT 0
232 #define SSI_SFCSR_TFWM0_MASK 0x0000000F
233 #define SSI_SFCSR_TFWM0(x) \
234 (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
235
236 /* SSI Test Register -- REG_SSI_STR 0x30 */
237 #define SSI_STR_TEST 0x00008000
238 #define SSI_STR_RCK2TCK 0x00004000
239 #define SSI_STR_RFS2TFS 0x00002000
240 #define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
241 #define SSI_STR_TXD2RXD 0x00000080
242 #define SSI_STR_TCK2RCK 0x00000040
243 #define SSI_STR_TFS2RFS 0x00000020
244 #define SSI_STR_TXSTATE(x) ((x) & 0x1F)
245
246 /* SSI Option Register -- REG_SSI_SOR 0x34 */
247 #define SSI_SOR_CLKOFF 0x00000040
248 #define SSI_SOR_RX_CLR 0x00000020
249 #define SSI_SOR_TX_CLR 0x00000010
250 #define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
251 #define SSI_SOR_INIT 0x00000008
252 #define SSI_SOR_WAIT_SHIFT 1
253 #define SSI_SOR_WAIT_MASK 0x00000006
254 #define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT)
255 #define SSI_SOR_SYNRST 0x00000001
256
257 /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
258 #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
259 #define SSI_SACNT_WR 0x00000010
260 #define SSI_SACNT_RD 0x00000008
261 #define SSI_SACNT_RDWR_MASK 0x00000018
262 #define SSI_SACNT_TIF 0x00000004
263 #define SSI_SACNT_FV 0x00000002
264 #define SSI_SACNT_AC97EN 0x00000001
265
266
267 struct device;
268
269 #if IS_ENABLED(CONFIG_DEBUG_FS)
270
271 struct fsl_ssi_dbg {
272 struct dentry *dbg_dir;
273
274 struct {
275 unsigned int rfrc;
276 unsigned int tfrc;
277 unsigned int cmdau;
278 unsigned int cmddu;
279 unsigned int rxt;
280 unsigned int rdr1;
281 unsigned int rdr0;
282 unsigned int tde1;
283 unsigned int tde0;
284 unsigned int roe1;
285 unsigned int roe0;
286 unsigned int tue1;
287 unsigned int tue0;
288 unsigned int tfs;
289 unsigned int rfs;
290 unsigned int tls;
291 unsigned int rls;
292 unsigned int rff1;
293 unsigned int rff0;
294 unsigned int tfe1;
295 unsigned int tfe0;
296 } stats;
297 };
298
299 void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
300
301 void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
302
303 void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
304
305 #else
306
307 struct fsl_ssi_dbg {
308 };
309
310 static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
311 {
312 }
313
314 static inline void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
315 struct device *dev)
316 {
317 }
318
319 static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
320 {
321 }
322 #endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
323
324 #endif
325
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