1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * skl_topology.h - Intel HDA Platform topology header file
4 *
5 * Copyright (C) 2014-15 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 */
11
12 #ifndef __SKL_TOPOLOGY_H__
13 #define __SKL_TOPOLOGY_H__
14
15 #include <linux/types.h>
16
17 #include <sound/hdaudio_ext.h>
18 #include <sound/soc.h>
19 #include <uapi/sound/skl-tplg-interface.h>
20 #include "skl.h"
21
22 #define BITS_PER_BYTE 8
23 #define MAX_TS_GROUPS 8
24 #define MAX_DMIC_TS_GROUPS 4
25 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
26
27 /* Maximum number of coefficients up down mixer module */
28 #define UP_DOWN_MIXER_MAX_COEFF 8
29
30 #define MODULE_MAX_IN_PINS 8
31 #define MODULE_MAX_OUT_PINS 8
32
33 #define SKL_MIC_CH_SUPPORT 4
34 #define SKL_MIC_MAX_CH_SUPPORT 8
35 #define SKL_DEFAULT_MIC_SEL_GAIN 0x3FF
36 #define SKL_MIC_SEL_SWITCH 0x3
37
38 #define SKL_OUTPUT_PIN 0
39 #define SKL_INPUT_PIN 1
40 #define SKL_MAX_PATH_CONFIGS 8
41 #define SKL_MAX_MODULES_IN_PIPE 8
42 #define SKL_MAX_MODULE_FORMATS 32
43 #define SKL_MAX_MODULE_RESOURCES 32
44
45 enum skl_channel_index {
46 SKL_CHANNEL_LEFT = 0,
47 SKL_CHANNEL_RIGHT = 1,
48 SKL_CHANNEL_CENTER = 2,
49 SKL_CHANNEL_LEFT_SURROUND = 3,
50 SKL_CHANNEL_CENTER_SURROUND = 3,
51 SKL_CHANNEL_RIGHT_SURROUND = 4,
52 SKL_CHANNEL_LFE = 7,
53 SKL_CHANNEL_INVALID = 0xF,
54 };
55
56 enum skl_bitdepth {
57 SKL_DEPTH_8BIT = 8,
58 SKL_DEPTH_16BIT = 16,
59 SKL_DEPTH_24BIT = 24,
60 SKL_DEPTH_32BIT = 32,
61 SKL_DEPTH_INVALID
62 };
63
64
65 enum skl_s_freq {
66 SKL_FS_8000 = 8000,
67 SKL_FS_11025 = 11025,
68 SKL_FS_12000 = 12000,
69 SKL_FS_16000 = 16000,
70 SKL_FS_22050 = 22050,
71 SKL_FS_24000 = 24000,
72 SKL_FS_32000 = 32000,
73 SKL_FS_44100 = 44100,
74 SKL_FS_48000 = 48000,
75 SKL_FS_64000 = 64000,
76 SKL_FS_88200 = 88200,
77 SKL_FS_96000 = 96000,
78 SKL_FS_128000 = 128000,
79 SKL_FS_176400 = 176400,
80 SKL_FS_192000 = 192000,
81 SKL_FS_INVALID
82 };
83
84 #define SKL_MAX_PARAMS_TYPES 4
85
86 enum skl_widget_type {
87 SKL_WIDGET_VMIXER = 1,
88 SKL_WIDGET_MIXER = 2,
89 SKL_WIDGET_PGA = 3,
90 SKL_WIDGET_MUX = 4
91 };
92
93 struct skl_audio_data_format {
94 enum skl_s_freq s_freq;
95 enum skl_bitdepth bit_depth;
96 u32 channel_map;
97 enum skl_ch_cfg ch_cfg;
98 enum skl_interleaving interleaving;
99 u8 number_of_channels;
100 u8 valid_bit_depth;
101 u8 sample_type;
102 u8 reserved;
103 } __packed;
104
105 struct skl_base_cfg {
106 u32 cpc;
107 u32 ibs;
108 u32 obs;
109 u32 is_pages;
110 struct skl_audio_data_format audio_fmt;
111 };
112
113 struct skl_cpr_gtw_cfg {
114 u32 node_id;
115 u32 dma_buffer_size;
116 u32 config_length;
117 /* not mandatory; required only for DMIC/I2S */
118 struct {
119 u32 gtw_attrs;
120 u32 data[];
121 } config_data;
122 } __packed;
123
124 struct skl_dma_control {
125 u32 node_id;
126 u32 config_length;
127 u32 config_data[];
128 } __packed;
129
130 struct skl_cpr_cfg {
131 struct skl_base_cfg base_cfg;
132 struct skl_audio_data_format out_fmt;
133 u32 cpr_feature_mask;
134 struct skl_cpr_gtw_cfg gtw_cfg;
135 } __packed;
136
137 struct skl_cpr_pin_fmt {
138 u32 sink_id;
139 struct skl_audio_data_format src_fmt;
140 struct skl_audio_data_format dst_fmt;
141 } __packed;
142
143 struct skl_src_module_cfg {
144 struct skl_base_cfg base_cfg;
145 enum skl_s_freq src_cfg;
146 } __packed;
147
148 struct skl_up_down_mixer_cfg {
149 struct skl_base_cfg base_cfg;
150 enum skl_ch_cfg out_ch_cfg;
151 /* This should be set to 1 if user coefficients are required */
152 u32 coeff_sel;
153 /* Pass the user coeff in this array */
154 s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
155 u32 ch_map;
156 } __packed;
157
158 struct skl_pin_format {
159 u32 pin_idx;
160 u32 buf_size;
161 struct skl_audio_data_format audio_fmt;
162 } __packed;
163
164 struct skl_base_cfg_ext {
165 u16 nr_input_pins;
166 u16 nr_output_pins;
167 u8 reserved[8];
168 u32 priv_param_length;
169 /* Input pin formats followed by output ones. */
170 struct skl_pin_format pins_fmt[];
171 } __packed;
172
173 struct skl_algo_cfg {
174 struct skl_base_cfg base_cfg;
175 char params[];
176 } __packed;
177
178 struct skl_base_outfmt_cfg {
179 struct skl_base_cfg base_cfg;
180 struct skl_audio_data_format out_fmt;
181 } __packed;
182
183 enum skl_dma_type {
184 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
185 SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
186 SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
187 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
188 SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
189 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
190 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
191 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
192 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
193 };
194
195 union skl_ssp_dma_node {
196 u8 val;
197 struct {
198 u8 time_slot_index:4;
199 u8 i2s_instance:4;
200 } dma_node;
201 };
202
203 union skl_connector_node_id {
204 u32 val;
205 struct {
206 u32 vindex:8;
207 u32 dma_type:4;
208 u32 rsvd:20;
209 } node;
210 };
211
212 struct skl_module_fmt {
213 u32 channels;
214 u32 s_freq;
215 u32 bit_depth;
216 u32 valid_bit_depth;
217 u32 ch_cfg;
218 u32 interleaving_style;
219 u32 sample_type;
220 u32 ch_map;
221 };
222
223 struct skl_module_cfg;
224
225 struct skl_mod_inst_map {
226 u16 mod_id;
227 u16 inst_id;
228 };
229
230 struct skl_uuid_inst_map {
231 u16 inst_id;
232 u16 reserved;
233 guid_t mod_uuid;
234 } __packed;
235
236 struct skl_kpb_params {
237 u32 num_modules;
238 union {
239 DECLARE_FLEX_ARRAY(struct skl_mod_inst_map, map);
240 DECLARE_FLEX_ARRAY(struct skl_uuid_inst_map, map_uuid);
241 } u;
242 };
243
244 struct skl_module_inst_id {
245 guid_t mod_uuid;
246 int module_id;
247 u32 instance_id;
248 int pvt_id;
249 };
250
251 enum skl_module_pin_state {
252 SKL_PIN_UNBIND = 0,
253 SKL_PIN_BIND_DONE = 1,
254 };
255
256 struct skl_module_pin {
257 struct skl_module_inst_id id;
258 bool is_dynamic;
259 bool in_use;
260 enum skl_module_pin_state pin_state;
261 struct skl_module_cfg *tgt_mcfg;
262 };
263
264 struct skl_specific_cfg {
265 u32 set_params;
266 u32 param_id;
267 u32 caps_size;
268 u32 *caps;
269 };
270
271 enum skl_pipe_state {
272 SKL_PIPE_INVALID = 0,
273 SKL_PIPE_CREATED = 1,
274 SKL_PIPE_PAUSED = 2,
275 SKL_PIPE_STARTED = 3,
276 SKL_PIPE_RESET = 4
277 };
278
279 struct skl_pipe_module {
280 struct snd_soc_dapm_widget *w;
281 struct list_head node;
282 };
283
284 struct skl_pipe_params {
285 u8 host_dma_id;
286 u8 link_dma_id;
287 u32 ch;
288 u32 s_freq;
289 u32 s_fmt;
290 u32 s_cont;
291 u8 linktype;
292 snd_pcm_format_t format;
293 int link_index;
294 int stream;
295 unsigned int host_bps;
296 unsigned int link_bps;
297 };
298
299 struct skl_pipe_fmt {
300 u32 freq;
301 u8 channels;
302 u8 bps;
303 };
304
305 struct skl_pipe_mcfg {
306 u8 res_idx;
307 u8 fmt_idx;
308 };
309
310 struct skl_path_config {
311 u8 mem_pages;
312 struct skl_pipe_fmt in_fmt;
313 struct skl_pipe_fmt out_fmt;
314 };
315
316 struct skl_pipe {
317 u8 ppl_id;
318 u8 pipe_priority;
319 u16 conn_type;
320 u32 memory_pages;
321 u8 lp_mode;
322 struct skl_pipe_params *p_params;
323 enum skl_pipe_state state;
324 u8 direction;
325 u8 cur_config_idx;
326 u8 nr_cfgs;
327 struct skl_path_config configs[SKL_MAX_PATH_CONFIGS];
328 struct list_head w_list;
329 bool passthru;
330 };
331
332 enum skl_module_state {
333 SKL_MODULE_UNINIT = 0,
334 SKL_MODULE_INIT_DONE = 1,
335 SKL_MODULE_BIND_DONE = 2,
336 };
337
338 enum d0i3_capability {
339 SKL_D0I3_NONE = 0,
340 SKL_D0I3_STREAMING = 1,
341 SKL_D0I3_NON_STREAMING = 2,
342 };
343
344 struct skl_module_pin_fmt {
345 u8 id;
346 struct skl_module_fmt fmt;
347 };
348
349 struct skl_module_iface {
350 u8 fmt_idx;
351 u8 nr_in_fmt;
352 u8 nr_out_fmt;
353 struct skl_module_pin_fmt inputs[MAX_IN_QUEUE];
354 struct skl_module_pin_fmt outputs[MAX_OUT_QUEUE];
355 };
356
357 struct skl_module_pin_resources {
358 u8 pin_index;
359 u32 buf_size;
360 };
361
362 struct skl_module_res {
363 u8 id;
364 u32 is_pages;
365 u32 ibs;
366 u32 obs;
367 u32 dma_buffer_size;
368 u32 cpc;
369 u8 nr_input_pins;
370 u8 nr_output_pins;
371 struct skl_module_pin_resources input[MAX_IN_QUEUE];
372 struct skl_module_pin_resources output[MAX_OUT_QUEUE];
373 };
374
375 struct skl_module {
376 guid_t uuid;
377 u8 loadable;
378 u8 input_pin_type;
379 u8 output_pin_type;
380 u8 max_input_pins;
381 u8 max_output_pins;
382 u8 nr_resources;
383 u8 nr_interfaces;
384 struct skl_module_res resources[SKL_MAX_MODULE_RESOURCES];
385 struct skl_module_iface formats[SKL_MAX_MODULE_FORMATS];
386 };
387
388 struct skl_module_cfg {
389 u8 guid[16];
390 struct skl_module_inst_id id;
391 struct skl_module *module;
392 int res_idx;
393 int fmt_idx;
394 int fmt_cfg_idx;
395 u8 domain;
396 bool homogenous_inputs;
397 bool homogenous_outputs;
398 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
399 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
400 u8 max_in_queue;
401 u8 max_out_queue;
402 u8 in_queue_mask;
403 u8 out_queue_mask;
404 u8 in_queue;
405 u8 out_queue;
406 u8 is_loadable;
407 u8 core_id;
408 u8 dev_type;
409 u8 dma_id;
410 u8 time_slot;
411 u8 dmic_ch_combo_index;
412 u32 dmic_ch_type;
413 u32 params_fixup;
414 u32 converter;
415 u32 vbus_id;
416 u32 mem_pages;
417 enum d0i3_capability d0i3_caps;
418 u32 dma_buffer_size; /* in milli seconds */
419 struct skl_module_pin *m_in_pin;
420 struct skl_module_pin *m_out_pin;
421 enum skl_module_type m_type;
422 enum skl_hw_conn_type hw_conn_type;
423 enum skl_module_state m_state;
424 struct skl_pipe *pipe;
425 struct skl_specific_cfg formats_config[SKL_MAX_PARAMS_TYPES];
426 struct skl_pipe_mcfg mod_cfg[SKL_MAX_MODULES_IN_PIPE];
427 };
428
429 struct skl_algo_data {
430 u32 param_id;
431 u32 set_params;
432 u32 max;
433 u32 size;
434 char *params;
435 };
436
437 struct skl_pipeline {
438 struct skl_pipe *pipe;
439 struct list_head node;
440 };
441
442 struct skl_module_deferred_bind {
443 struct skl_module_cfg *src;
444 struct skl_module_cfg *dst;
445 struct list_head node;
446 };
447
448 struct skl_mic_sel_config {
449 u16 mic_switch;
450 u16 flags;
451 u16 blob[SKL_MIC_MAX_CH_SUPPORT][SKL_MIC_MAX_CH_SUPPORT];
452 } __packed;
453
454 enum skl_channel {
455 SKL_CH_MONO = 1,
456 SKL_CH_STEREO = 2,
457 SKL_CH_TRIO = 3,
458 SKL_CH_QUATRO = 4,
459 };
460
461 static inline struct skl_dev *get_skl_ctx(struct device *dev)
462 {
463 struct hdac_bus *bus = dev_get_drvdata(dev);
464
465 return bus_to_skl(bus);
466 }
467
468 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
469 struct skl_pipe_params *params);
470 int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
471 u32 caps_size, u32 node_id);
472 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
473 struct skl_pipe_params *params, int stream);
474 int skl_tplg_init(struct snd_soc_component *component,
475 struct hdac_bus *bus);
476 void skl_tplg_exit(struct snd_soc_component *component,
477 struct hdac_bus *bus);
478 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
479 struct snd_soc_dai *dai, int stream);
480 int skl_tplg_update_pipe_params(struct device *dev,
481 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
482
483 void skl_tplg_d0i3_get(struct skl_dev *skl, enum d0i3_capability caps);
484 void skl_tplg_d0i3_put(struct skl_dev *skl, enum d0i3_capability caps);
485
486 int skl_create_pipeline(struct skl_dev *skl, struct skl_pipe *pipe);
487
488 int skl_run_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
489
490 int skl_pause_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
491
492 int skl_delete_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
493
494 int skl_stop_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
495
496 int skl_reset_pipe(struct skl_dev *skl, struct skl_pipe *pipe);
497
498 int skl_init_module(struct skl_dev *skl, struct skl_module_cfg *mconfig);
499
500 int skl_bind_modules(struct skl_dev *skl, struct skl_module_cfg
501 *src_mcfg, struct skl_module_cfg *dst_mcfg);
502
503 int skl_unbind_modules(struct skl_dev *skl, struct skl_module_cfg
504 *src_mcfg, struct skl_module_cfg *dst_mcfg);
505
506 int skl_set_module_params(struct skl_dev *skl, u32 *params, int size,
507 u32 param_id, struct skl_module_cfg *mcfg);
508 int skl_get_module_params(struct skl_dev *skl, u32 *params, int size,
509 u32 param_id, struct skl_module_cfg *mcfg);
510
511 struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
512 int stream);
513 enum skl_bitdepth skl_get_bit_depth(int params);
514 int skl_pcm_host_dma_prepare(struct device *dev,
515 struct skl_pipe_params *params);
516 int skl_pcm_link_dma_prepare(struct device *dev,
517 struct skl_pipe_params *params);
518
519 int skl_dai_load(struct snd_soc_component *cmp, int index,
520 struct snd_soc_dai_driver *dai_drv,
521 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai);
522 void skl_tplg_add_moduleid_in_bind_params(struct skl_dev *skl,
523 struct snd_soc_dapm_widget *w);
524 #endif
525
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.