1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * mt8188-audsys-clkid.h -- MediaTek 8188 audsys clock id definition
4 *
5 * Copyright (c) 2022 MediaTek Inc.
6 * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
7 */
8
9 #ifndef _MT8188_AUDSYS_CLKID_H_
10 #define _MT8188_AUDSYS_CLKID_H_
11
12 enum{
13 CLK_AUD_AFE,
14 CLK_AUD_LRCK_CNT,
15 CLK_AUD_SPDIFIN_TUNER_APLL,
16 CLK_AUD_SPDIFIN_TUNER_DBG,
17 CLK_AUD_UL_TML,
18 CLK_AUD_APLL1_TUNER,
19 CLK_AUD_APLL2_TUNER,
20 CLK_AUD_TOP0_SPDF,
21 CLK_AUD_APLL,
22 CLK_AUD_APLL2,
23 CLK_AUD_DAC,
24 CLK_AUD_DAC_PREDIS,
25 CLK_AUD_TML,
26 CLK_AUD_ADC,
27 CLK_AUD_DAC_HIRES,
28 CLK_AUD_A1SYS_HP,
29 CLK_AUD_AFE_DMIC1,
30 CLK_AUD_AFE_DMIC2,
31 CLK_AUD_AFE_DMIC3,
32 CLK_AUD_AFE_DMIC4,
33 CLK_AUD_AFE_26M_DMIC_TM,
34 CLK_AUD_UL_TML_HIRES,
35 CLK_AUD_ADC_HIRES,
36 CLK_AUD_LINEIN_TUNER,
37 CLK_AUD_EARC_TUNER,
38 CLK_AUD_I2SIN,
39 CLK_AUD_TDM_IN,
40 CLK_AUD_I2S_OUT,
41 CLK_AUD_TDM_OUT,
42 CLK_AUD_HDMI_OUT,
43 CLK_AUD_ASRC11,
44 CLK_AUD_ASRC12,
45 CLK_AUD_MULTI_IN,
46 CLK_AUD_INTDIR,
47 CLK_AUD_A1SYS,
48 CLK_AUD_A2SYS,
49 CLK_AUD_PCMIF,
50 CLK_AUD_A3SYS,
51 CLK_AUD_A4SYS,
52 CLK_AUD_MEMIF_UL1,
53 CLK_AUD_MEMIF_UL2,
54 CLK_AUD_MEMIF_UL3,
55 CLK_AUD_MEMIF_UL4,
56 CLK_AUD_MEMIF_UL5,
57 CLK_AUD_MEMIF_UL6,
58 CLK_AUD_MEMIF_UL8,
59 CLK_AUD_MEMIF_UL9,
60 CLK_AUD_MEMIF_UL10,
61 CLK_AUD_MEMIF_DL2,
62 CLK_AUD_MEMIF_DL3,
63 CLK_AUD_MEMIF_DL6,
64 CLK_AUD_MEMIF_DL7,
65 CLK_AUD_MEMIF_DL8,
66 CLK_AUD_MEMIF_DL10,
67 CLK_AUD_MEMIF_DL11,
68 CLK_AUD_GASRC0,
69 CLK_AUD_GASRC1,
70 CLK_AUD_GASRC2,
71 CLK_AUD_GASRC3,
72 CLK_AUD_GASRC4,
73 CLK_AUD_GASRC5,
74 CLK_AUD_GASRC6,
75 CLK_AUD_GASRC7,
76 CLK_AUD_GASRC8,
77 CLK_AUD_GASRC9,
78 CLK_AUD_GASRC10,
79 CLK_AUD_GASRC11,
80 CLK_AUD_NR_CLK,
81 };
82
83 #endif
84
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