1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * mt8192-reg.h -- Mediatek 8192 audio driver reg definition
4 *
5 * Copyright (c) 2020 MediaTek Inc.
6 * Author: Shane Chien <shane.chien@mediatek.com>
7 */
8
9 #ifndef _MT8192_REG_H_
10 #define _MT8192_REG_H_
11
12 /* reg bit enum */
13 enum {
14 MT8192_MEMIF_PBUF_SIZE_32_BYTES,
15 MT8192_MEMIF_PBUF_SIZE_64_BYTES,
16 MT8192_MEMIF_PBUF_SIZE_128_BYTES,
17 MT8192_MEMIF_PBUF_SIZE_256_BYTES,
18 MT8192_MEMIF_PBUF_SIZE_NUM,
19 };
20
21 /*****************************************************************************
22 * R E G I S T E R D E F I N I T I O N
23 *****************************************************************************/
24 /* AUDIO_TOP_CON3 */
25 #define BCK_INVERSE_SFT 3
26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
28
29 /* AFE_DAC_CON0 */
30 #define VUL12_ON_SFT 31
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
33 #define MOD_DAI_ON_SFT 30
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
36 #define DAI_ON_SFT 29
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
39 #define DAI2_ON_SFT 28
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
42 #define VUL6_ON_SFT 23
43 #define VUL6_ON_MASK 0x1
44 #define VUL6_ON_MASK_SFT (0x1 << 23)
45 #define VUL5_ON_SFT 22
46 #define VUL5_ON_MASK 0x1
47 #define VUL5_ON_MASK_SFT (0x1 << 22)
48 #define VUL4_ON_SFT 21
49 #define VUL4_ON_MASK 0x1
50 #define VUL4_ON_MASK_SFT (0x1 << 21)
51 #define VUL3_ON_SFT 20
52 #define VUL3_ON_MASK 0x1
53 #define VUL3_ON_MASK_SFT (0x1 << 20)
54 #define VUL2_ON_SFT 19
55 #define VUL2_ON_MASK 0x1
56 #define VUL2_ON_MASK_SFT (0x1 << 19)
57 #define VUL_ON_SFT 18
58 #define VUL_ON_MASK 0x1
59 #define VUL_ON_MASK_SFT (0x1 << 18)
60 #define AWB2_ON_SFT 17
61 #define AWB2_ON_MASK 0x1
62 #define AWB2_ON_MASK_SFT (0x1 << 17)
63 #define AWB_ON_SFT 16
64 #define AWB_ON_MASK 0x1
65 #define AWB_ON_MASK_SFT (0x1 << 16)
66 #define DL12_ON_SFT 15
67 #define DL12_ON_MASK 0x1
68 #define DL12_ON_MASK_SFT (0x1 << 15)
69 #define DL9_ON_SFT 12
70 #define DL9_ON_MASK 0x1
71 #define DL9_ON_MASK_SFT (0x1 << 12)
72 #define DL8_ON_SFT 11
73 #define DL8_ON_MASK 0x1
74 #define DL8_ON_MASK_SFT (0x1 << 11)
75 #define DL7_ON_SFT 10
76 #define DL7_ON_MASK 0x1
77 #define DL7_ON_MASK_SFT (0x1 << 10)
78 #define DL6_ON_SFT 9
79 #define DL6_ON_MASK 0x1
80 #define DL6_ON_MASK_SFT (0x1 << 9)
81 #define DL5_ON_SFT 8
82 #define DL5_ON_MASK 0x1
83 #define DL5_ON_MASK_SFT (0x1 << 8)
84 #define DL4_ON_SFT 7
85 #define DL4_ON_MASK 0x1
86 #define DL4_ON_MASK_SFT (0x1 << 7)
87 #define DL3_ON_SFT 6
88 #define DL3_ON_MASK 0x1
89 #define DL3_ON_MASK_SFT (0x1 << 6)
90 #define DL2_ON_SFT 5
91 #define DL2_ON_MASK 0x1
92 #define DL2_ON_MASK_SFT (0x1 << 5)
93 #define DL1_ON_SFT 4
94 #define DL1_ON_MASK 0x1
95 #define DL1_ON_MASK_SFT (0x1 << 4)
96 #define HDMI_OUT_ON_SFT 1
97 #define HDMI_OUT_ON_MASK 0x1
98 #define HDMI_OUT_ON_MASK_SFT (0x1 << 1)
99 #define AFE_ON_SFT 0
100 #define AFE_ON_MASK 0x1
101 #define AFE_ON_MASK_SFT (0x1 << 0)
102
103 /* AFE_DAC_MON */
104 #define AFE_ON_RETM_SFT 0
105 #define AFE_ON_RETM_MASK 0x1
106 #define AFE_ON_RETM_MASK_SFT (0x1 << 0)
107
108 /* AFE_I2S_CON */
109 #define BCK_NEG_EG_LATCH_SFT 30
110 #define BCK_NEG_EG_LATCH_MASK 0x1
111 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
112 #define BCK_INV_SFT 29
113 #define BCK_INV_MASK 0x1
114 #define BCK_INV_MASK_SFT (0x1 << 29)
115 #define I2SIN_PAD_SEL_SFT 28
116 #define I2SIN_PAD_SEL_MASK 0x1
117 #define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
118 #define I2S_LOOPBACK_SFT 20
119 #define I2S_LOOPBACK_MASK 0x1
120 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
121 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
122 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
123 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
124 #define I2S1_HD_EN_SFT 12
125 #define I2S1_HD_EN_MASK 0x1
126 #define I2S1_HD_EN_MASK_SFT (0x1 << 12)
127 #define I2S_OUT_MODE_SFT 8
128 #define I2S_OUT_MODE_MASK 0xf
129 #define I2S_OUT_MODE_MASK_SFT (0xf << 8)
130 #define INV_PAD_CTRL_SFT 7
131 #define INV_PAD_CTRL_MASK 0x1
132 #define INV_PAD_CTRL_MASK_SFT (0x1 << 7)
133 #define I2S_BYPSRC_SFT 6
134 #define I2S_BYPSRC_MASK 0x1
135 #define I2S_BYPSRC_MASK_SFT (0x1 << 6)
136 #define INV_LRCK_SFT 5
137 #define INV_LRCK_MASK 0x1
138 #define INV_LRCK_MASK_SFT (0x1 << 5)
139 #define I2S_FMT_SFT 3
140 #define I2S_FMT_MASK 0x1
141 #define I2S_FMT_MASK_SFT (0x1 << 3)
142 #define I2S_SRC_SFT 2
143 #define I2S_SRC_MASK 0x1
144 #define I2S_SRC_MASK_SFT (0x1 << 2)
145 #define I2S_WLEN_SFT 1
146 #define I2S_WLEN_MASK 0x1
147 #define I2S_WLEN_MASK_SFT (0x1 << 1)
148 #define I2S_EN_SFT 0
149 #define I2S_EN_MASK 0x1
150 #define I2S_EN_MASK_SFT (0x1 << 0)
151
152 /* AFE_I2S_CON1 */
153 #define I2S2_LR_SWAP_SFT 31
154 #define I2S2_LR_SWAP_MASK 0x1
155 #define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)
156 #define I2S2_SEL_O19_O20_SFT 18
157 #define I2S2_SEL_O19_O20_MASK 0x1
158 #define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)
159 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
160 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
161 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
162 #define I2S2_SEL_O03_O04_SFT 16
163 #define I2S2_SEL_O03_O04_MASK 0x1
164 #define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)
165 #define I2S2_32BIT_EN_SFT 13
166 #define I2S2_32BIT_EN_MASK 0x1
167 #define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)
168 #define I2S2_HD_EN_SFT 12
169 #define I2S2_HD_EN_MASK 0x1
170 #define I2S2_HD_EN_MASK_SFT (0x1 << 12)
171 #define I2S2_OUT_MODE_SFT 8
172 #define I2S2_OUT_MODE_MASK 0xf
173 #define I2S2_OUT_MODE_MASK_SFT (0xf << 8)
174 #define INV_LRCK_SFT 5
175 #define INV_LRCK_MASK 0x1
176 #define INV_LRCK_MASK_SFT (0x1 << 5)
177 #define I2S2_FMT_SFT 3
178 #define I2S2_FMT_MASK 0x1
179 #define I2S2_FMT_MASK_SFT (0x1 << 3)
180 #define I2S2_WLEN_SFT 1
181 #define I2S2_WLEN_MASK 0x1
182 #define I2S2_WLEN_MASK_SFT (0x1 << 1)
183 #define I2S2_EN_SFT 0
184 #define I2S2_EN_MASK 0x1
185 #define I2S2_EN_MASK_SFT (0x1 << 0)
186
187 /* AFE_I2S_CON2 */
188 #define I2S3_LR_SWAP_SFT 31
189 #define I2S3_LR_SWAP_MASK 0x1
190 #define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)
191 #define I2S3_UPDATE_WORD_SFT 24
192 #define I2S3_UPDATE_WORD_MASK 0x1f
193 #define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24)
194 #define I2S3_BCK_INV_SFT 23
195 #define I2S3_BCK_INV_MASK 0x1
196 #define I2S3_BCK_INV_MASK_SFT (0x1 << 23)
197 #define I2S3_FPGA_BIT_TEST_SFT 22
198 #define I2S3_FPGA_BIT_TEST_MASK 0x1
199 #define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)
200 #define I2S3_FPGA_BIT_SFT 21
201 #define I2S3_FPGA_BIT_MASK 0x1
202 #define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)
203 #define I2S3_LOOPBACK_SFT 20
204 #define I2S3_LOOPBACK_MASK 0x1
205 #define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)
206 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
207 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
208 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
209 #define I2S3_HD_EN_SFT 12
210 #define I2S3_HD_EN_MASK 0x1
211 #define I2S3_HD_EN_MASK_SFT (0x1 << 12)
212 #define I2S3_OUT_MODE_SFT 8
213 #define I2S3_OUT_MODE_MASK 0xf
214 #define I2S3_OUT_MODE_MASK_SFT (0xf << 8)
215 #define I2S3_FMT_SFT 3
216 #define I2S3_FMT_MASK 0x1
217 #define I2S3_FMT_MASK_SFT (0x1 << 3)
218 #define I2S3_WLEN_SFT 1
219 #define I2S3_WLEN_MASK 0x1
220 #define I2S3_WLEN_MASK_SFT (0x1 << 1)
221 #define I2S3_EN_SFT 0
222 #define I2S3_EN_MASK 0x1
223 #define I2S3_EN_MASK_SFT (0x1 << 0)
224
225 /* AFE_I2S_CON3 */
226 #define I2S4_LR_SWAP_SFT 31
227 #define I2S4_LR_SWAP_MASK 0x1
228 #define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)
229 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
230 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
231 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
232 #define I2S4_32BIT_EN_SFT 13
233 #define I2S4_32BIT_EN_MASK 0x1
234 #define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)
235 #define I2S4_HD_EN_SFT 12
236 #define I2S4_HD_EN_MASK 0x1
237 #define I2S4_HD_EN_MASK_SFT (0x1 << 12)
238 #define I2S4_OUT_MODE_SFT 8
239 #define I2S4_OUT_MODE_MASK 0xf
240 #define I2S4_OUT_MODE_MASK_SFT (0xf << 8)
241 #define INV_LRCK_SFT 5
242 #define INV_LRCK_MASK 0x1
243 #define INV_LRCK_MASK_SFT (0x1 << 5)
244 #define I2S4_FMT_SFT 3
245 #define I2S4_FMT_MASK 0x1
246 #define I2S4_FMT_MASK_SFT (0x1 << 3)
247 #define I2S4_WLEN_SFT 1
248 #define I2S4_WLEN_MASK 0x1
249 #define I2S4_WLEN_MASK_SFT (0x1 << 1)
250 #define I2S4_EN_SFT 0
251 #define I2S4_EN_MASK 0x1
252 #define I2S4_EN_MASK_SFT (0x1 << 0)
253
254 /* AFE_I2S_CON4 */
255 #define I2S5_LR_SWAP_SFT 31
256 #define I2S5_LR_SWAP_MASK 0x1
257 #define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)
258 #define I2S_LOOPBACK_SFT 20
259 #define I2S_LOOPBACK_MASK 0x1
260 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
261 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
262 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
263 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
264 #define I2S5_32BIT_EN_SFT 13
265 #define I2S5_32BIT_EN_MASK 0x1
266 #define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)
267 #define I2S5_HD_EN_SFT 12
268 #define I2S5_HD_EN_MASK 0x1
269 #define I2S5_HD_EN_MASK_SFT (0x1 << 12)
270 #define I2S5_OUT_MODE_SFT 8
271 #define I2S5_OUT_MODE_MASK 0xf
272 #define I2S5_OUT_MODE_MASK_SFT (0xf << 8)
273 #define INV_LRCK_SFT 5
274 #define INV_LRCK_MASK 0x1
275 #define INV_LRCK_MASK_SFT (0x1 << 5)
276 #define I2S5_FMT_SFT 3
277 #define I2S5_FMT_MASK 0x1
278 #define I2S5_FMT_MASK_SFT (0x1 << 3)
279 #define I2S5_WLEN_SFT 1
280 #define I2S5_WLEN_MASK 0x1
281 #define I2S5_WLEN_MASK_SFT (0x1 << 1)
282 #define I2S5_EN_SFT 0
283 #define I2S5_EN_MASK 0x1
284 #define I2S5_EN_MASK_SFT (0x1 << 0)
285
286 /* AFE_CONNSYS_I2S_CON */
287 #define BCK_NEG_EG_LATCH_SFT 30
288 #define BCK_NEG_EG_LATCH_MASK 0x1
289 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
290 #define BCK_INV_SFT 29
291 #define BCK_INV_MASK 0x1
292 #define BCK_INV_MASK_SFT (0x1 << 29)
293 #define I2SIN_PAD_SEL_SFT 28
294 #define I2SIN_PAD_SEL_MASK 0x1
295 #define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
296 #define I2S_LOOPBACK_SFT 20
297 #define I2S_LOOPBACK_MASK 0x1
298 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
299 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
300 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
301 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
302 #define I2S_MODE_SFT 8
303 #define I2S_MODE_MASK 0xf
304 #define I2S_MODE_MASK_SFT (0xf << 8)
305 #define INV_PAD_CTRL_SFT 7
306 #define INV_PAD_CTRL_MASK 0x1
307 #define INV_PAD_CTRL_MASK_SFT (0x1 << 7)
308 #define I2S_BYPSRC_SFT 6
309 #define I2S_BYPSRC_MASK 0x1
310 #define I2S_BYPSRC_MASK_SFT (0x1 << 6)
311 #define INV_LRCK_SFT 5
312 #define INV_LRCK_MASK 0x1
313 #define INV_LRCK_MASK_SFT (0x1 << 5)
314 #define I2S_FMT_SFT 3
315 #define I2S_FMT_MASK 0x1
316 #define I2S_FMT_MASK_SFT (0x1 << 3)
317 #define I2S_SRC_SFT 2
318 #define I2S_SRC_MASK 0x1
319 #define I2S_SRC_MASK_SFT (0x1 << 2)
320 #define I2S_WLEN_SFT 1
321 #define I2S_WLEN_MASK 0x1
322 #define I2S_WLEN_MASK_SFT (0x1 << 1)
323 #define I2S_EN_SFT 0
324 #define I2S_EN_MASK 0x1
325 #define I2S_EN_MASK_SFT (0x1 << 0)
326
327 /* AFE_I2S_CON6 */
328 #define BCK_NEG_EG_LATCH_SFT 30
329 #define BCK_NEG_EG_LATCH_MASK 0x1
330 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
331 #define BCK_INV_SFT 29
332 #define BCK_INV_MASK 0x1
333 #define BCK_INV_MASK_SFT (0x1 << 29)
334 #define I2S6_LOOPBACK_SFT 20
335 #define I2S6_LOOPBACK_MASK 0x1
336 #define I2S6_LOOPBACK_MASK_SFT (0x1 << 20)
337 #define I2S6_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
338 #define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
339 #define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
340 #define I2S6_HD_EN_SFT 12
341 #define I2S6_HD_EN_MASK 0x1
342 #define I2S6_HD_EN_MASK_SFT (0x1 << 12)
343 #define I2S6_OUT_MODE_SFT 8
344 #define I2S6_OUT_MODE_MASK 0xf
345 #define I2S6_OUT_MODE_MASK_SFT (0xf << 8)
346 #define I2S6_BYPSRC_SFT 6
347 #define I2S6_BYPSRC_MASK 0x1
348 #define I2S6_BYPSRC_MASK_SFT (0x1 << 6)
349 #define INV_LRCK_SFT 5
350 #define INV_LRCK_MASK 0x1
351 #define INV_LRCK_MASK_SFT (0x1 << 5)
352 #define I2S6_FMT_SFT 3
353 #define I2S6_FMT_MASK 0x1
354 #define I2S6_FMT_MASK_SFT (0x1 << 3)
355 #define I2S6_SRC_SFT 2
356 #define I2S6_SRC_MASK 0x1
357 #define I2S6_SRC_MASK_SFT (0x1 << 2)
358 #define I2S6_WLEN_SFT 1
359 #define I2S6_WLEN_MASK 0x1
360 #define I2S6_WLEN_MASK_SFT (0x1 << 1)
361 #define I2S6_EN_SFT 0
362 #define I2S6_EN_MASK 0x1
363 #define I2S6_EN_MASK_SFT (0x1 << 0)
364
365 /* AFE_I2S_CON7 */
366 #define I2S7_LR_SWAP_SFT 31
367 #define I2S7_LR_SWAP_MASK 0x1
368 #define I2S7_LR_SWAP_MASK_SFT (0x1 << 31)
369 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
370 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
371 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
372 #define I2S7_32BIT_EN_SFT 13
373 #define I2S7_32BIT_EN_MASK 0x1
374 #define I2S7_32BIT_EN_MASK_SFT (0x1 << 13)
375 #define I2S7_HD_EN_SFT 12
376 #define I2S7_HD_EN_MASK 0x1
377 #define I2S7_HD_EN_MASK_SFT (0x1 << 12)
378 #define I2S7_OUT_MODE_SFT 8
379 #define I2S7_OUT_MODE_MASK 0xf
380 #define I2S7_OUT_MODE_MASK_SFT (0xf << 8)
381 #define INV_LRCK_SFT 5
382 #define INV_LRCK_MASK 0x1
383 #define INV_LRCK_MASK_SFT (0x1 << 5)
384 #define I2S7_FMT_SFT 3
385 #define I2S7_FMT_MASK 0x1
386 #define I2S7_FMT_MASK_SFT (0x1 << 3)
387 #define I2S7_WLEN_SFT 1
388 #define I2S7_WLEN_MASK 0x1
389 #define I2S7_WLEN_MASK_SFT (0x1 << 1)
390 #define I2S7_EN_SFT 0
391 #define I2S7_EN_MASK 0x1
392 #define I2S7_EN_MASK_SFT (0x1 << 0)
393
394 /* AFE_I2S_CON8 */
395 #define BCK_NEG_EG_LATCH_SFT 30
396 #define BCK_NEG_EG_LATCH_MASK 0x1
397 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
398 #define BCK_INV_SFT 29
399 #define BCK_INV_MASK 0x1
400 #define BCK_INV_MASK_SFT (0x1 << 29)
401 #define I2S8_LOOPBACK_SFT 20
402 #define I2S8_LOOPBACK_MASK 0x1
403 #define I2S8_LOOPBACK_MASK_SFT (0x1 << 20)
404 #define I2S8_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
405 #define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
406 #define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
407 #define I2S8_HD_EN_SFT 12
408 #define I2S8_HD_EN_MASK 0x1
409 #define I2S8_HD_EN_MASK_SFT (0x1 << 12)
410 #define I2S8_OUT_MODE_SFT 8
411 #define I2S8_OUT_MODE_MASK 0xf
412 #define I2S8_OUT_MODE_MASK_SFT (0xf << 8)
413 #define I2S8_BYPSRC_SFT 6
414 #define I2S8_BYPSRC_MASK 0x1
415 #define I2S8_BYPSRC_MASK_SFT (0x1 << 6)
416 #define INV_LRCK_SFT 5
417 #define INV_LRCK_MASK 0x1
418 #define INV_LRCK_MASK_SFT (0x1 << 5)
419 #define I2S8_FMT_SFT 3
420 #define I2S8_FMT_MASK 0x1
421 #define I2S8_FMT_MASK_SFT (0x1 << 3)
422 #define I2S8_SRC_SFT 2
423 #define I2S8_SRC_MASK 0x1
424 #define I2S8_SRC_MASK_SFT (0x1 << 2)
425 #define I2S8_WLEN_SFT 1
426 #define I2S8_WLEN_MASK 0x1
427 #define I2S8_WLEN_MASK_SFT (0x1 << 1)
428 #define I2S8_EN_SFT 0
429 #define I2S8_EN_MASK 0x1
430 #define I2S8_EN_MASK_SFT (0x1 << 0)
431
432 /* AFE_I2S_CON9 */
433 #define I2S9_LR_SWAP_SFT 31
434 #define I2S9_LR_SWAP_MASK 0x1
435 #define I2S9_LR_SWAP_MASK_SFT (0x1 << 31)
436 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
437 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
438 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
439 #define I2S9_32BIT_EN_SFT 13
440 #define I2S9_32BIT_EN_MASK 0x1
441 #define I2S9_32BIT_EN_MASK_SFT (0x1 << 13)
442 #define I2S9_HD_EN_SFT 12
443 #define I2S9_HD_EN_MASK 0x1
444 #define I2S9_HD_EN_MASK_SFT (0x1 << 12)
445 #define I2S9_OUT_MODE_SFT 8
446 #define I2S9_OUT_MODE_MASK 0xf
447 #define I2S9_OUT_MODE_MASK_SFT (0xf << 8)
448 #define INV_LRCK_SFT 5
449 #define INV_LRCK_MASK 0x1
450 #define INV_LRCK_MASK_SFT (0x1 << 5)
451 #define I2S9_FMT_SFT 3
452 #define I2S9_FMT_MASK 0x1
453 #define I2S9_FMT_MASK_SFT (0x1 << 3)
454 #define I2S9_WLEN_SFT 1
455 #define I2S9_WLEN_MASK 0x1
456 #define I2S9_WLEN_MASK_SFT (0x1 << 1)
457 #define I2S9_EN_SFT 0
458 #define I2S9_EN_MASK 0x1
459 #define I2S9_EN_MASK_SFT (0x1 << 0)
460
461 /* AFE_ASRC_2CH_CON2 */
462 #define CHSET_O16BIT_SFT 19
463 #define CHSET_O16BIT_MASK 0x1
464 #define CHSET_O16BIT_MASK_SFT (0x1 << 19)
465 #define CHSET_CLR_IIR_HISTORY_SFT 17
466 #define CHSET_CLR_IIR_HISTORY_MASK 0x1
467 #define CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)
468 #define CHSET_IS_MONO_SFT 16
469 #define CHSET_IS_MONO_MASK 0x1
470 #define CHSET_IS_MONO_MASK_SFT (0x1 << 16)
471 #define CHSET_IIR_EN_SFT 11
472 #define CHSET_IIR_EN_MASK 0x1
473 #define CHSET_IIR_EN_MASK_SFT (0x1 << 11)
474 #define CHSET_IIR_STAGE_SFT 8
475 #define CHSET_IIR_STAGE_MASK 0x7
476 #define CHSET_IIR_STAGE_MASK_SFT (0x7 << 8)
477 #define CHSET_STR_CLR_SFT 5
478 #define CHSET_STR_CLR_MASK 0x1
479 #define CHSET_STR_CLR_MASK_SFT (0x1 << 5)
480 #define CHSET_ON_SFT 2
481 #define CHSET_ON_MASK 0x1
482 #define CHSET_ON_MASK_SFT (0x1 << 2)
483 #define COEFF_SRAM_CTRL_SFT 1
484 #define COEFF_SRAM_CTRL_MASK 0x1
485 #define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
486 #define ASM_ON_SFT 0
487 #define ASM_ON_MASK 0x1
488 #define ASM_ON_MASK_SFT (0x1 << 0)
489
490 /* AFE_GAIN1_CON0 */
491 #define GAIN1_SAMPLE_PER_STEP_SFT 8
492 #define GAIN1_SAMPLE_PER_STEP_MASK 0xff
493 #define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)
494 #define GAIN1_MODE_SFT 4
495 #define GAIN1_MODE_MASK 0xf
496 #define GAIN1_MODE_MASK_SFT (0xf << 4)
497 #define GAIN1_ON_SFT 0
498 #define GAIN1_ON_MASK 0x1
499 #define GAIN1_ON_MASK_SFT (0x1 << 0)
500
501 /* AFE_GAIN1_CON1 */
502 #define GAIN1_TARGET_SFT 0
503 #define GAIN1_TARGET_MASK 0xfffffff
504 #define GAIN1_TARGET_MASK_SFT (0xfffffff << 0)
505
506 /* AFE_GAIN2_CON0 */
507 #define GAIN2_SAMPLE_PER_STEP_SFT 8
508 #define GAIN2_SAMPLE_PER_STEP_MASK 0xff
509 #define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)
510 #define GAIN2_MODE_SFT 4
511 #define GAIN2_MODE_MASK 0xf
512 #define GAIN2_MODE_MASK_SFT (0xf << 4)
513 #define GAIN2_ON_SFT 0
514 #define GAIN2_ON_MASK 0x1
515 #define GAIN2_ON_MASK_SFT (0x1 << 0)
516
517 /* AFE_GAIN2_CON1 */
518 #define GAIN2_TARGET_SFT 0
519 #define GAIN2_TARGET_MASK 0xfffffff
520 #define GAIN2_TARGET_MASK_SFT (0xfffffff << 0)
521
522 /* AFE_GAIN1_CUR */
523 #define AFE_GAIN1_CUR_SFT 0
524 #define AFE_GAIN1_CUR_MASK 0xfffffff
525 #define AFE_GAIN1_CUR_MASK_SFT (0xfffffff << 0)
526
527 /* AFE_GAIN2_CUR */
528 #define AFE_GAIN2_CUR_SFT 0
529 #define AFE_GAIN2_CUR_MASK 0xfffffff
530 #define AFE_GAIN2_CUR_MASK_SFT (0xfffffff << 0)
531
532 /* PCM_INTF_CON1 */
533 #define PCM_FIX_VALUE_SEL_SFT 31
534 #define PCM_FIX_VALUE_SEL_MASK 0x1
535 #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
536 #define PCM_BUFFER_LOOPBACK_SFT 30
537 #define PCM_BUFFER_LOOPBACK_MASK 0x1
538 #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
539 #define PCM_PARALLEL_LOOPBACK_SFT 29
540 #define PCM_PARALLEL_LOOPBACK_MASK 0x1
541 #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
542 #define PCM_SERIAL_LOOPBACK_SFT 28
543 #define PCM_SERIAL_LOOPBACK_MASK 0x1
544 #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
545 #define PCM_DAI_PCM_LOOPBACK_SFT 27
546 #define PCM_DAI_PCM_LOOPBACK_MASK 0x1
547 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
548 #define PCM_I2S_PCM_LOOPBACK_SFT 26
549 #define PCM_I2S_PCM_LOOPBACK_MASK 0x1
550 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
551 #define PCM_SYNC_DELSEL_SFT 25
552 #define PCM_SYNC_DELSEL_MASK 0x1
553 #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
554 #define PCM_TX_LR_SWAP_SFT 24
555 #define PCM_TX_LR_SWAP_MASK 0x1
556 #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
557 #define PCM_SYNC_OUT_INV_SFT 23
558 #define PCM_SYNC_OUT_INV_MASK 0x1
559 #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
560 #define PCM_BCLK_OUT_INV_SFT 22
561 #define PCM_BCLK_OUT_INV_MASK 0x1
562 #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
563 #define PCM_SYNC_IN_INV_SFT 21
564 #define PCM_SYNC_IN_INV_MASK 0x1
565 #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
566 #define PCM_BCLK_IN_INV_SFT 20
567 #define PCM_BCLK_IN_INV_MASK 0x1
568 #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
569 #define PCM_TX_LCH_RPT_SFT 19
570 #define PCM_TX_LCH_RPT_MASK 0x1
571 #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
572 #define PCM_VBT_16K_MODE_SFT 18
573 #define PCM_VBT_16K_MODE_MASK 0x1
574 #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
575 #define PCM_EXT_MODEM_SFT 17
576 #define PCM_EXT_MODEM_MASK 0x1
577 #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
578 #define PCM_24BIT_SFT 16
579 #define PCM_24BIT_MASK 0x1
580 #define PCM_24BIT_MASK_SFT (0x1 << 16)
581 #define PCM_WLEN_SFT 14
582 #define PCM_WLEN_MASK 0x3
583 #define PCM_WLEN_MASK_SFT (0x3 << 14)
584 #define PCM_SYNC_LENGTH_SFT 9
585 #define PCM_SYNC_LENGTH_MASK 0x1f
586 #define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)
587 #define PCM_SYNC_TYPE_SFT 8
588 #define PCM_SYNC_TYPE_MASK 0x1
589 #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
590 #define PCM_BT_MODE_SFT 7
591 #define PCM_BT_MODE_MASK 0x1
592 #define PCM_BT_MODE_MASK_SFT (0x1 << 7)
593 #define PCM_BYP_ASRC_SFT 6
594 #define PCM_BYP_ASRC_MASK 0x1
595 #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
596 #define PCM_SLAVE_SFT 5
597 #define PCM_SLAVE_MASK 0x1
598 #define PCM_SLAVE_MASK_SFT (0x1 << 5)
599 #define PCM_MODE_SFT 3
600 #define PCM_MODE_MASK 0x3
601 #define PCM_MODE_MASK_SFT (0x3 << 3)
602 #define PCM_FMT_SFT 1
603 #define PCM_FMT_MASK 0x3
604 #define PCM_FMT_MASK_SFT (0x3 << 1)
605 #define PCM_EN_SFT 0
606 #define PCM_EN_MASK 0x1
607 #define PCM_EN_MASK_SFT (0x1 << 0)
608
609 /* PCM_INTF_CON2 */
610 #define PCM1_TX_FIFO_OV_SFT 31
611 #define PCM1_TX_FIFO_OV_MASK 0x1
612 #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
613 #define PCM1_RX_FIFO_OV_SFT 30
614 #define PCM1_RX_FIFO_OV_MASK 0x1
615 #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
616 #define PCM2_TX_FIFO_OV_SFT 29
617 #define PCM2_TX_FIFO_OV_MASK 0x1
618 #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
619 #define PCM2_RX_FIFO_OV_SFT 28
620 #define PCM2_RX_FIFO_OV_MASK 0x1
621 #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
622 #define PCM1_SYNC_GLITCH_SFT 27
623 #define PCM1_SYNC_GLITCH_MASK 0x1
624 #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
625 #define PCM2_SYNC_GLITCH_SFT 26
626 #define PCM2_SYNC_GLITCH_MASK 0x1
627 #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
628 #define TX3_RCH_DBG_MODE_SFT 17
629 #define TX3_RCH_DBG_MODE_MASK 0x1
630 #define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)
631 #define PCM1_PCM2_LOOPBACK_SFT 16
632 #define PCM1_PCM2_LOOPBACK_MASK 0x1
633 #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)
634 #define DAI_PCM_LOOPBACK_CH_SFT 14
635 #define DAI_PCM_LOOPBACK_CH_MASK 0x3
636 #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14)
637 #define I2S_PCM_LOOPBACK_CH_SFT 12
638 #define I2S_PCM_LOOPBACK_CH_MASK 0x3
639 #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12)
640 #define TX_FIX_VALUE_SFT 0
641 #define TX_FIX_VALUE_MASK 0xff
642 #define TX_FIX_VALUE_MASK_SFT (0xff << 0)
643
644 /* PCM2_INTF_CON */
645 #define PCM2_TX_FIX_VALUE_SFT 24
646 #define PCM2_TX_FIX_VALUE_MASK 0xff
647 #define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)
648 #define PCM2_FIX_VALUE_SEL_SFT 23
649 #define PCM2_FIX_VALUE_SEL_MASK 0x1
650 #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
651 #define PCM2_BUFFER_LOOPBACK_SFT 22
652 #define PCM2_BUFFER_LOOPBACK_MASK 0x1
653 #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
654 #define PCM2_PARALLEL_LOOPBACK_SFT 21
655 #define PCM2_PARALLEL_LOOPBACK_MASK 0x1
656 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
657 #define PCM2_SERIAL_LOOPBACK_SFT 20
658 #define PCM2_SERIAL_LOOPBACK_MASK 0x1
659 #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
660 #define PCM2_DAI_PCM_LOOPBACK_SFT 19
661 #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
662 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
663 #define PCM2_I2S_PCM_LOOPBACK_SFT 18
664 #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
665 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
666 #define PCM2_SYNC_DELSEL_SFT 17
667 #define PCM2_SYNC_DELSEL_MASK 0x1
668 #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
669 #define PCM2_TX_LR_SWAP_SFT 16
670 #define PCM2_TX_LR_SWAP_MASK 0x1
671 #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
672 #define PCM2_SYNC_IN_INV_SFT 15
673 #define PCM2_SYNC_IN_INV_MASK 0x1
674 #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
675 #define PCM2_BCLK_IN_INV_SFT 14
676 #define PCM2_BCLK_IN_INV_MASK 0x1
677 #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
678 #define PCM2_TX_LCH_RPT_SFT 13
679 #define PCM2_TX_LCH_RPT_MASK 0x1
680 #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
681 #define PCM2_VBT_16K_MODE_SFT 12
682 #define PCM2_VBT_16K_MODE_MASK 0x1
683 #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
684 #define PCM2_LOOPBACK_CH_SEL_SFT 10
685 #define PCM2_LOOPBACK_CH_SEL_MASK 0x3
686 #define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)
687 #define PCM2_TX2_BT_MODE_SFT 8
688 #define PCM2_TX2_BT_MODE_MASK 0x1
689 #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
690 #define PCM2_BT_MODE_SFT 7
691 #define PCM2_BT_MODE_MASK 0x1
692 #define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
693 #define PCM2_AFIFO_SFT 6
694 #define PCM2_AFIFO_MASK 0x1
695 #define PCM2_AFIFO_MASK_SFT (0x1 << 6)
696 #define PCM2_WLEN_SFT 5
697 #define PCM2_WLEN_MASK 0x1
698 #define PCM2_WLEN_MASK_SFT (0x1 << 5)
699 #define PCM2_MODE_SFT 3
700 #define PCM2_MODE_MASK 0x3
701 #define PCM2_MODE_MASK_SFT (0x3 << 3)
702 #define PCM2_FMT_SFT 1
703 #define PCM2_FMT_MASK 0x3
704 #define PCM2_FMT_MASK_SFT (0x3 << 1)
705 #define PCM2_EN_SFT 0
706 #define PCM2_EN_MASK 0x1
707 #define PCM2_EN_MASK_SFT (0x1 << 0)
708
709 /* AFE_ADDA_MTKAIF_CFG0 */
710 #define MTKAIF_RXIF_CLKINV_ADC_SFT 31
711 #define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1
712 #define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)
713 #define MTKAIF_RXIF_BYPASS_SRC_SFT 17
714 #define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1
715 #define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
716 #define MTKAIF_RXIF_PROTOCOL2_SFT 16
717 #define MTKAIF_RXIF_PROTOCOL2_MASK 0x1
718 #define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
719 #define MTKAIF_TXIF_BYPASS_SRC_SFT 5
720 #define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1
721 #define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
722 #define MTKAIF_TXIF_PROTOCOL2_SFT 4
723 #define MTKAIF_TXIF_PROTOCOL2_MASK 0x1
724 #define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
725 #define MTKAIF_TXIF_8TO5_SFT 2
726 #define MTKAIF_TXIF_8TO5_MASK 0x1
727 #define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)
728 #define MTKAIF_RXIF_8TO5_SFT 1
729 #define MTKAIF_RXIF_8TO5_MASK 0x1
730 #define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)
731 #define MTKAIF_IF_LOOPBACK1_SFT 0
732 #define MTKAIF_IF_LOOPBACK1_MASK 0x1
733 #define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)
734
735 /* AFE_ADDA_MTKAIF_RX_CFG2 */
736 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16
737 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
738 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)
739 #define MTKAIF_RXIF_DELAY_CYCLE_SFT 12
740 #define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf
741 #define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)
742 #define MTKAIF_RXIF_DELAY_DATA_SFT 8
743 #define MTKAIF_RXIF_DELAY_DATA_MASK 0x1
744 #define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
745 #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4
746 #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
747 #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
748
749 /* AFE_ADDA_DL_SRC2_CON0 */
750 #define DL_2_INPUT_MODE_CTL_SFT 28
751 #define DL_2_INPUT_MODE_CTL_MASK 0xf
752 #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)
753 #define DL_2_CH1_SATURATION_EN_CTL_SFT 27
754 #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
755 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
756 #define DL_2_CH2_SATURATION_EN_CTL_SFT 26
757 #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
758 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
759 #define DL_2_OUTPUT_SEL_CTL_SFT 24
760 #define DL_2_OUTPUT_SEL_CTL_MASK 0x3
761 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)
762 #define DL_2_FADEIN_0START_EN_SFT 16
763 #define DL_2_FADEIN_0START_EN_MASK 0x3
764 #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
765 #define DL_DISABLE_HW_CG_CTL_SFT 15
766 #define DL_DISABLE_HW_CG_CTL_MASK 0x1
767 #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
768 #define C_DATA_EN_SEL_CTL_PRE_SFT 14
769 #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
770 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
771 #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13
772 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
773 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
774 #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12
775 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
776 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
777 #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11
778 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
779 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
780 #define DL2_ARAMPSP_CTL_PRE_SFT 9
781 #define DL2_ARAMPSP_CTL_PRE_MASK 0x3
782 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)
783 #define DL_2_IIRMODE_CTL_PRE_SFT 6
784 #define DL_2_IIRMODE_CTL_PRE_MASK 0x7
785 #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)
786 #define DL_2_VOICE_MODE_CTL_PRE_SFT 5
787 #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
788 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
789 #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4
790 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
791 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
792 #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3
793 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
794 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
795 #define DL_2_IIR_ON_CTL_PRE_SFT 2
796 #define DL_2_IIR_ON_CTL_PRE_MASK 0x1
797 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
798 #define DL_2_GAIN_ON_CTL_PRE_SFT 1
799 #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
800 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
801 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
802 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
803 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
804
805 /* AFE_ADDA_DL_SRC2_CON1 */
806 #define DL_2_GAIN_CTL_PRE_SFT 16
807 #define DL_2_GAIN_CTL_PRE_MASK 0xffff
808 #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)
809 #define DL_2_GAIN_MODE_CTL_SFT 0
810 #define DL_2_GAIN_MODE_CTL_MASK 0x1
811 #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
812
813 /* AFE_ADDA_UL_SRC_CON0 */
814 #define ULCF_CFG_EN_CTL_SFT 31
815 #define ULCF_CFG_EN_CTL_MASK 0x1
816 #define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
817 #define UL_DMIC_PHASE_SEL_CH1_SFT 27
818 #define UL_DMIC_PHASE_SEL_CH1_MASK 0x7
819 #define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)
820 #define UL_DMIC_PHASE_SEL_CH2_SFT 24
821 #define UL_DMIC_PHASE_SEL_CH2_MASK 0x7
822 #define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)
823 #define UL_MODE_3P25M_CH2_CTL_SFT 22
824 #define UL_MODE_3P25M_CH2_CTL_MASK 0x1
825 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
826 #define UL_MODE_3P25M_CH1_CTL_SFT 21
827 #define UL_MODE_3P25M_CH1_CTL_MASK 0x1
828 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
829 #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
830 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
831 #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
832 #define UL_AP_DMIC_ON_SFT 16
833 #define UL_AP_DMIC_ON_MASK 0x1
834 #define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)
835 #define DMIC_LOW_POWER_MODE_CTL_SFT 14
836 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
837 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
838 #define UL_DISABLE_HW_CG_CTL_SFT 12
839 #define UL_DISABLE_HW_CG_CTL_MASK 0x1
840 #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
841 #define UL_IIR_ON_TMP_CTL_SFT 10
842 #define UL_IIR_ON_TMP_CTL_MASK 0x1
843 #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
844 #define UL_IIRMODE_CTL_SFT 7
845 #define UL_IIRMODE_CTL_MASK 0x7
846 #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
847 #define DIGMIC_4P33M_SEL_SFT 6
848 #define DIGMIC_4P33M_SEL_MASK 0x1
849 #define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)
850 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
851 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
852 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
853 #define UL_LOOP_BACK_MODE_CTL_SFT 2
854 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
855 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
856 #define UL_SDM_3_LEVEL_CTL_SFT 1
857 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
858 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
859 #define UL_SRC_ON_TMP_CTL_SFT 0
860 #define UL_SRC_ON_TMP_CTL_MASK 0x1
861 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
862
863 /* AFE_ADDA_UL_SRC_CON1 */
864 #define C_DAC_EN_CTL_SFT 27
865 #define C_DAC_EN_CTL_MASK 0x1
866 #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
867 #define C_MUTE_SW_CTL_SFT 26
868 #define C_MUTE_SW_CTL_MASK 0x1
869 #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
870 #define ASDM_SRC_SEL_CTL_SFT 25
871 #define ASDM_SRC_SEL_CTL_MASK 0x1
872 #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
873 #define C_AMP_DIV_CH2_CTL_SFT 21
874 #define C_AMP_DIV_CH2_CTL_MASK 0x7
875 #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
876 #define C_FREQ_DIV_CH2_CTL_SFT 16
877 #define C_FREQ_DIV_CH2_CTL_MASK 0x1f
878 #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
879 #define C_SINE_MODE_CH2_CTL_SFT 12
880 #define C_SINE_MODE_CH2_CTL_MASK 0xf
881 #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
882 #define C_AMP_DIV_CH1_CTL_SFT 9
883 #define C_AMP_DIV_CH1_CTL_MASK 0x7
884 #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
885 #define C_FREQ_DIV_CH1_CTL_SFT 4
886 #define C_FREQ_DIV_CH1_CTL_MASK 0x1f
887 #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
888 #define C_SINE_MODE_CH1_CTL_SFT 0
889 #define C_SINE_MODE_CH1_CTL_MASK 0xf
890 #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
891
892 /* AFE_ADDA_TOP_CON0 */
893 #define C_LOOP_BACK_MODE_CTL_SFT 12
894 #define C_LOOP_BACK_MODE_CTL_MASK 0xf
895 #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)
896 #define ADDA_UL_GAIN_MODE_SFT 8
897 #define ADDA_UL_GAIN_MODE_MASK 0x3
898 #define ADDA_UL_GAIN_MODE_MASK_SFT (0x3 << 8)
899 #define C_EXT_ADC_CTL_SFT 0
900 #define C_EXT_ADC_CTL_MASK 0x1
901 #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
902
903 /* AFE_ADDA_UL_DL_CON0 */
904 #define AFE_ADDA_UL_LR_SWAP_SFT 31
905 #define AFE_ADDA_UL_LR_SWAP_MASK 0x1
906 #define AFE_ADDA_UL_LR_SWAP_MASK_SFT (0x1 << 31)
907 #define AFE_ADDA_CKDIV_RST_SFT 30
908 #define AFE_ADDA_CKDIV_RST_MASK 0x1
909 #define AFE_ADDA_CKDIV_RST_MASK_SFT (0x1 << 30)
910 #define AFE_ADDA_FIFO_AUTO_RST_SFT 29
911 #define AFE_ADDA_FIFO_AUTO_RST_MASK 0x1
912 #define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT (0x1 << 29)
913 #define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT 21
914 #define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK 0x3
915 #define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 21)
916 #define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 20
917 #define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
918 #define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 20)
919 #define AFE_ADDA6_UL_LR_SWAP_SFT 15
920 #define AFE_ADDA6_UL_LR_SWAP_MASK 0x1
921 #define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)
922 #define AFE_ADDA6_CKDIV_RST_SFT 14
923 #define AFE_ADDA6_CKDIV_RST_MASK 0x1
924 #define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)
925 #define AFE_ADDA6_FIFO_AUTO_RST_SFT 13
926 #define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1
927 #define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)
928 #define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT 5
929 #define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK 0x3
930 #define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5)
931 #define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4
932 #define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
933 #define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)
934 #define ADDA_AFE_ON_SFT 0
935 #define ADDA_AFE_ON_MASK 0x1
936 #define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
937
938 /* AFE_SIDETONE_CON0 */
939 #define R_RDY_SFT 30
940 #define R_RDY_MASK 0x1
941 #define R_RDY_MASK_SFT (0x1 << 30)
942 #define W_RDY_SFT 29
943 #define W_RDY_MASK 0x1
944 #define W_RDY_MASK_SFT (0x1 << 29)
945 #define R_W_EN_SFT 25
946 #define R_W_EN_MASK 0x1
947 #define R_W_EN_MASK_SFT (0x1 << 25)
948 #define R_W_SEL_SFT 24
949 #define R_W_SEL_MASK 0x1
950 #define R_W_SEL_MASK_SFT (0x1 << 24)
951 #define SEL_CH2_SFT 23
952 #define SEL_CH2_MASK 0x1
953 #define SEL_CH2_MASK_SFT (0x1 << 23)
954 #define SIDE_TONE_COEFFICIENT_ADDR_SFT 16
955 #define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f
956 #define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)
957 #define SIDE_TONE_COEFFICIENT_SFT 0
958 #define SIDE_TONE_COEFFICIENT_MASK 0xffff
959 #define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)
960
961 /* AFE_SIDETONE_COEFF */
962 #define SIDE_TONE_COEFF_SFT 0
963 #define SIDE_TONE_COEFF_MASK 0xffff
964 #define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)
965
966 /* AFE_SIDETONE_CON1 */
967 #define STF_BYPASS_MODE_SFT 31
968 #define STF_BYPASS_MODE_MASK 0x1
969 #define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)
970 #define STF_BYPASS_MODE_O28_O29_SFT 30
971 #define STF_BYPASS_MODE_O28_O29_MASK 0x1
972 #define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)
973 #define STF_BYPASS_MODE_I2S4_SFT 29
974 #define STF_BYPASS_MODE_I2S4_MASK 0x1
975 #define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)
976 #define STF_BYPASS_MODE_I2S5_SFT 28
977 #define STF_BYPASS_MODE_I2S5_MASK 0x1
978 #define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)
979 #define STF_BYPASS_MODE_DL3_SFT 27
980 #define STF_BYPASS_MODE_DL3_MASK 0x1
981 #define STF_BYPASS_MODE_DL3_MASK_SFT (0x1 << 27)
982 #define STF_BYPASS_MODE_I2S7_SFT 26
983 #define STF_BYPASS_MODE_I2S7_MASK 0x1
984 #define STF_BYPASS_MODE_I2S7_MASK_SFT (0x1 << 26)
985 #define STF_BYPASS_MODE_I2S9_SFT 25
986 #define STF_BYPASS_MODE_I2S9_MASK 0x1
987 #define STF_BYPASS_MODE_I2S9_MASK_SFT (0x1 << 25)
988 #define STF_O19O20_OUT_EN_SEL_SFT 13
989 #define STF_O19O20_OUT_EN_SEL_MASK 0x1
990 #define STF_O19O20_OUT_EN_SEL_MASK_SFT (0x1 << 13)
991 #define STF_SOURCE_FROM_O19O20_SFT 12
992 #define STF_SOURCE_FROM_O19O20_MASK 0x1
993 #define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)
994 #define SIDE_TONE_ON_SFT 8
995 #define SIDE_TONE_ON_MASK 0x1
996 #define SIDE_TONE_ON_MASK_SFT (0x1 << 8)
997 #define SIDE_TONE_HALF_TAP_NUM_SFT 0
998 #define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f
999 #define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0)
1000
1001 /* AFE_SIDETONE_GAIN */
1002 #define POSITIVE_GAIN_SFT 16
1003 #define POSITIVE_GAIN_MASK 0x7
1004 #define POSITIVE_GAIN_MASK_SFT (0x7 << 16)
1005 #define SIDE_TONE_GAIN_SFT 0
1006 #define SIDE_TONE_GAIN_MASK 0xffff
1007 #define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)
1008
1009 /* AFE_ADDA_DL_SDM_DCCOMP_CON */
1010 #define USE_3RD_SDM_SFT 28
1011 #define USE_3RD_SDM_MASK 0x1
1012 #define USE_3RD_SDM_MASK_SFT (0x1 << 28)
1013 #define DL_FIFO_START_POINT_SFT 24
1014 #define DL_FIFO_START_POINT_MASK 0x7
1015 #define DL_FIFO_START_POINT_MASK_SFT (0x7 << 24)
1016 #define DL_FIFO_SWAP_SFT 20
1017 #define DL_FIFO_SWAP_MASK 0x1
1018 #define DL_FIFO_SWAP_MASK_SFT (0x1 << 20)
1019 #define C_AUDSDM1ORDSELECT_CTL_SFT 19
1020 #define C_AUDSDM1ORDSELECT_CTL_MASK 0x1
1021 #define C_AUDSDM1ORDSELECT_CTL_MASK_SFT (0x1 << 19)
1022 #define C_SDM7BITSEL_CTL_SFT 18
1023 #define C_SDM7BITSEL_CTL_MASK 0x1
1024 #define C_SDM7BITSEL_CTL_MASK_SFT (0x1 << 18)
1025 #define GAIN_AT_SDM_RST_PRE_CTL_SFT 15
1026 #define GAIN_AT_SDM_RST_PRE_CTL_MASK 0x1
1027 #define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT (0x1 << 15)
1028 #define DL_DCM_AUTO_IDLE_EN_SFT 14
1029 #define DL_DCM_AUTO_IDLE_EN_MASK 0x1
1030 #define DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 14)
1031 #define AFE_DL_SRC_DCM_EN_SFT 13
1032 #define AFE_DL_SRC_DCM_EN_MASK 0x1
1033 #define AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 13)
1034 #define AFE_DL_POST_SRC_DCM_EN_SFT 12
1035 #define AFE_DL_POST_SRC_DCM_EN_MASK 0x1
1036 #define AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 12)
1037 #define AUD_SDM_MONO_SFT 9
1038 #define AUD_SDM_MONO_MASK 0x1
1039 #define AUD_SDM_MONO_MASK_SFT (0x1 << 9)
1040 #define AUD_DC_COMP_EN_SFT 8
1041 #define AUD_DC_COMP_EN_MASK 0x1
1042 #define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)
1043 #define ATTGAIN_CTL_SFT 0
1044 #define ATTGAIN_CTL_MASK 0x3f
1045 #define ATTGAIN_CTL_MASK_SFT (0x3f << 0)
1046
1047 /* AFE_SINEGEN_CON0 */
1048 #define DAC_EN_SFT 26
1049 #define DAC_EN_MASK 0x1
1050 #define DAC_EN_MASK_SFT (0x1 << 26)
1051 #define MUTE_SW_CH2_SFT 25
1052 #define MUTE_SW_CH2_MASK 0x1
1053 #define MUTE_SW_CH2_MASK_SFT (0x1 << 25)
1054 #define MUTE_SW_CH1_SFT 24
1055 #define MUTE_SW_CH1_MASK 0x1
1056 #define MUTE_SW_CH1_MASK_SFT (0x1 << 24)
1057 #define SINE_MODE_CH2_SFT 20
1058 #define SINE_MODE_CH2_MASK 0xf
1059 #define SINE_MODE_CH2_MASK_SFT (0xf << 20)
1060 #define AMP_DIV_CH2_SFT 17
1061 #define AMP_DIV_CH2_MASK 0x7
1062 #define AMP_DIV_CH2_MASK_SFT (0x7 << 17)
1063 #define FREQ_DIV_CH2_SFT 12
1064 #define FREQ_DIV_CH2_MASK 0x1f
1065 #define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)
1066 #define SINE_MODE_CH1_SFT 8
1067 #define SINE_MODE_CH1_MASK 0xf
1068 #define SINE_MODE_CH1_MASK_SFT (0xf << 8)
1069 #define AMP_DIV_CH1_SFT 5
1070 #define AMP_DIV_CH1_MASK 0x7
1071 #define AMP_DIV_CH1_MASK_SFT (0x7 << 5)
1072 #define FREQ_DIV_CH1_SFT 0
1073 #define FREQ_DIV_CH1_MASK 0x1f
1074 #define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)
1075
1076 /* AFE_SINEGEN_CON2 */
1077 #define INNER_LOOP_BACK_MODE_SFT 0
1078 #define INNER_LOOP_BACK_MODE_MASK 0x3f
1079 #define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0)
1080
1081 /* AFE_HD_ENGEN_ENABLE */
1082 #define AFE_24M_ON_SFT 1
1083 #define AFE_24M_ON_MASK 0x1
1084 #define AFE_24M_ON_MASK_SFT (0x1 << 1)
1085 #define AFE_22M_ON_SFT 0
1086 #define AFE_22M_ON_MASK 0x1
1087 #define AFE_22M_ON_MASK_SFT (0x1 << 0)
1088
1089 /* AFE_ADDA_DL_NLE_FIFO_MON */
1090 #define DL_NLE_FIFO_WBIN_SFT 8
1091 #define DL_NLE_FIFO_WBIN_MASK 0xf
1092 #define DL_NLE_FIFO_WBIN_MASK_SFT (0xf << 8)
1093 #define DL_NLE_FIFO_RBIN_SFT 4
1094 #define DL_NLE_FIFO_RBIN_MASK 0xf
1095 #define DL_NLE_FIFO_RBIN_MASK_SFT (0xf << 4)
1096 #define DL_NLE_FIFO_RDACTIVE_SFT 3
1097 #define DL_NLE_FIFO_RDACTIVE_MASK 0x1
1098 #define DL_NLE_FIFO_RDACTIVE_MASK_SFT (0x1 << 3)
1099 #define DL_NLE_FIFO_STARTRD_SFT 2
1100 #define DL_NLE_FIFO_STARTRD_MASK 0x1
1101 #define DL_NLE_FIFO_STARTRD_MASK_SFT (0x1 << 2)
1102 #define DL_NLE_FIFO_RD_EMPTY_SFT 1
1103 #define DL_NLE_FIFO_RD_EMPTY_MASK 0x1
1104 #define DL_NLE_FIFO_RD_EMPTY_MASK_SFT (0x1 << 1)
1105 #define DL_NLE_FIFO_WR_FULL_SFT 0
1106 #define DL_NLE_FIFO_WR_FULL_MASK 0x1
1107 #define DL_NLE_FIFO_WR_FULL_MASK_SFT (0x1 << 0)
1108
1109 /* AFE_DL1_CON0 */
1110 #define DL1_MODE_SFT 24
1111 #define DL1_MODE_MASK 0xf
1112 #define DL1_MODE_MASK_SFT (0xf << 24)
1113 #define DL1_MINLEN_SFT 20
1114 #define DL1_MINLEN_MASK 0xf
1115 #define DL1_MINLEN_MASK_SFT (0xf << 20)
1116 #define DL1_MAXLEN_SFT 16
1117 #define DL1_MAXLEN_MASK 0xf
1118 #define DL1_MAXLEN_MASK_SFT (0xf << 16)
1119 #define DL1_SW_CLEAR_BUF_EMPTY_SFT 15
1120 #define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1
1121 #define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1122 #define DL1_PBUF_SIZE_SFT 12
1123 #define DL1_PBUF_SIZE_MASK 0x3
1124 #define DL1_PBUF_SIZE_MASK_SFT (0x3 << 12)
1125 #define DL1_MONO_SFT 8
1126 #define DL1_MONO_MASK 0x1
1127 #define DL1_MONO_MASK_SFT (0x1 << 8)
1128 #define DL1_NORMAL_MODE_SFT 5
1129 #define DL1_NORMAL_MODE_MASK 0x1
1130 #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 5)
1131 #define DL1_HALIGN_SFT 4
1132 #define DL1_HALIGN_MASK 0x1
1133 #define DL1_HALIGN_MASK_SFT (0x1 << 4)
1134 #define DL1_HD_MODE_SFT 0
1135 #define DL1_HD_MODE_MASK 0x3
1136 #define DL1_HD_MODE_MASK_SFT (0x3 << 0)
1137
1138 /* AFE_DL2_CON0 */
1139 #define DL2_MODE_SFT 24
1140 #define DL2_MODE_MASK 0xf
1141 #define DL2_MODE_MASK_SFT (0xf << 24)
1142 #define DL2_MINLEN_SFT 20
1143 #define DL2_MINLEN_MASK 0xf
1144 #define DL2_MINLEN_MASK_SFT (0xf << 20)
1145 #define DL2_MAXLEN_SFT 16
1146 #define DL2_MAXLEN_MASK 0xf
1147 #define DL2_MAXLEN_MASK_SFT (0xf << 16)
1148 #define DL2_SW_CLEAR_BUF_EMPTY_SFT 15
1149 #define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1
1150 #define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1151 #define DL2_PBUF_SIZE_SFT 12
1152 #define DL2_PBUF_SIZE_MASK 0x3
1153 #define DL2_PBUF_SIZE_MASK_SFT (0x3 << 12)
1154 #define DL2_MONO_SFT 8
1155 #define DL2_MONO_MASK 0x1
1156 #define DL2_MONO_MASK_SFT (0x1 << 8)
1157 #define DL2_NORMAL_MODE_SFT 5
1158 #define DL2_NORMAL_MODE_MASK 0x1
1159 #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1160 #define DL2_HALIGN_SFT 4
1161 #define DL2_HALIGN_MASK 0x1
1162 #define DL2_HALIGN_MASK_SFT (0x1 << 4)
1163 #define DL2_HD_MODE_SFT 0
1164 #define DL2_HD_MODE_MASK 0x3
1165 #define DL2_HD_MODE_MASK_SFT (0x3 << 0)
1166
1167 /* AFE_DL3_CON0 */
1168 #define DL3_MODE_SFT 24
1169 #define DL3_MODE_MASK 0xf
1170 #define DL3_MODE_MASK_SFT (0xf << 24)
1171 #define DL3_MINLEN_SFT 20
1172 #define DL3_MINLEN_MASK 0xf
1173 #define DL3_MINLEN_MASK_SFT (0xf << 20)
1174 #define DL3_MAXLEN_SFT 16
1175 #define DL3_MAXLEN_MASK 0xf
1176 #define DL3_MAXLEN_MASK_SFT (0xf << 16)
1177 #define DL3_SW_CLEAR_BUF_EMPTY_SFT 15
1178 #define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1
1179 #define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1180 #define DL3_PBUF_SIZE_SFT 12
1181 #define DL3_PBUF_SIZE_MASK 0x3
1182 #define DL3_PBUF_SIZE_MASK_SFT (0x3 << 12)
1183 #define DL3_MONO_SFT 8
1184 #define DL3_MONO_MASK 0x1
1185 #define DL3_MONO_MASK_SFT (0x1 << 8)
1186 #define DL3_NORMAL_MODE_SFT 5
1187 #define DL3_NORMAL_MODE_MASK 0x1
1188 #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 5)
1189 #define DL3_HALIGN_SFT 4
1190 #define DL3_HALIGN_MASK 0x1
1191 #define DL3_HALIGN_MASK_SFT (0x1 << 4)
1192 #define DL3_HD_MODE_SFT 0
1193 #define DL3_HD_MODE_MASK 0x3
1194 #define DL3_HD_MODE_MASK_SFT (0x3 << 0)
1195
1196 /* AFE_DL4_CON0 */
1197 #define DL4_MODE_SFT 24
1198 #define DL4_MODE_MASK 0xf
1199 #define DL4_MODE_MASK_SFT (0xf << 24)
1200 #define DL4_MINLEN_SFT 20
1201 #define DL4_MINLEN_MASK 0xf
1202 #define DL4_MINLEN_MASK_SFT (0xf << 20)
1203 #define DL4_MAXLEN_SFT 16
1204 #define DL4_MAXLEN_MASK 0xf
1205 #define DL4_MAXLEN_MASK_SFT (0xf << 16)
1206 #define DL4_SW_CLEAR_BUF_EMPTY_SFT 15
1207 #define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1
1208 #define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1209 #define DL4_PBUF_SIZE_SFT 12
1210 #define DL4_PBUF_SIZE_MASK 0x3
1211 #define DL4_PBUF_SIZE_MASK_SFT (0x3 << 12)
1212 #define DL4_MONO_SFT 8
1213 #define DL4_MONO_MASK 0x1
1214 #define DL4_MONO_MASK_SFT (0x1 << 8)
1215 #define DL4_NORMAL_MODE_SFT 5
1216 #define DL4_NORMAL_MODE_MASK 0x1
1217 #define DL4_NORMAL_MODE_MASK_SFT (0x1 << 5)
1218 #define DL4_HALIGN_SFT 4
1219 #define DL4_HALIGN_MASK 0x1
1220 #define DL4_HALIGN_MASK_SFT (0x1 << 4)
1221 #define DL4_HD_MODE_SFT 0
1222 #define DL4_HD_MODE_MASK 0x3
1223 #define DL4_HD_MODE_MASK_SFT (0x3 << 0)
1224
1225 /* AFE_DL5_CON0 */
1226 #define DL5_MODE_SFT 24
1227 #define DL5_MODE_MASK 0xf
1228 #define DL5_MODE_MASK_SFT (0xf << 24)
1229 #define DL5_MINLEN_SFT 20
1230 #define DL5_MINLEN_MASK 0xf
1231 #define DL5_MINLEN_MASK_SFT (0xf << 20)
1232 #define DL5_MAXLEN_SFT 16
1233 #define DL5_MAXLEN_MASK 0xf
1234 #define DL5_MAXLEN_MASK_SFT (0xf << 16)
1235 #define DL5_SW_CLEAR_BUF_EMPTY_SFT 15
1236 #define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1
1237 #define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1238 #define DL5_PBUF_SIZE_SFT 12
1239 #define DL5_PBUF_SIZE_MASK 0x3
1240 #define DL5_PBUF_SIZE_MASK_SFT (0x3 << 12)
1241 #define DL5_MONO_SFT 8
1242 #define DL5_MONO_MASK 0x1
1243 #define DL5_MONO_MASK_SFT (0x1 << 8)
1244 #define DL5_NORMAL_MODE_SFT 5
1245 #define DL5_NORMAL_MODE_MASK 0x1
1246 #define DL5_NORMAL_MODE_MASK_SFT (0x1 << 5)
1247 #define DL5_HALIGN_SFT 4
1248 #define DL5_HALIGN_MASK 0x1
1249 #define DL5_HALIGN_MASK_SFT (0x1 << 4)
1250 #define DL5_HD_MODE_SFT 0
1251 #define DL5_HD_MODE_MASK 0x3
1252 #define DL5_HD_MODE_MASK_SFT (0x3 << 0)
1253
1254 /* AFE_DL6_CON0 */
1255 #define DL6_MODE_SFT 24
1256 #define DL6_MODE_MASK 0xf
1257 #define DL6_MODE_MASK_SFT (0xf << 24)
1258 #define DL6_MINLEN_SFT 20
1259 #define DL6_MINLEN_MASK 0xf
1260 #define DL6_MINLEN_MASK_SFT (0xf << 20)
1261 #define DL6_MAXLEN_SFT 16
1262 #define DL6_MAXLEN_MASK 0xf
1263 #define DL6_MAXLEN_MASK_SFT (0xf << 16)
1264 #define DL6_SW_CLEAR_BUF_EMPTY_SFT 15
1265 #define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1
1266 #define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1267 #define DL6_PBUF_SIZE_SFT 12
1268 #define DL6_PBUF_SIZE_MASK 0x3
1269 #define DL6_PBUF_SIZE_MASK_SFT (0x3 << 12)
1270 #define DL6_MONO_SFT 8
1271 #define DL6_MONO_MASK 0x1
1272 #define DL6_MONO_MASK_SFT (0x1 << 8)
1273 #define DL6_NORMAL_MODE_SFT 5
1274 #define DL6_NORMAL_MODE_MASK 0x1
1275 #define DL6_NORMAL_MODE_MASK_SFT (0x1 << 5)
1276 #define DL6_HALIGN_SFT 4
1277 #define DL6_HALIGN_MASK 0x1
1278 #define DL6_HALIGN_MASK_SFT (0x1 << 4)
1279 #define DL6_HD_MODE_SFT 0
1280 #define DL6_HD_MODE_MASK 0x3
1281 #define DL6_HD_MODE_MASK_SFT (0x3 << 0)
1282
1283 /* AFE_DL7_CON0 */
1284 #define DL7_MODE_SFT 24
1285 #define DL7_MODE_MASK 0xf
1286 #define DL7_MODE_MASK_SFT (0xf << 24)
1287 #define DL7_MINLEN_SFT 20
1288 #define DL7_MINLEN_MASK 0xf
1289 #define DL7_MINLEN_MASK_SFT (0xf << 20)
1290 #define DL7_MAXLEN_SFT 16
1291 #define DL7_MAXLEN_MASK 0xf
1292 #define DL7_MAXLEN_MASK_SFT (0xf << 16)
1293 #define DL7_SW_CLEAR_BUF_EMPTY_SFT 15
1294 #define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1
1295 #define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1296 #define DL7_PBUF_SIZE_SFT 12
1297 #define DL7_PBUF_SIZE_MASK 0x3
1298 #define DL7_PBUF_SIZE_MASK_SFT (0x3 << 12)
1299 #define DL7_MONO_SFT 8
1300 #define DL7_MONO_MASK 0x1
1301 #define DL7_MONO_MASK_SFT (0x1 << 8)
1302 #define DL7_NORMAL_MODE_SFT 5
1303 #define DL7_NORMAL_MODE_MASK 0x1
1304 #define DL7_NORMAL_MODE_MASK_SFT (0x1 << 5)
1305 #define DL7_HALIGN_SFT 4
1306 #define DL7_HALIGN_MASK 0x1
1307 #define DL7_HALIGN_MASK_SFT (0x1 << 4)
1308 #define DL7_HD_MODE_SFT 0
1309 #define DL7_HD_MODE_MASK 0x3
1310 #define DL7_HD_MODE_MASK_SFT (0x3 << 0)
1311
1312 /* AFE_DL8_CON0 */
1313 #define DL8_MODE_SFT 24
1314 #define DL8_MODE_MASK 0xf
1315 #define DL8_MODE_MASK_SFT (0xf << 24)
1316 #define DL8_MINLEN_SFT 20
1317 #define DL8_MINLEN_MASK 0xf
1318 #define DL8_MINLEN_MASK_SFT (0xf << 20)
1319 #define DL8_MAXLEN_SFT 16
1320 #define DL8_MAXLEN_MASK 0xf
1321 #define DL8_MAXLEN_MASK_SFT (0xf << 16)
1322 #define DL8_SW_CLEAR_BUF_EMPTY_SFT 15
1323 #define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1
1324 #define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1325 #define DL8_PBUF_SIZE_SFT 12
1326 #define DL8_PBUF_SIZE_MASK 0x3
1327 #define DL8_PBUF_SIZE_MASK_SFT (0x3 << 12)
1328 #define DL8_MONO_SFT 8
1329 #define DL8_MONO_MASK 0x1
1330 #define DL8_MONO_MASK_SFT (0x1 << 8)
1331 #define DL8_NORMAL_MODE_SFT 5
1332 #define DL8_NORMAL_MODE_MASK 0x1
1333 #define DL8_NORMAL_MODE_MASK_SFT (0x1 << 5)
1334 #define DL8_HALIGN_SFT 4
1335 #define DL8_HALIGN_MASK 0x1
1336 #define DL8_HALIGN_MASK_SFT (0x1 << 4)
1337 #define DL8_HD_MODE_SFT 0
1338 #define DL8_HD_MODE_MASK 0x3
1339 #define DL8_HD_MODE_MASK_SFT (0x3 << 0)
1340
1341 /* AFE_DL9_CON0 */
1342 #define DL9_MODE_SFT 24
1343 #define DL9_MODE_MASK 0xf
1344 #define DL9_MODE_MASK_SFT (0xf << 24)
1345 #define DL9_MINLEN_SFT 20
1346 #define DL9_MINLEN_MASK 0xf
1347 #define DL9_MINLEN_MASK_SFT (0xf << 20)
1348 #define DL9_MAXLEN_SFT 16
1349 #define DL9_MAXLEN_MASK 0xf
1350 #define DL9_MAXLEN_MASK_SFT (0xf << 16)
1351 #define DL9_SW_CLEAR_BUF_EMPTY_SFT 15
1352 #define DL9_SW_CLEAR_BUF_EMPTY_MASK 0x1
1353 #define DL9_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1354 #define DL9_PBUF_SIZE_SFT 12
1355 #define DL9_PBUF_SIZE_MASK 0x3
1356 #define DL9_PBUF_SIZE_MASK_SFT (0x3 << 12)
1357 #define DL9_MONO_SFT 8
1358 #define DL9_MONO_MASK 0x1
1359 #define DL9_MONO_MASK_SFT (0x1 << 8)
1360 #define DL9_NORMAL_MODE_SFT 5
1361 #define DL9_NORMAL_MODE_MASK 0x1
1362 #define DL9_NORMAL_MODE_MASK_SFT (0x1 << 5)
1363 #define DL9_HALIGN_SFT 4
1364 #define DL9_HALIGN_MASK 0x1
1365 #define DL9_HALIGN_MASK_SFT (0x1 << 4)
1366 #define DL9_HD_MODE_SFT 0
1367 #define DL9_HD_MODE_MASK 0x3
1368 #define DL9_HD_MODE_MASK_SFT (0x3 << 0)
1369
1370 /* AFE_DL12_CON0 */
1371 #define DL12_MODE_SFT 24
1372 #define DL12_MODE_MASK 0xf
1373 #define DL12_MODE_MASK_SFT (0xf << 24)
1374 #define DL12_MINLEN_SFT 20
1375 #define DL12_MINLEN_MASK 0xf
1376 #define DL12_MINLEN_MASK_SFT (0xf << 20)
1377 #define DL12_MAXLEN_SFT 16
1378 #define DL12_MAXLEN_MASK 0xf
1379 #define DL12_MAXLEN_MASK_SFT (0xf << 16)
1380 #define DL12_SW_CLEAR_BUF_EMPTY_SFT 15
1381 #define DL12_SW_CLEAR_BUF_EMPTY_MASK 0x1
1382 #define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1383 #define DL12_PBUF_SIZE_SFT 12
1384 #define DL12_PBUF_SIZE_MASK 0x3
1385 #define DL12_PBUF_SIZE_MASK_SFT (0x3 << 12)
1386 #define DL12_4CH_EN_SFT 11
1387 #define DL12_4CH_EN_MASK 0x1
1388 #define DL12_4CH_EN_MASK_SFT (0x1 << 11)
1389 #define DL12_MONO_SFT 8
1390 #define DL12_MONO_MASK 0x1
1391 #define DL12_MONO_MASK_SFT (0x1 << 8)
1392 #define DL12_NORMAL_MODE_SFT 5
1393 #define DL12_NORMAL_MODE_MASK 0x1
1394 #define DL12_NORMAL_MODE_MASK_SFT (0x1 << 5)
1395 #define DL12_HALIGN_SFT 4
1396 #define DL12_HALIGN_MASK 0x1
1397 #define DL12_HALIGN_MASK_SFT (0x1 << 4)
1398 #define DL12_HD_MODE_SFT 0
1399 #define DL12_HD_MODE_MASK 0x3
1400 #define DL12_HD_MODE_MASK_SFT (0x3 << 0)
1401
1402 /* AFE_AWB_CON0 */
1403 #define AWB_MODE_SFT 24
1404 #define AWB_MODE_MASK 0xf
1405 #define AWB_MODE_MASK_SFT (0xf << 24)
1406 #define AWB_SW_CLEAR_BUF_FULL_SFT 15
1407 #define AWB_SW_CLEAR_BUF_FULL_MASK 0x1
1408 #define AWB_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1409 #define AWB_R_MONO_SFT 9
1410 #define AWB_R_MONO_MASK 0x1
1411 #define AWB_R_MONO_MASK_SFT (0x1 << 9)
1412 #define AWB_MONO_SFT 8
1413 #define AWB_MONO_MASK 0x1
1414 #define AWB_MONO_MASK_SFT (0x1 << 8)
1415 #define AWB_WR_SIGN_SFT 6
1416 #define AWB_WR_SIGN_MASK 0x1
1417 #define AWB_WR_SIGN_MASK_SFT (0x1 << 6)
1418 #define AWB_NORMAL_MODE_SFT 5
1419 #define AWB_NORMAL_MODE_MASK 0x1
1420 #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 5)
1421 #define AWB_HALIGN_SFT 4
1422 #define AWB_HALIGN_MASK 0x1
1423 #define AWB_HALIGN_MASK_SFT (0x1 << 4)
1424 #define AWB_HD_MODE_SFT 0
1425 #define AWB_HD_MODE_MASK 0x3
1426 #define AWB_HD_MODE_MASK_SFT (0x3 << 0)
1427
1428 /* AFE_AWB2_CON0 */
1429 #define AWB2_MODE_SFT 24
1430 #define AWB2_MODE_MASK 0xf
1431 #define AWB2_MODE_MASK_SFT (0xf << 24)
1432 #define AWB2_SW_CLEAR_BUF_FULL_SFT 15
1433 #define AWB2_SW_CLEAR_BUF_FULL_MASK 0x1
1434 #define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1435 #define AWB2_R_MONO_SFT 9
1436 #define AWB2_R_MONO_MASK 0x1
1437 #define AWB2_R_MONO_MASK_SFT (0x1 << 9)
1438 #define AWB2_MONO_SFT 8
1439 #define AWB2_MONO_MASK 0x1
1440 #define AWB2_MONO_MASK_SFT (0x1 << 8)
1441 #define AWB2_WR_SIGN_SFT 6
1442 #define AWB2_WR_SIGN_MASK 0x1
1443 #define AWB2_WR_SIGN_MASK_SFT (0x1 << 6)
1444 #define AWB2_NORMAL_MODE_SFT 5
1445 #define AWB2_NORMAL_MODE_MASK 0x1
1446 #define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1447 #define AWB2_HALIGN_SFT 4
1448 #define AWB2_HALIGN_MASK 0x1
1449 #define AWB2_HALIGN_MASK_SFT (0x1 << 4)
1450 #define AWB2_HD_MODE_SFT 0
1451 #define AWB2_HD_MODE_MASK 0x3
1452 #define AWB2_HD_MODE_MASK_SFT (0x3 << 0)
1453
1454 /* AFE_VUL_CON0 */
1455 #define VUL_MODE_SFT 24
1456 #define VUL_MODE_MASK 0xf
1457 #define VUL_MODE_MASK_SFT (0xf << 24)
1458 #define VUL_SW_CLEAR_BUF_FULL_SFT 15
1459 #define VUL_SW_CLEAR_BUF_FULL_MASK 0x1
1460 #define VUL_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1461 #define VUL_R_MONO_SFT 9
1462 #define VUL_R_MONO_MASK 0x1
1463 #define VUL_R_MONO_MASK_SFT (0x1 << 9)
1464 #define VUL_MONO_SFT 8
1465 #define VUL_MONO_MASK 0x1
1466 #define VUL_MONO_MASK_SFT (0x1 << 8)
1467 #define VUL_WR_SIGN_SFT 6
1468 #define VUL_WR_SIGN_MASK 0x1
1469 #define VUL_WR_SIGN_MASK_SFT (0x1 << 6)
1470 #define VUL_NORMAL_MODE_SFT 5
1471 #define VUL_NORMAL_MODE_MASK 0x1
1472 #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 5)
1473 #define VUL_HALIGN_SFT 4
1474 #define VUL_HALIGN_MASK 0x1
1475 #define VUL_HALIGN_MASK_SFT (0x1 << 4)
1476 #define VUL_HD_MODE_SFT 0
1477 #define VUL_HD_MODE_MASK 0x3
1478 #define VUL_HD_MODE_MASK_SFT (0x3 << 0)
1479
1480 /* AFE_VUL12_CON0 */
1481 #define VUL12_MODE_SFT 24
1482 #define VUL12_MODE_MASK 0xf
1483 #define VUL12_MODE_MASK_SFT (0xf << 24)
1484 #define VUL12_SW_CLEAR_BUF_FULL_SFT 15
1485 #define VUL12_SW_CLEAR_BUF_FULL_MASK 0x1
1486 #define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1487 #define VUL12_4CH_EN_SFT 11
1488 #define VUL12_4CH_EN_MASK 0x1
1489 #define VUL12_4CH_EN_MASK_SFT (0x1 << 11)
1490 #define VUL12_R_MONO_SFT 9
1491 #define VUL12_R_MONO_MASK 0x1
1492 #define VUL12_R_MONO_MASK_SFT (0x1 << 9)
1493 #define VUL12_MONO_SFT 8
1494 #define VUL12_MONO_MASK 0x1
1495 #define VUL12_MONO_MASK_SFT (0x1 << 8)
1496 #define VUL12_WR_SIGN_SFT 6
1497 #define VUL12_WR_SIGN_MASK 0x1
1498 #define VUL12_WR_SIGN_MASK_SFT (0x1 << 6)
1499 #define VUL12_NORMAL_MODE_SFT 5
1500 #define VUL12_NORMAL_MODE_MASK 0x1
1501 #define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 5)
1502 #define VUL12_HALIGN_SFT 4
1503 #define VUL12_HALIGN_MASK 0x1
1504 #define VUL12_HALIGN_MASK_SFT (0x1 << 4)
1505 #define VUL12_HD_MODE_SFT 0
1506 #define VUL12_HD_MODE_MASK 0x3
1507 #define VUL12_HD_MODE_MASK_SFT (0x3 << 0)
1508
1509 /* AFE_VUL2_CON0 */
1510 #define VUL2_MODE_SFT 24
1511 #define VUL2_MODE_MASK 0xf
1512 #define VUL2_MODE_MASK_SFT (0xf << 24)
1513 #define VUL2_SW_CLEAR_BUF_FULL_SFT 15
1514 #define VUL2_SW_CLEAR_BUF_FULL_MASK 0x1
1515 #define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1516 #define VUL2_R_MONO_SFT 9
1517 #define VUL2_R_MONO_MASK 0x1
1518 #define VUL2_R_MONO_MASK_SFT (0x1 << 9)
1519 #define VUL2_MONO_SFT 8
1520 #define VUL2_MONO_MASK 0x1
1521 #define VUL2_MONO_MASK_SFT (0x1 << 8)
1522 #define VUL2_WR_SIGN_SFT 6
1523 #define VUL2_WR_SIGN_MASK 0x1
1524 #define VUL2_WR_SIGN_MASK_SFT (0x1 << 6)
1525 #define VUL2_NORMAL_MODE_SFT 5
1526 #define VUL2_NORMAL_MODE_MASK 0x1
1527 #define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1528 #define VUL2_HALIGN_SFT 4
1529 #define VUL2_HALIGN_MASK 0x1
1530 #define VUL2_HALIGN_MASK_SFT (0x1 << 4)
1531 #define VUL2_HD_MODE_SFT 0
1532 #define VUL2_HD_MODE_MASK 0x3
1533 #define VUL2_HD_MODE_MASK_SFT (0x3 << 0)
1534
1535 /* AFE_VUL3_CON0 */
1536 #define VUL3_MODE_SFT 24
1537 #define VUL3_MODE_MASK 0xf
1538 #define VUL3_MODE_MASK_SFT (0xf << 24)
1539 #define VUL3_SW_CLEAR_BUF_FULL_SFT 15
1540 #define VUL3_SW_CLEAR_BUF_FULL_MASK 0x1
1541 #define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1542 #define VUL3_R_MONO_SFT 9
1543 #define VUL3_R_MONO_MASK 0x1
1544 #define VUL3_R_MONO_MASK_SFT (0x1 << 9)
1545 #define VUL3_MONO_SFT 8
1546 #define VUL3_MONO_MASK 0x1
1547 #define VUL3_MONO_MASK_SFT (0x1 << 8)
1548 #define VUL3_WR_SIGN_SFT 6
1549 #define VUL3_WR_SIGN_MASK 0x1
1550 #define VUL3_WR_SIGN_MASK_SFT (0x1 << 6)
1551 #define VUL3_NORMAL_MODE_SFT 5
1552 #define VUL3_NORMAL_MODE_MASK 0x1
1553 #define VUL3_NORMAL_MODE_MASK_SFT (0x1 << 5)
1554 #define VUL3_HALIGN_SFT 4
1555 #define VUL3_HALIGN_MASK 0x1
1556 #define VUL3_HALIGN_MASK_SFT (0x1 << 4)
1557 #define VUL3_HD_MODE_SFT 0
1558 #define VUL3_HD_MODE_MASK 0x3
1559 #define VUL3_HD_MODE_MASK_SFT (0x3 << 0)
1560
1561 /* AFE_VUL4_CON0 */
1562 #define VUL4_MODE_SFT 24
1563 #define VUL4_MODE_MASK 0xf
1564 #define VUL4_MODE_MASK_SFT (0xf << 24)
1565 #define VUL4_SW_CLEAR_BUF_FULL_SFT 15
1566 #define VUL4_SW_CLEAR_BUF_FULL_MASK 0x1
1567 #define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1568 #define VUL4_R_MONO_SFT 9
1569 #define VUL4_R_MONO_MASK 0x1
1570 #define VUL4_R_MONO_MASK_SFT (0x1 << 9)
1571 #define VUL4_MONO_SFT 8
1572 #define VUL4_MONO_MASK 0x1
1573 #define VUL4_MONO_MASK_SFT (0x1 << 8)
1574 #define VUL4_WR_SIGN_SFT 6
1575 #define VUL4_WR_SIGN_MASK 0x1
1576 #define VUL4_WR_SIGN_MASK_SFT (0x1 << 6)
1577 #define VUL4_NORMAL_MODE_SFT 5
1578 #define VUL4_NORMAL_MODE_MASK 0x1
1579 #define VUL4_NORMAL_MODE_MASK_SFT (0x1 << 5)
1580 #define VUL4_HALIGN_SFT 4
1581 #define VUL4_HALIGN_MASK 0x1
1582 #define VUL4_HALIGN_MASK_SFT (0x1 << 4)
1583 #define VUL4_HD_MODE_SFT 0
1584 #define VUL4_HD_MODE_MASK 0x3
1585 #define VUL4_HD_MODE_MASK_SFT (0x3 << 0)
1586
1587 /* AFE_VUL5_CON0 */
1588 #define VUL5_MODE_SFT 24
1589 #define VUL5_MODE_MASK 0xf
1590 #define VUL5_MODE_MASK_SFT (0xf << 24)
1591 #define VUL5_SW_CLEAR_BUF_FULL_SFT 15
1592 #define VUL5_SW_CLEAR_BUF_FULL_MASK 0x1
1593 #define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1594 #define VUL5_R_MONO_SFT 9
1595 #define VUL5_R_MONO_MASK 0x1
1596 #define VUL5_R_MONO_MASK_SFT (0x1 << 9)
1597 #define VUL5_MONO_SFT 8
1598 #define VUL5_MONO_MASK 0x1
1599 #define VUL5_MONO_MASK_SFT (0x1 << 8)
1600 #define VUL5_WR_SIGN_SFT 6
1601 #define VUL5_WR_SIGN_MASK 0x1
1602 #define VUL5_WR_SIGN_MASK_SFT (0x1 << 6)
1603 #define VUL5_NORMAL_MODE_SFT 5
1604 #define VUL5_NORMAL_MODE_MASK 0x1
1605 #define VUL5_NORMAL_MODE_MASK_SFT (0x1 << 5)
1606 #define VUL5_HALIGN_SFT 4
1607 #define VUL5_HALIGN_MASK 0x1
1608 #define VUL5_HALIGN_MASK_SFT (0x1 << 4)
1609 #define VUL5_HD_MODE_SFT 0
1610 #define VUL5_HD_MODE_MASK 0x3
1611 #define VUL5_HD_MODE_MASK_SFT (0x3 << 0)
1612
1613 /* AFE_VUL6_CON0 */
1614 #define VUL6_MODE_SFT 24
1615 #define VUL6_MODE_MASK 0xf
1616 #define VUL6_MODE_MASK_SFT (0xf << 24)
1617 #define VUL6_SW_CLEAR_BUF_FULL_SFT 15
1618 #define VUL6_SW_CLEAR_BUF_FULL_MASK 0x1
1619 #define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1620 #define VUL6_R_MONO_SFT 9
1621 #define VUL6_R_MONO_MASK 0x1
1622 #define VUL6_R_MONO_MASK_SFT (0x1 << 9)
1623 #define VUL6_MONO_SFT 8
1624 #define VUL6_MONO_MASK 0x1
1625 #define VUL6_MONO_MASK_SFT (0x1 << 8)
1626 #define VUL6_WR_SIGN_SFT 6
1627 #define VUL6_WR_SIGN_MASK 0x1
1628 #define VUL6_WR_SIGN_MASK_SFT (0x1 << 6)
1629 #define VUL6_NORMAL_MODE_SFT 5
1630 #define VUL6_NORMAL_MODE_MASK 0x1
1631 #define VUL6_NORMAL_MODE_MASK_SFT (0x1 << 5)
1632 #define VUL6_HALIGN_SFT 4
1633 #define VUL6_HALIGN_MASK 0x1
1634 #define VUL6_HALIGN_MASK_SFT (0x1 << 4)
1635 #define VUL6_HD_MODE_SFT 0
1636 #define VUL6_HD_MODE_MASK 0x3
1637 #define VUL6_HD_MODE_MASK_SFT (0x3 << 0)
1638
1639 /* AFE_DAI_CON0 */
1640 #define DAI_MODE_SFT 24
1641 #define DAI_MODE_MASK 0x3
1642 #define DAI_MODE_MASK_SFT (0x3 << 24)
1643 #define DAI_SW_CLEAR_BUF_FULL_SFT 15
1644 #define DAI_SW_CLEAR_BUF_FULL_MASK 0x1
1645 #define DAI_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1646 #define DAI_DUPLICATE_WR_SFT 10
1647 #define DAI_DUPLICATE_WR_MASK 0x1
1648 #define DAI_DUPLICATE_WR_MASK_SFT (0x1 << 10)
1649 #define DAI_MONO_SFT 8
1650 #define DAI_MONO_MASK 0x1
1651 #define DAI_MONO_MASK_SFT (0x1 << 8)
1652 #define DAI_WR_SIGN_SFT 6
1653 #define DAI_WR_SIGN_MASK 0x1
1654 #define DAI_WR_SIGN_MASK_SFT (0x1 << 6)
1655 #define DAI_NORMAL_MODE_SFT 5
1656 #define DAI_NORMAL_MODE_MASK 0x1
1657 #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 5)
1658 #define DAI_HALIGN_SFT 4
1659 #define DAI_HALIGN_MASK 0x1
1660 #define DAI_HALIGN_MASK_SFT (0x1 << 4)
1661 #define DAI_HD_MODE_SFT 0
1662 #define DAI_HD_MODE_MASK 0x3
1663 #define DAI_HD_MODE_MASK_SFT (0x3 << 0)
1664
1665 /* AFE_MOD_DAI_CON0 */
1666 #define MOD_DAI_MODE_SFT 24
1667 #define MOD_DAI_MODE_MASK 0x3
1668 #define MOD_DAI_MODE_MASK_SFT (0x3 << 24)
1669 #define MOD_DAI_SW_CLEAR_BUF_FULL_SFT 15
1670 #define MOD_DAI_SW_CLEAR_BUF_FULL_MASK 0x1
1671 #define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1672 #define MOD_DAI_DUPLICATE_WR_SFT 10
1673 #define MOD_DAI_DUPLICATE_WR_MASK 0x1
1674 #define MOD_DAI_DUPLICATE_WR_MASK_SFT (0x1 << 10)
1675 #define MOD_DAI_MONO_SFT 8
1676 #define MOD_DAI_MONO_MASK 0x1
1677 #define MOD_DAI_MONO_MASK_SFT (0x1 << 8)
1678 #define MOD_DAI_WR_SIGN_SFT 6
1679 #define MOD_DAI_WR_SIGN_MASK 0x1
1680 #define MOD_DAI_WR_SIGN_MASK_SFT (0x1 << 6)
1681 #define MOD_DAI_NORMAL_MODE_SFT 5
1682 #define MOD_DAI_NORMAL_MODE_MASK 0x1
1683 #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 5)
1684 #define MOD_DAI_HALIGN_SFT 4
1685 #define MOD_DAI_HALIGN_MASK 0x1
1686 #define MOD_DAI_HALIGN_MASK_SFT (0x1 << 4)
1687 #define MOD_DAI_HD_MODE_SFT 0
1688 #define MOD_DAI_HD_MODE_MASK 0x3
1689 #define MOD_DAI_HD_MODE_MASK_SFT (0x3 << 0)
1690
1691 /* AFE_DAI2_CON0 */
1692 #define DAI2_MODE_SFT 24
1693 #define DAI2_MODE_MASK 0xf
1694 #define DAI2_MODE_MASK_SFT (0xf << 24)
1695 #define DAI2_SW_CLEAR_BUF_FULL_SFT 15
1696 #define DAI2_SW_CLEAR_BUF_FULL_MASK 0x1
1697 #define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1698 #define DAI2_DUPLICATE_WR_SFT 10
1699 #define DAI2_DUPLICATE_WR_MASK 0x1
1700 #define DAI2_DUPLICATE_WR_MASK_SFT (0x1 << 10)
1701 #define DAI2_MONO_SFT 8
1702 #define DAI2_MONO_MASK 0x1
1703 #define DAI2_MONO_MASK_SFT (0x1 << 8)
1704 #define DAI2_WR_SIGN_SFT 6
1705 #define DAI2_WR_SIGN_MASK 0x1
1706 #define DAI2_WR_SIGN_MASK_SFT (0x1 << 6)
1707 #define DAI2_NORMAL_MODE_SFT 5
1708 #define DAI2_NORMAL_MODE_MASK 0x1
1709 #define DAI2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1710 #define DAI2_HALIGN_SFT 4
1711 #define DAI2_HALIGN_MASK 0x1
1712 #define DAI2_HALIGN_MASK_SFT (0x1 << 4)
1713 #define DAI2_HD_MODE_SFT 0
1714 #define DAI2_HD_MODE_MASK 0x3
1715 #define DAI2_HD_MODE_MASK_SFT (0x3 << 0)
1716
1717 /* AFE_MEMIF_CON0 */
1718 #define CPU_COMPACT_MODE_SFT 2
1719 #define CPU_COMPACT_MODE_MASK 0x1
1720 #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 2)
1721 #define CPU_HD_ALIGN_SFT 1
1722 #define CPU_HD_ALIGN_MASK 0x1
1723 #define CPU_HD_ALIGN_MASK_SFT (0x1 << 1)
1724 #define SYSRAM_SIGN_SFT 0
1725 #define SYSRAM_SIGN_MASK 0x1
1726 #define SYSRAM_SIGN_MASK_SFT (0x1 << 0)
1727
1728 /* AFE_HDMI_OUT_CON0 */
1729 #define HDMI_CH_NUM_SFT 24
1730 #define HDMI_CH_NUM_MASK 0xf
1731 #define HDMI_CH_NUM_MASK_SFT (0xf << 24)
1732 #define HDMI_OUT_MINLEN_SFT 20
1733 #define HDMI_OUT_MINLEN_MASK 0xf
1734 #define HDMI_OUT_MINLEN_MASK_SFT (0xf << 20)
1735 #define HDMI_OUT_MAXLEN_SFT 16
1736 #define HDMI_OUT_MAXLEN_MASK 0xf
1737 #define HDMI_OUT_MAXLEN_MASK_SFT (0xf << 16)
1738 #define HDMI_OUT_SW_CLEAR_BUF_EMPTY_SFT 15
1739 #define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK 0x1
1740 #define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1741 #define HDMI_OUT_PBUF_SIZE_SFT 12
1742 #define HDMI_OUT_PBUF_SIZE_MASK 0x3
1743 #define HDMI_OUT_PBUF_SIZE_MASK_SFT (0x3 << 12)
1744 #define HDMI_OUT_NORMAL_MODE_SFT 5
1745 #define HDMI_OUT_NORMAL_MODE_MASK 0x1
1746 #define HDMI_OUT_NORMAL_MODE_MASK_SFT (0x1 << 5)
1747 #define HDMI_OUT_HALIGN_SFT 4
1748 #define HDMI_OUT_HALIGN_MASK 0x1
1749 #define HDMI_OUT_HALIGN_MASK_SFT (0x1 << 4)
1750 #define HDMI_OUT_HD_MODE_SFT 0
1751 #define HDMI_OUT_HD_MODE_MASK 0x3
1752 #define HDMI_OUT_HD_MODE_MASK_SFT (0x3 << 0)
1753
1754 /* AFE_IRQ_MCU_CON0 */
1755 #define IRQ31_MCU_ON_SFT 31
1756 #define IRQ31_MCU_ON_MASK 0x1
1757 #define IRQ31_MCU_ON_MASK_SFT (0x1 << 31)
1758 #define IRQ26_MCU_ON_SFT 26
1759 #define IRQ26_MCU_ON_MASK 0x1
1760 #define IRQ26_MCU_ON_MASK_SFT (0x1 << 26)
1761 #define IRQ25_MCU_ON_SFT 25
1762 #define IRQ25_MCU_ON_MASK 0x1
1763 #define IRQ25_MCU_ON_MASK_SFT (0x1 << 25)
1764 #define IRQ24_MCU_ON_SFT 24
1765 #define IRQ24_MCU_ON_MASK 0x1
1766 #define IRQ24_MCU_ON_MASK_SFT (0x1 << 24)
1767 #define IRQ23_MCU_ON_SFT 23
1768 #define IRQ23_MCU_ON_MASK 0x1
1769 #define IRQ23_MCU_ON_MASK_SFT (0x1 << 23)
1770 #define IRQ22_MCU_ON_SFT 22
1771 #define IRQ22_MCU_ON_MASK 0x1
1772 #define IRQ22_MCU_ON_MASK_SFT (0x1 << 22)
1773 #define IRQ21_MCU_ON_SFT 21
1774 #define IRQ21_MCU_ON_MASK 0x1
1775 #define IRQ21_MCU_ON_MASK_SFT (0x1 << 21)
1776 #define IRQ20_MCU_ON_SFT 20
1777 #define IRQ20_MCU_ON_MASK 0x1
1778 #define IRQ20_MCU_ON_MASK_SFT (0x1 << 20)
1779 #define IRQ19_MCU_ON_SFT 19
1780 #define IRQ19_MCU_ON_MASK 0x1
1781 #define IRQ19_MCU_ON_MASK_SFT (0x1 << 19)
1782 #define IRQ18_MCU_ON_SFT 18
1783 #define IRQ18_MCU_ON_MASK 0x1
1784 #define IRQ18_MCU_ON_MASK_SFT (0x1 << 18)
1785 #define IRQ17_MCU_ON_SFT 17
1786 #define IRQ17_MCU_ON_MASK 0x1
1787 #define IRQ17_MCU_ON_MASK_SFT (0x1 << 17)
1788 #define IRQ16_MCU_ON_SFT 16
1789 #define IRQ16_MCU_ON_MASK 0x1
1790 #define IRQ16_MCU_ON_MASK_SFT (0x1 << 16)
1791 #define IRQ15_MCU_ON_SFT 15
1792 #define IRQ15_MCU_ON_MASK 0x1
1793 #define IRQ15_MCU_ON_MASK_SFT (0x1 << 15)
1794 #define IRQ14_MCU_ON_SFT 14
1795 #define IRQ14_MCU_ON_MASK 0x1
1796 #define IRQ14_MCU_ON_MASK_SFT (0x1 << 14)
1797 #define IRQ13_MCU_ON_SFT 13
1798 #define IRQ13_MCU_ON_MASK 0x1
1799 #define IRQ13_MCU_ON_MASK_SFT (0x1 << 13)
1800 #define IRQ12_MCU_ON_SFT 12
1801 #define IRQ12_MCU_ON_MASK 0x1
1802 #define IRQ12_MCU_ON_MASK_SFT (0x1 << 12)
1803 #define IRQ11_MCU_ON_SFT 11
1804 #define IRQ11_MCU_ON_MASK 0x1
1805 #define IRQ11_MCU_ON_MASK_SFT (0x1 << 11)
1806 #define IRQ10_MCU_ON_SFT 10
1807 #define IRQ10_MCU_ON_MASK 0x1
1808 #define IRQ10_MCU_ON_MASK_SFT (0x1 << 10)
1809 #define IRQ9_MCU_ON_SFT 9
1810 #define IRQ9_MCU_ON_MASK 0x1
1811 #define IRQ9_MCU_ON_MASK_SFT (0x1 << 9)
1812 #define IRQ8_MCU_ON_SFT 8
1813 #define IRQ8_MCU_ON_MASK 0x1
1814 #define IRQ8_MCU_ON_MASK_SFT (0x1 << 8)
1815 #define IRQ7_MCU_ON_SFT 7
1816 #define IRQ7_MCU_ON_MASK 0x1
1817 #define IRQ7_MCU_ON_MASK_SFT (0x1 << 7)
1818 #define IRQ6_MCU_ON_SFT 6
1819 #define IRQ6_MCU_ON_MASK 0x1
1820 #define IRQ6_MCU_ON_MASK_SFT (0x1 << 6)
1821 #define IRQ5_MCU_ON_SFT 5
1822 #define IRQ5_MCU_ON_MASK 0x1
1823 #define IRQ5_MCU_ON_MASK_SFT (0x1 << 5)
1824 #define IRQ4_MCU_ON_SFT 4
1825 #define IRQ4_MCU_ON_MASK 0x1
1826 #define IRQ4_MCU_ON_MASK_SFT (0x1 << 4)
1827 #define IRQ3_MCU_ON_SFT 3
1828 #define IRQ3_MCU_ON_MASK 0x1
1829 #define IRQ3_MCU_ON_MASK_SFT (0x1 << 3)
1830 #define IRQ2_MCU_ON_SFT 2
1831 #define IRQ2_MCU_ON_MASK 0x1
1832 #define IRQ2_MCU_ON_MASK_SFT (0x1 << 2)
1833 #define IRQ1_MCU_ON_SFT 1
1834 #define IRQ1_MCU_ON_MASK 0x1
1835 #define IRQ1_MCU_ON_MASK_SFT (0x1 << 1)
1836 #define IRQ0_MCU_ON_SFT 0
1837 #define IRQ0_MCU_ON_MASK 0x1
1838 #define IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
1839
1840 /* AFE_IRQ_MCU_CON1 */
1841 #define IRQ7_MCU_MODE_SFT 28
1842 #define IRQ7_MCU_MODE_MASK 0xf
1843 #define IRQ7_MCU_MODE_MASK_SFT (0xf << 28)
1844 #define IRQ6_MCU_MODE_SFT 24
1845 #define IRQ6_MCU_MODE_MASK 0xf
1846 #define IRQ6_MCU_MODE_MASK_SFT (0xf << 24)
1847 #define IRQ5_MCU_MODE_SFT 20
1848 #define IRQ5_MCU_MODE_MASK 0xf
1849 #define IRQ5_MCU_MODE_MASK_SFT (0xf << 20)
1850 #define IRQ4_MCU_MODE_SFT 16
1851 #define IRQ4_MCU_MODE_MASK 0xf
1852 #define IRQ4_MCU_MODE_MASK_SFT (0xf << 16)
1853 #define IRQ3_MCU_MODE_SFT 12
1854 #define IRQ3_MCU_MODE_MASK 0xf
1855 #define IRQ3_MCU_MODE_MASK_SFT (0xf << 12)
1856 #define IRQ2_MCU_MODE_SFT 8
1857 #define IRQ2_MCU_MODE_MASK 0xf
1858 #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)
1859 #define IRQ1_MCU_MODE_SFT 4
1860 #define IRQ1_MCU_MODE_MASK 0xf
1861 #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)
1862 #define IRQ0_MCU_MODE_SFT 0
1863 #define IRQ0_MCU_MODE_MASK 0xf
1864 #define IRQ0_MCU_MODE_MASK_SFT (0xf << 0)
1865
1866 /* AFE_IRQ_MCU_CON2 */
1867 #define IRQ15_MCU_MODE_SFT 28
1868 #define IRQ15_MCU_MODE_MASK 0xf
1869 #define IRQ15_MCU_MODE_MASK_SFT (0xf << 28)
1870 #define IRQ14_MCU_MODE_SFT 24
1871 #define IRQ14_MCU_MODE_MASK 0xf
1872 #define IRQ14_MCU_MODE_MASK_SFT (0xf << 24)
1873 #define IRQ13_MCU_MODE_SFT 20
1874 #define IRQ13_MCU_MODE_MASK 0xf
1875 #define IRQ13_MCU_MODE_MASK_SFT (0xf << 20)
1876 #define IRQ12_MCU_MODE_SFT 16
1877 #define IRQ12_MCU_MODE_MASK 0xf
1878 #define IRQ12_MCU_MODE_MASK_SFT (0xf << 16)
1879 #define IRQ11_MCU_MODE_SFT 12
1880 #define IRQ11_MCU_MODE_MASK 0xf
1881 #define IRQ11_MCU_MODE_MASK_SFT (0xf << 12)
1882 #define IRQ10_MCU_MODE_SFT 8
1883 #define IRQ10_MCU_MODE_MASK 0xf
1884 #define IRQ10_MCU_MODE_MASK_SFT (0xf << 8)
1885 #define IRQ9_MCU_MODE_SFT 4
1886 #define IRQ9_MCU_MODE_MASK 0xf
1887 #define IRQ9_MCU_MODE_MASK_SFT (0xf << 4)
1888 #define IRQ8_MCU_MODE_SFT 0
1889 #define IRQ8_MCU_MODE_MASK 0xf
1890 #define IRQ8_MCU_MODE_MASK_SFT (0xf << 0)
1891
1892 /* AFE_IRQ_MCU_CON3 */
1893 #define IRQ23_MCU_MODE_SFT 28
1894 #define IRQ23_MCU_MODE_MASK 0xf
1895 #define IRQ23_MCU_MODE_MASK_SFT (0xf << 28)
1896 #define IRQ22_MCU_MODE_SFT 24
1897 #define IRQ22_MCU_MODE_MASK 0xf
1898 #define IRQ22_MCU_MODE_MASK_SFT (0xf << 24)
1899 #define IRQ21_MCU_MODE_SFT 20
1900 #define IRQ21_MCU_MODE_MASK 0xf
1901 #define IRQ21_MCU_MODE_MASK_SFT (0xf << 20)
1902 #define IRQ20_MCU_MODE_SFT 16
1903 #define IRQ20_MCU_MODE_MASK 0xf
1904 #define IRQ20_MCU_MODE_MASK_SFT (0xf << 16)
1905 #define IRQ19_MCU_MODE_SFT 12
1906 #define IRQ19_MCU_MODE_MASK 0xf
1907 #define IRQ19_MCU_MODE_MASK_SFT (0xf << 12)
1908 #define IRQ18_MCU_MODE_SFT 8
1909 #define IRQ18_MCU_MODE_MASK 0xf
1910 #define IRQ18_MCU_MODE_MASK_SFT (0xf << 8)
1911 #define IRQ17_MCU_MODE_SFT 4
1912 #define IRQ17_MCU_MODE_MASK 0xf
1913 #define IRQ17_MCU_MODE_MASK_SFT (0xf << 4)
1914 #define IRQ16_MCU_MODE_SFT 0
1915 #define IRQ16_MCU_MODE_MASK 0xf
1916 #define IRQ16_MCU_MODE_MASK_SFT (0xf << 0)
1917
1918 /* AFE_IRQ_MCU_CON4 */
1919 #define IRQ26_MCU_MODE_SFT 8
1920 #define IRQ26_MCU_MODE_MASK 0xf
1921 #define IRQ26_MCU_MODE_MASK_SFT (0xf << 8)
1922 #define IRQ25_MCU_MODE_SFT 4
1923 #define IRQ25_MCU_MODE_MASK 0xf
1924 #define IRQ25_MCU_MODE_MASK_SFT (0xf << 4)
1925 #define IRQ24_MCU_MODE_SFT 0
1926 #define IRQ24_MCU_MODE_MASK 0xf
1927 #define IRQ24_MCU_MODE_MASK_SFT (0xf << 0)
1928
1929 /* AFE_IRQ_MCU_CLR */
1930 #define IRQ31_MCU_CLR_SFT 31
1931 #define IRQ31_MCU_CLR_MASK 0x1
1932 #define IRQ31_MCU_CLR_MASK_SFT (0x1 << 31)
1933 #define IRQ26_MCU_CLR_SFT 26
1934 #define IRQ26_MCU_CLR_MASK 0x1
1935 #define IRQ26_MCU_CLR_MASK_SFT (0x1 << 26)
1936 #define IRQ25_MCU_CLR_SFT 25
1937 #define IRQ25_MCU_CLR_MASK 0x1
1938 #define IRQ25_MCU_CLR_MASK_SFT (0x1 << 25)
1939 #define IRQ24_MCU_CLR_SFT 24
1940 #define IRQ24_MCU_CLR_MASK 0x1
1941 #define IRQ24_MCU_CLR_MASK_SFT (0x1 << 24)
1942 #define IRQ23_MCU_CLR_SFT 23
1943 #define IRQ23_MCU_CLR_MASK 0x1
1944 #define IRQ23_MCU_CLR_MASK_SFT (0x1 << 23)
1945 #define IRQ22_MCU_CLR_SFT 22
1946 #define IRQ22_MCU_CLR_MASK 0x1
1947 #define IRQ22_MCU_CLR_MASK_SFT (0x1 << 22)
1948 #define IRQ21_MCU_CLR_SFT 21
1949 #define IRQ21_MCU_CLR_MASK 0x1
1950 #define IRQ21_MCU_CLR_MASK_SFT (0x1 << 21)
1951 #define IRQ20_MCU_CLR_SFT 20
1952 #define IRQ20_MCU_CLR_MASK 0x1
1953 #define IRQ20_MCU_CLR_MASK_SFT (0x1 << 20)
1954 #define IRQ19_MCU_CLR_SFT 19
1955 #define IRQ19_MCU_CLR_MASK 0x1
1956 #define IRQ19_MCU_CLR_MASK_SFT (0x1 << 19)
1957 #define IRQ18_MCU_CLR_SFT 18
1958 #define IRQ18_MCU_CLR_MASK 0x1
1959 #define IRQ18_MCU_CLR_MASK_SFT (0x1 << 18)
1960 #define IRQ17_MCU_CLR_SFT 17
1961 #define IRQ17_MCU_CLR_MASK 0x1
1962 #define IRQ17_MCU_CLR_MASK_SFT (0x1 << 17)
1963 #define IRQ16_MCU_CLR_SFT 16
1964 #define IRQ16_MCU_CLR_MASK 0x1
1965 #define IRQ16_MCU_CLR_MASK_SFT (0x1 << 16)
1966 #define IRQ15_MCU_CLR_SFT 15
1967 #define IRQ15_MCU_CLR_MASK 0x1
1968 #define IRQ15_MCU_CLR_MASK_SFT (0x1 << 15)
1969 #define IRQ14_MCU_CLR_SFT 14
1970 #define IRQ14_MCU_CLR_MASK 0x1
1971 #define IRQ14_MCU_CLR_MASK_SFT (0x1 << 14)
1972 #define IRQ13_MCU_CLR_SFT 13
1973 #define IRQ13_MCU_CLR_MASK 0x1
1974 #define IRQ13_MCU_CLR_MASK_SFT (0x1 << 13)
1975 #define IRQ12_MCU_CLR_SFT 12
1976 #define IRQ12_MCU_CLR_MASK 0x1
1977 #define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12)
1978 #define IRQ11_MCU_CLR_SFT 11
1979 #define IRQ11_MCU_CLR_MASK 0x1
1980 #define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11)
1981 #define IRQ10_MCU_CLR_SFT 10
1982 #define IRQ10_MCU_CLR_MASK 0x1
1983 #define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10)
1984 #define IRQ9_MCU_CLR_SFT 9
1985 #define IRQ9_MCU_CLR_MASK 0x1
1986 #define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9)
1987 #define IRQ8_MCU_CLR_SFT 8
1988 #define IRQ8_MCU_CLR_MASK 0x1
1989 #define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8)
1990 #define IRQ7_MCU_CLR_SFT 7
1991 #define IRQ7_MCU_CLR_MASK 0x1
1992 #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7)
1993 #define IRQ6_MCU_CLR_SFT 6
1994 #define IRQ6_MCU_CLR_MASK 0x1
1995 #define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6)
1996 #define IRQ5_MCU_CLR_SFT 5
1997 #define IRQ5_MCU_CLR_MASK 0x1
1998 #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5)
1999 #define IRQ4_MCU_CLR_SFT 4
2000 #define IRQ4_MCU_CLR_MASK 0x1
2001 #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4)
2002 #define IRQ3_MCU_CLR_SFT 3
2003 #define IRQ3_MCU_CLR_MASK 0x1
2004 #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3)
2005 #define IRQ2_MCU_CLR_SFT 2
2006 #define IRQ2_MCU_CLR_MASK 0x1
2007 #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2)
2008 #define IRQ1_MCU_CLR_SFT 1
2009 #define IRQ1_MCU_CLR_MASK 0x1
2010 #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1)
2011 #define IRQ0_MCU_CLR_SFT 0
2012 #define IRQ0_MCU_CLR_MASK 0x1
2013 #define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0)
2014
2015 /* AFE_IRQ_MCU_EN */
2016 #define IRQ31_MCU_EN_SFT 31
2017 #define IRQ30_MCU_EN_SFT 30
2018 #define IRQ29_MCU_EN_SFT 29
2019 #define IRQ28_MCU_EN_SFT 28
2020 #define IRQ27_MCU_EN_SFT 27
2021 #define IRQ26_MCU_EN_SFT 26
2022 #define IRQ25_MCU_EN_SFT 25
2023 #define IRQ24_MCU_EN_SFT 24
2024 #define IRQ23_MCU_EN_SFT 23
2025 #define IRQ22_MCU_EN_SFT 22
2026 #define IRQ21_MCU_EN_SFT 21
2027 #define IRQ20_MCU_EN_SFT 20
2028 #define IRQ19_MCU_EN_SFT 19
2029 #define IRQ18_MCU_EN_SFT 18
2030 #define IRQ17_MCU_EN_SFT 17
2031 #define IRQ16_MCU_EN_SFT 16
2032 #define IRQ15_MCU_EN_SFT 15
2033 #define IRQ14_MCU_EN_SFT 14
2034 #define IRQ13_MCU_EN_SFT 13
2035 #define IRQ12_MCU_EN_SFT 12
2036 #define IRQ11_MCU_EN_SFT 11
2037 #define IRQ10_MCU_EN_SFT 10
2038 #define IRQ9_MCU_EN_SFT 9
2039 #define IRQ8_MCU_EN_SFT 8
2040 #define IRQ7_MCU_EN_SFT 7
2041 #define IRQ6_MCU_EN_SFT 6
2042 #define IRQ5_MCU_EN_SFT 5
2043 #define IRQ4_MCU_EN_SFT 4
2044 #define IRQ3_MCU_EN_SFT 3
2045 #define IRQ2_MCU_EN_SFT 2
2046 #define IRQ1_MCU_EN_SFT 1
2047 #define IRQ0_MCU_EN_SFT 0
2048
2049 /* AFE_IRQ_MCU_SCP_EN */
2050 #define IRQ31_MCU_SCP_EN_SFT 31
2051 #define IRQ30_MCU_SCP_EN_SFT 30
2052 #define IRQ29_MCU_SCP_EN_SFT 29
2053 #define IRQ28_MCU_SCP_EN_SFT 28
2054 #define IRQ27_MCU_SCP_EN_SFT 27
2055 #define IRQ26_MCU_SCP_EN_SFT 26
2056 #define IRQ25_MCU_SCP_EN_SFT 25
2057 #define IRQ24_MCU_SCP_EN_SFT 24
2058 #define IRQ23_MCU_SCP_EN_SFT 23
2059 #define IRQ22_MCU_SCP_EN_SFT 22
2060 #define IRQ21_MCU_SCP_EN_SFT 21
2061 #define IRQ20_MCU_SCP_EN_SFT 20
2062 #define IRQ19_MCU_SCP_EN_SFT 19
2063 #define IRQ18_MCU_SCP_EN_SFT 18
2064 #define IRQ17_MCU_SCP_EN_SFT 17
2065 #define IRQ16_MCU_SCP_EN_SFT 16
2066 #define IRQ15_MCU_SCP_EN_SFT 15
2067 #define IRQ14_MCU_SCP_EN_SFT 14
2068 #define IRQ13_MCU_SCP_EN_SFT 13
2069 #define IRQ12_MCU_SCP_EN_SFT 12
2070 #define IRQ11_MCU_SCP_EN_SFT 11
2071 #define IRQ10_MCU_SCP_EN_SFT 10
2072 #define IRQ9_MCU_SCP_EN_SFT 9
2073 #define IRQ8_MCU_SCP_EN_SFT 8
2074 #define IRQ7_MCU_SCP_EN_SFT 7
2075 #define IRQ6_MCU_SCP_EN_SFT 6
2076 #define IRQ5_MCU_SCP_EN_SFT 5
2077 #define IRQ4_MCU_SCP_EN_SFT 4
2078 #define IRQ3_MCU_SCP_EN_SFT 3
2079 #define IRQ2_MCU_SCP_EN_SFT 2
2080 #define IRQ1_MCU_SCP_EN_SFT 1
2081 #define IRQ0_MCU_SCP_EN_SFT 0
2082
2083 /* AFE_TDM_CON1 */
2084 #define TDM_EN_SFT 0
2085 #define TDM_EN_MASK 0x1
2086 #define TDM_EN_MASK_SFT (0x1 << 0)
2087 #define LRCK_INVERSE_SFT 2
2088 #define LRCK_INVERSE_MASK 0x1
2089 #define LRCK_INVERSE_MASK_SFT (0x1 << 2)
2090 #define DELAY_DATA_SFT 3
2091 #define DELAY_DATA_MASK 0x1
2092 #define DELAY_DATA_MASK_SFT (0x1 << 3)
2093 #define LEFT_ALIGN_SFT 4
2094 #define LEFT_ALIGN_MASK 0x1
2095 #define LEFT_ALIGN_MASK_SFT (0x1 << 4)
2096 #define WLEN_SFT 8
2097 #define WLEN_MASK 0x3
2098 #define WLEN_MASK_SFT (0x3 << 8)
2099 #define CHANNEL_NUM_SFT 10
2100 #define CHANNEL_NUM_MASK 0x3
2101 #define CHANNEL_NUM_MASK_SFT (0x3 << 10)
2102 #define CHANNEL_BCK_CYCLES_SFT 12
2103 #define CHANNEL_BCK_CYCLES_MASK 0x3
2104 #define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12)
2105 #define DAC_BIT_NUM_SFT 16
2106 #define DAC_BIT_NUM_MASK 0x1f
2107 #define DAC_BIT_NUM_MASK_SFT (0x1f << 16)
2108 #define LRCK_TDM_WIDTH_SFT 24
2109 #define LRCK_TDM_WIDTH_MASK 0xff
2110 #define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24)
2111
2112 /* AFE_TDM_CON2 */
2113 #define ST_CH_PAIR_SOUT0_SFT 0
2114 #define ST_CH_PAIR_SOUT0_MASK 0x7
2115 #define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0)
2116 #define ST_CH_PAIR_SOUT1_SFT 4
2117 #define ST_CH_PAIR_SOUT1_MASK 0x7
2118 #define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4)
2119 #define ST_CH_PAIR_SOUT2_SFT 8
2120 #define ST_CH_PAIR_SOUT2_MASK 0x7
2121 #define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8)
2122 #define ST_CH_PAIR_SOUT3_SFT 12
2123 #define ST_CH_PAIR_SOUT3_MASK 0x7
2124 #define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12)
2125 #define TDM_FIX_VALUE_SEL_SFT 16
2126 #define TDM_FIX_VALUE_SEL_MASK 0x1
2127 #define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)
2128 #define TDM_I2S_LOOPBACK_SFT 20
2129 #define TDM_I2S_LOOPBACK_MASK 0x1
2130 #define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)
2131 #define TDM_I2S_LOOPBACK_CH_SFT 21
2132 #define TDM_I2S_LOOPBACK_CH_MASK 0x3
2133 #define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21)
2134 #define TDM_FIX_VALUE_SFT 24
2135 #define TDM_FIX_VALUE_MASK 0xff
2136 #define TDM_FIX_VALUE_MASK_SFT (0xff << 24)
2137
2138 /* AFE_HDMI_CONN0 */
2139 #define HDMI_O_7_SFT 21
2140 #define HDMI_O_7_MASK 0x7
2141 #define HDMI_O_7_MASK_SFT (0x7 << 21)
2142 #define HDMI_O_6_SFT 18
2143 #define HDMI_O_6_MASK 0x7
2144 #define HDMI_O_6_MASK_SFT (0x7 << 18)
2145 #define HDMI_O_5_SFT 15
2146 #define HDMI_O_5_MASK 0x7
2147 #define HDMI_O_5_MASK_SFT (0x7 << 15)
2148 #define HDMI_O_4_SFT 12
2149 #define HDMI_O_4_MASK 0x7
2150 #define HDMI_O_4_MASK_SFT (0x7 << 12)
2151 #define HDMI_O_3_SFT 9
2152 #define HDMI_O_3_MASK 0x7
2153 #define HDMI_O_3_MASK_SFT (0x7 << 9)
2154 #define HDMI_O_2_SFT 6
2155 #define HDMI_O_2_MASK 0x7
2156 #define HDMI_O_2_MASK_SFT (0x7 << 6)
2157 #define HDMI_O_1_SFT 3
2158 #define HDMI_O_1_MASK 0x7
2159 #define HDMI_O_1_MASK_SFT (0x7 << 3)
2160 #define HDMI_O_0_SFT 0
2161 #define HDMI_O_0_MASK 0x7
2162 #define HDMI_O_0_MASK_SFT (0x7 << 0)
2163
2164 /* AFE_AUD_PAD_TOP */
2165 #define AUD_PAD_TOP_MON_SFT 15
2166 #define AUD_PAD_TOP_MON_MASK 0x1ffff
2167 #define AUD_PAD_TOP_MON_MASK_SFT (0x1ffff << 15)
2168 #define AUD_PAD_TOP_FIFO_RSP_SFT 4
2169 #define AUD_PAD_TOP_FIFO_RSP_MASK 0xf
2170 #define AUD_PAD_TOP_FIFO_RSP_MASK_SFT (0xf << 4)
2171 #define RG_RX_PROTOCOL2_SFT 3
2172 #define RG_RX_PROTOCOL2_MASK 0x1
2173 #define RG_RX_PROTOCOL2_MASK_SFT (0x1 << 3)
2174 #define RESERVDED_01_SFT 1
2175 #define RESERVDED_01_MASK 0x3
2176 #define RESERVDED_01_MASK_SFT (0x3 << 1)
2177 #define RG_RX_FIFO_ON_SFT 0
2178 #define RG_RX_FIFO_ON_MASK 0x1
2179 #define RG_RX_FIFO_ON_MASK_SFT (0x1 << 0)
2180
2181 /* AFE_ADDA_MTKAIF_SYNCWORD_CFG */
2182 #define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT 23
2183 #define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK 0x1
2184 #define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 23)
2185
2186 /* AFE_ADDA_MTKAIF_RX_CFG0 */
2187 #define MTKAIF_RXIF_VOICE_MODE_SFT 20
2188 #define MTKAIF_RXIF_VOICE_MODE_MASK 0xf
2189 #define MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 20)
2190 #define MTKAIF_RXIF_DETECT_ON_SFT 16
2191 #define MTKAIF_RXIF_DETECT_ON_MASK 0x1
2192 #define MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)
2193 #define MTKAIF_RXIF_DATA_BIT_SFT 8
2194 #define MTKAIF_RXIF_DATA_BIT_MASK 0x7
2195 #define MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
2196 #define MTKAIF_RXIF_FIFO_RSP_SFT 4
2197 #define MTKAIF_RXIF_FIFO_RSP_MASK 0x7
2198 #define MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
2199 #define MTKAIF_RXIF_DATA_MODE_SFT 0
2200 #define MTKAIF_RXIF_DATA_MODE_MASK 0x1
2201 #define MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
2202
2203 /* GENERAL_ASRC_MODE */
2204 #define GENERAL2_ASRCOUT_MODE_SFT 12
2205 #define GENERAL2_ASRCOUT_MODE_MASK 0xf
2206 #define GENERAL2_ASRCOUT_MODE_MASK_SFT (0xf << 12)
2207 #define GENERAL2_ASRCIN_MODE_SFT 8
2208 #define GENERAL2_ASRCIN_MODE_MASK 0xf
2209 #define GENERAL2_ASRCIN_MODE_MASK_SFT (0xf << 8)
2210 #define GENERAL1_ASRCOUT_MODE_SFT 4
2211 #define GENERAL1_ASRCOUT_MODE_MASK 0xf
2212 #define GENERAL1_ASRCOUT_MODE_MASK_SFT (0xf << 4)
2213 #define GENERAL1_ASRCIN_MODE_SFT 0
2214 #define GENERAL1_ASRCIN_MODE_MASK 0xf
2215 #define GENERAL1_ASRCIN_MODE_MASK_SFT (0xf << 0)
2216
2217 /* GENERAL_ASRC_EN_ON */
2218 #define GENERAL2_ASRC_EN_ON_SFT 1
2219 #define GENERAL2_ASRC_EN_ON_MASK 0x1
2220 #define GENERAL2_ASRC_EN_ON_MASK_SFT (0x1 << 1)
2221 #define GENERAL1_ASRC_EN_ON_SFT 0
2222 #define GENERAL1_ASRC_EN_ON_MASK 0x1
2223 #define GENERAL1_ASRC_EN_ON_MASK_SFT (0x1 << 0)
2224
2225 /* AFE_GENERAL1_ASRC_2CH_CON0 */
2226 #define G_SRC_CHSET_STR_CLR_SFT 4
2227 #define G_SRC_CHSET_STR_CLR_MASK 0x1
2228 #define G_SRC_CHSET_STR_CLR_MASK_SFT (0x1 << 4)
2229 #define G_SRC_CHSET_ON_SFT 2
2230 #define G_SRC_CHSET_ON_MASK 0x1
2231 #define G_SRC_CHSET_ON_MASK_SFT (0x1 << 2)
2232 #define G_SRC_COEFF_SRAM_CTRL_SFT 1
2233 #define G_SRC_COEFF_SRAM_CTRL_MASK 0x1
2234 #define G_SRC_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
2235 #define G_SRC_ASM_ON_SFT 0
2236 #define G_SRC_ASM_ON_MASK 0x1
2237 #define G_SRC_ASM_ON_MASK_SFT (0x1 << 0)
2238
2239 /* AFE_GENERAL1_ASRC_2CH_CON3 */
2240 #define G_SRC_ASM_FREQ_4_SFT 0
2241 #define G_SRC_ASM_FREQ_4_MASK 0xffffff
2242 #define G_SRC_ASM_FREQ_4_MASK_SFT (0xffffff << 0)
2243
2244 /* AFE_GENERAL1_ASRC_2CH_CON4 */
2245 #define G_SRC_ASM_FREQ_5_SFT 0
2246 #define G_SRC_ASM_FREQ_5_MASK 0xffffff
2247 #define G_SRC_ASM_FREQ_5_MASK_SFT (0xffffff << 0)
2248
2249 /* AFE_GENERAL1_ASRC_2CH_CON13 */
2250 #define G_SRC_COEFF_SRAM_ADR_SFT 0
2251 #define G_SRC_COEFF_SRAM_ADR_MASK 0x3f
2252 #define G_SRC_COEFF_SRAM_ADR_MASK_SFT (0x3f << 0)
2253
2254 /* AFE_GENERAL1_ASRC_2CH_CON2 */
2255 #define G_SRC_CHSET_O16BIT_SFT 19
2256 #define G_SRC_CHSET_O16BIT_MASK 0x1
2257 #define G_SRC_CHSET_O16BIT_MASK_SFT (0x1 << 19)
2258 #define G_SRC_CHSET_CLR_IIR_HISTORY_SFT 17
2259 #define G_SRC_CHSET_CLR_IIR_HISTORY_MASK 0x1
2260 #define G_SRC_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)
2261 #define G_SRC_CHSET_IS_MONO_SFT 16
2262 #define G_SRC_CHSET_IS_MONO_MASK 0x1
2263 #define G_SRC_CHSET_IS_MONO_MASK_SFT (0x1 << 16)
2264 #define G_SRC_CHSET_IIR_EN_SFT 11
2265 #define G_SRC_CHSET_IIR_EN_MASK 0x1
2266 #define G_SRC_CHSET_IIR_EN_MASK_SFT (0x1 << 11)
2267 #define G_SRC_CHSET_IIR_STAGE_SFT 8
2268 #define G_SRC_CHSET_IIR_STAGE_MASK 0x7
2269 #define G_SRC_CHSET_IIR_STAGE_MASK_SFT (0x7 << 8)
2270 #define G_SRC_CHSET_STR_CLR_RU_SFT 5
2271 #define G_SRC_CHSET_STR_CLR_RU_MASK 0x1
2272 #define G_SRC_CHSET_STR_CLR_RU_MASK_SFT (0x1 << 5)
2273 #define G_SRC_CHSET_ON_SFT 2
2274 #define G_SRC_CHSET_ON_MASK 0x1
2275 #define G_SRC_CHSET_ON_MASK_SFT (0x1 << 2)
2276 #define G_SRC_COEFF_SRAM_CTRL_SFT 1
2277 #define G_SRC_COEFF_SRAM_CTRL_MASK 0x1
2278 #define G_SRC_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
2279 #define G_SRC_ASM_ON_SFT 0
2280 #define G_SRC_ASM_ON_MASK 0x1
2281 #define G_SRC_ASM_ON_MASK_SFT (0x1 << 0)
2282
2283 /* AFE_ADDA_DL_SDM_AUTO_RESET_CON */
2284 #define ADDA_SDM_AUTO_RESET_ONOFF_SFT 31
2285 #define ADDA_SDM_AUTO_RESET_ONOFF_MASK 0x1
2286 #define ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT (0x1 << 31)
2287
2288 /* AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON */
2289 #define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT 31
2290 #define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK 0x1
2291 #define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT (0x1 << 31)
2292
2293 /* AFE_TINY_CONN0 */
2294 #define O_3_CFG_SFT 24
2295 #define O_3_CFG_MASK 0x1f
2296 #define O_3_CFG_MASK_SFT (0x1f << 24)
2297 #define O_2_CFG_SFT 16
2298 #define O_2_CFG_MASK 0x1f
2299 #define O_2_CFG_MASK_SFT (0x1f << 16)
2300 #define O_1_CFG_SFT 8
2301 #define O_1_CFG_MASK 0x1f
2302 #define O_1_CFG_MASK_SFT (0x1f << 8)
2303 #define O_0_CFG_SFT 0
2304 #define O_0_CFG_MASK 0x1f
2305 #define O_0_CFG_MASK_SFT (0x1f << 0)
2306
2307 /* AFE_TINY_CONN5 */
2308 #define O_23_CFG_SFT 24
2309 #define O_23_CFG_MASK 0x1f
2310 #define O_23_CFG_MASK_SFT (0x1f << 24)
2311 #define O_22_CFG_SFT 16
2312 #define O_22_CFG_MASK 0x1f
2313 #define O_22_CFG_MASK_SFT (0x1f << 16)
2314 #define O_21_CFG_SFT 8
2315 #define O_21_CFG_MASK 0x1f
2316 #define O_21_CFG_MASK_SFT (0x1f << 8)
2317 #define O_20_CFG_SFT 0
2318 #define O_20_CFG_MASK 0x1f
2319 #define O_20_CFG_MASK_SFT (0x1f << 0)
2320
2321 /* AFE_MEMIF_CONN */
2322 #define VUL6_USE_TINY_SFT 8
2323 #define VUL6_USE_TINY_MASK 1
2324 #define VUL6_USE_TINY_MASK_SFT (0x1 << 8)
2325 #define VUL5_USE_TINY_SFT 7
2326 #define VUL5_USE_TINY_MASK 1
2327 #define VUL5_USE_TINY_MASK_SFT (0x1 << 7)
2328 #define VUL4_USE_TINY_SFT 6
2329 #define VUL4_USE_TINY_MASK 1
2330 #define VUL4_USE_TINY_MASK_SFT (0x1 << 6)
2331 #define VUL3_USE_TINY_SFT 5
2332 #define VUL3_USE_TINY_MASK 1
2333 #define VUL3_USE_TINY_MASK_SFT (0x1 << 5)
2334 #define AWB2_USE_TINY_SFT 4
2335 #define AWB2_USE_TINY_MASK 1
2336 #define AWB2_USE_TINY_MASK_SFT (0x1 << 4)
2337 #define AWB_USE_TINY_SFT 3
2338 #define AWB_USE_TINY_MASK 1
2339 #define AWB_USE_TINY_MASK_SFT (0x1 << 3)
2340 #define VUL12_USE_TINY_SFT 2
2341 #define VUL12_USE_TINY_MASK 1
2342 #define VUL12_USE_TINY_MASK_SFT (0x1 << 2)
2343 #define VUL2_USE_TINY_SFT 1
2344 #define VUL2_USE_TINY_MASK 1
2345 #define VUL2_USE_TINY_MASK_SFT (0x1 << 1)
2346 #define VUL1_USE_TINY_SFT 0
2347 #define VUL1_USE_TINY_MASK 1
2348 #define VUL1_USE_TINY_MASK_SFT (0x1 << 0)
2349
2350 /* AFE_ASRC_2CH_CON0 */
2351 #define CON0_CHSET_STR_CLR_SFT 4
2352 #define CON0_CHSET_STR_CLR_MASK 1
2353 #define CON0_CHSET_STR_CLR_MASK_SFT (0x1 << 4)
2354 #define CON0_ASM_ON_SFT 0
2355 #define CON0_ASM_ON_MASK 1
2356 #define CON0_ASM_ON_MASK_SFT (0x1 << 0)
2357
2358 /* AFE_ASRC_2CH_CON5 */
2359 #define CALI_EN_SFT 0
2360 #define CALI_EN_MASK 1
2361 #define CALI_EN_MASK_SFT (0x1 << 0)
2362
2363 #define AUDIO_TOP_CON0 0x0000
2364 #define AUDIO_TOP_CON1 0x0004
2365 #define AUDIO_TOP_CON2 0x0008
2366 #define AUDIO_TOP_CON3 0x000c
2367 #define AFE_DAC_CON0 0x0010
2368 #define AFE_I2S_CON 0x0018
2369 #define AFE_CONN0 0x0020
2370 #define AFE_CONN1 0x0024
2371 #define AFE_CONN2 0x0028
2372 #define AFE_CONN3 0x002c
2373 #define AFE_CONN4 0x0030
2374 #define AFE_I2S_CON1 0x0034
2375 #define AFE_I2S_CON2 0x0038
2376 #define AFE_I2S_CON3 0x0040
2377 #define AFE_CONN5 0x0044
2378 #define AFE_CONN_24BIT 0x0048
2379 #define AFE_DL1_CON0 0x004c
2380 #define AFE_DL1_BASE_MSB 0x0050
2381 #define AFE_DL1_BASE 0x0054
2382 #define AFE_DL1_CUR_MSB 0x0058
2383 #define AFE_DL1_CUR 0x005c
2384 #define AFE_DL1_END_MSB 0x0060
2385 #define AFE_DL1_END 0x0064
2386 #define AFE_DL2_CON0 0x0068
2387 #define AFE_DL2_BASE_MSB 0x006c
2388 #define AFE_DL2_BASE 0x0070
2389 #define AFE_DL2_CUR_MSB 0x0074
2390 #define AFE_DL2_CUR 0x0078
2391 #define AFE_DL2_END_MSB 0x007c
2392 #define AFE_DL2_END 0x0080
2393 #define AFE_DL3_CON0 0x0084
2394 #define AFE_DL3_BASE_MSB 0x0088
2395 #define AFE_DL3_BASE 0x008c
2396 #define AFE_DL3_CUR_MSB 0x0090
2397 #define AFE_DL3_CUR 0x0094
2398 #define AFE_DL3_END_MSB 0x0098
2399 #define AFE_DL3_END 0x009c
2400 #define AFE_CONN6 0x00bc
2401 #define AFE_DL4_CON0 0x00cc
2402 #define AFE_DL4_BASE_MSB 0x00d0
2403 #define AFE_DL4_BASE 0x00d4
2404 #define AFE_DL4_CUR_MSB 0x00d8
2405 #define AFE_DL4_CUR 0x00dc
2406 #define AFE_DL4_END_MSB 0x00e0
2407 #define AFE_DL4_END 0x00e4
2408 #define AFE_DL12_CON0 0x00e8
2409 #define AFE_DL12_BASE_MSB 0x00ec
2410 #define AFE_DL12_BASE 0x00f0
2411 #define AFE_DL12_CUR_MSB 0x00f4
2412 #define AFE_DL12_CUR 0x00f8
2413 #define AFE_DL12_END_MSB 0x00fc
2414 #define AFE_DL12_END 0x0100
2415 #define AFE_ADDA_DL_SRC2_CON0 0x0108
2416 #define AFE_ADDA_DL_SRC2_CON1 0x010c
2417 #define AFE_ADDA_UL_SRC_CON0 0x0114
2418 #define AFE_ADDA_UL_SRC_CON1 0x0118
2419 #define AFE_ADDA_TOP_CON0 0x0120
2420 #define AFE_ADDA_UL_DL_CON0 0x0124
2421 #define AFE_ADDA_SRC_DEBUG 0x012c
2422 #define AFE_ADDA_SRC_DEBUG_MON0 0x0130
2423 #define AFE_ADDA_SRC_DEBUG_MON1 0x0134
2424 #define AFE_ADDA_UL_SRC_MON0 0x0148
2425 #define AFE_ADDA_UL_SRC_MON1 0x014c
2426 #define AFE_SECURE_CON0 0x0150
2427 #define AFE_SRAM_BOUND 0x0154
2428 #define AFE_SECURE_CON1 0x0158
2429 #define AFE_SECURE_CONN0 0x015c
2430 #define AFE_VUL_CON0 0x0170
2431 #define AFE_VUL_BASE_MSB 0x0174
2432 #define AFE_VUL_BASE 0x0178
2433 #define AFE_VUL_CUR_MSB 0x017c
2434 #define AFE_VUL_CUR 0x0180
2435 #define AFE_VUL_END_MSB 0x0184
2436 #define AFE_VUL_END 0x0188
2437 #define AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON 0x018c
2438 #define AFE_ADDA_3RD_DAC_DL_SRC2_CON0 0x0190
2439 #define AFE_ADDA_3RD_DAC_DL_SRC2_CON1 0x0194
2440 #define AFE_ADDA_3RD_DAC_PREDIS_CON0 0x01a0
2441 #define AFE_ADDA_3RD_DAC_PREDIS_CON1 0x01a4
2442 #define AFE_ADDA_3RD_DAC_PREDIS_CON2 0x01a8
2443 #define AFE_ADDA_3RD_DAC_PREDIS_CON3 0x01ac
2444 #define AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON 0x01b0
2445 #define AFE_ADDA_3RD_DAC_DL_SDM_TEST 0x01b4
2446 #define AFE_ADDA_3RD_DAC_DL_DC_COMP_CFG0 0x01b8
2447 #define AFE_ADDA_3RD_DAC_DL_DC_COMP_CFG1 0x01bc
2448 #define AFE_ADDA_3RD_DAC_DL_SDM_FIFO_MON 0x01c0
2449 #define AFE_ADDA_3RD_DAC_DL_SRC_LCH_MON 0x01c4
2450 #define AFE_ADDA_3RD_DAC_DL_SRC_RCH_MON 0x01c8
2451 #define AFE_ADDA_3RD_DAC_DL_SDM_OUT_MON 0x01cc
2452 #define AFE_SIDETONE_DEBUG 0x01d0
2453 #define AFE_SIDETONE_MON 0x01d4
2454 #define AFE_ADDA_3RD_DAC_DL_SDM_DITHER_CON 0x01d8
2455 #define AFE_SINEGEN_CON2 0x01dc
2456 #define AFE_SIDETONE_CON0 0x01e0
2457 #define AFE_SIDETONE_COEFF 0x01e4
2458 #define AFE_SIDETONE_CON1 0x01e8
2459 #define AFE_SIDETONE_GAIN 0x01ec
2460 #define AFE_SINEGEN_CON0 0x01f0
2461 #define AFE_I2S_MON2 0x01f8
2462 #define AFE_SINEGEN_CON_TDM 0x01fc
2463 #define AFE_TOP_CON0 0x0200
2464 #define AFE_VUL2_CON0 0x020c
2465 #define AFE_VUL2_BASE_MSB 0x0210
2466 #define AFE_VUL2_BASE 0x0214
2467 #define AFE_VUL2_CUR_MSB 0x0218
2468 #define AFE_VUL2_CUR 0x021c
2469 #define AFE_VUL2_END_MSB 0x0220
2470 #define AFE_VUL2_END 0x0224
2471 #define AFE_VUL3_CON0 0x0228
2472 #define AFE_VUL3_BASE_MSB 0x022c
2473 #define AFE_VUL3_BASE 0x0230
2474 #define AFE_VUL3_CUR_MSB 0x0234
2475 #define AFE_VUL3_CUR 0x0238
2476 #define AFE_VUL3_END_MSB 0x023c
2477 #define AFE_VUL3_END 0x0240
2478 #define AFE_BUSY 0x0244
2479 #define AFE_BUS_CFG 0x0250
2480 #define AFE_ADDA_PREDIS_CON0 0x0260
2481 #define AFE_ADDA_PREDIS_CON1 0x0264
2482 #define AFE_I2S_MON 0x027c
2483 #define AFE_ADDA_IIR_COEF_02_01 0x0290
2484 #define AFE_ADDA_IIR_COEF_04_03 0x0294
2485 #define AFE_ADDA_IIR_COEF_06_05 0x0298
2486 #define AFE_ADDA_IIR_COEF_08_07 0x029c
2487 #define AFE_ADDA_IIR_COEF_10_09 0x02a0
2488 #define AFE_IRQ_MCU_CON1 0x02e4
2489 #define AFE_IRQ_MCU_CON2 0x02e8
2490 #define AFE_DAC_MON 0x02ec
2491 #define AFE_IRQ_MCU_CON3 0x02f0
2492 #define AFE_IRQ_MCU_CON4 0x02f4
2493 #define AFE_IRQ_MCU_CNT0 0x0300
2494 #define AFE_IRQ_MCU_CNT6 0x0304
2495 #define AFE_IRQ_MCU_CNT8 0x0308
2496 #define AFE_IRQ_MCU_DSP2_EN 0x030c
2497 #define AFE_IRQ0_MCU_CNT_MON 0x0310
2498 #define AFE_IRQ6_MCU_CNT_MON 0x0314
2499 #define AFE_VUL4_CON0 0x0358
2500 #define AFE_VUL4_BASE_MSB 0x035c
2501 #define AFE_VUL4_BASE 0x0360
2502 #define AFE_VUL4_CUR_MSB 0x0364
2503 #define AFE_VUL4_CUR 0x0368
2504 #define AFE_VUL4_END_MSB 0x036c
2505 #define AFE_VUL4_END 0x0370
2506 #define AFE_VUL12_CON0 0x0374
2507 #define AFE_VUL12_BASE_MSB 0x0378
2508 #define AFE_VUL12_BASE 0x037c
2509 #define AFE_VUL12_CUR_MSB 0x0380
2510 #define AFE_VUL12_CUR 0x0384
2511 #define AFE_VUL12_END_MSB 0x0388
2512 #define AFE_VUL12_END 0x038c
2513 #define AFE_HDMI_CONN0 0x0390
2514 #define AFE_IRQ3_MCU_CNT_MON 0x0398
2515 #define AFE_IRQ4_MCU_CNT_MON 0x039c
2516 #define AFE_IRQ_MCU_CON0 0x03a0
2517 #define AFE_IRQ_MCU_STATUS 0x03a4
2518 #define AFE_IRQ_MCU_CLR 0x03a8
2519 #define AFE_IRQ_MCU_CNT1 0x03ac
2520 #define AFE_IRQ_MCU_CNT2 0x03b0
2521 #define AFE_IRQ_MCU_EN 0x03b4
2522 #define AFE_IRQ_MCU_MON2 0x03b8
2523 #define AFE_IRQ_MCU_CNT5 0x03bc
2524 #define AFE_IRQ1_MCU_CNT_MON 0x03c0
2525 #define AFE_IRQ2_MCU_CNT_MON 0x03c4
2526 #define AFE_IRQ5_MCU_CNT_MON 0x03cc
2527 #define AFE_IRQ_MCU_DSP_EN 0x03d0
2528 #define AFE_IRQ_MCU_SCP_EN 0x03d4
2529 #define AFE_IRQ_MCU_CNT7 0x03dc
2530 #define AFE_IRQ7_MCU_CNT_MON 0x03e0
2531 #define AFE_IRQ_MCU_CNT3 0x03e4
2532 #define AFE_IRQ_MCU_CNT4 0x03e8
2533 #define AFE_IRQ_MCU_CNT11 0x03ec
2534 #define AFE_APLL1_TUNER_CFG 0x03f0
2535 #define AFE_APLL2_TUNER_CFG 0x03f4
2536 #define AFE_IRQ_MCU_MISS_CLR 0x03f8
2537 #define AFE_CONN33 0x0408
2538 #define AFE_IRQ_MCU_CNT12 0x040c
2539 #define AFE_GAIN1_CON0 0x0410
2540 #define AFE_GAIN1_CON1 0x0414
2541 #define AFE_GAIN1_CON2 0x0418
2542 #define AFE_GAIN1_CON3 0x041c
2543 #define AFE_CONN7 0x0420
2544 #define AFE_GAIN1_CUR 0x0424
2545 #define AFE_GAIN2_CON0 0x0428
2546 #define AFE_GAIN2_CON1 0x042c
2547 #define AFE_GAIN2_CON2 0x0430
2548 #define AFE_GAIN2_CON3 0x0434
2549 #define AFE_CONN8 0x0438
2550 #define AFE_GAIN2_CUR 0x043c
2551 #define AFE_CONN9 0x0440
2552 #define AFE_CONN10 0x0444
2553 #define AFE_CONN11 0x0448
2554 #define AFE_CONN12 0x044c
2555 #define AFE_CONN13 0x0450
2556 #define AFE_CONN14 0x0454
2557 #define AFE_CONN15 0x0458
2558 #define AFE_CONN16 0x045c
2559 #define AFE_CONN17 0x0460
2560 #define AFE_CONN18 0x0464
2561 #define AFE_CONN19 0x0468
2562 #define AFE_CONN20 0x046c
2563 #define AFE_CONN21 0x0470
2564 #define AFE_CONN22 0x0474
2565 #define AFE_CONN23 0x0478
2566 #define AFE_CONN24 0x047c
2567 #define AFE_CONN_RS 0x0494
2568 #define AFE_CONN_DI 0x0498
2569 #define AFE_CONN25 0x04b0
2570 #define AFE_CONN26 0x04b4
2571 #define AFE_CONN27 0x04b8
2572 #define AFE_CONN28 0x04bc
2573 #define AFE_CONN29 0x04c0
2574 #define AFE_CONN30 0x04c4
2575 #define AFE_CONN31 0x04c8
2576 #define AFE_CONN32 0x04cc
2577 #define AFE_SRAM_DELSEL_CON1 0x04f4
2578 #define AFE_CONN56 0x0500
2579 #define AFE_CONN57 0x0504
2580 #define AFE_CONN56_1 0x0510
2581 #define AFE_CONN57_1 0x0514
2582 #define AFE_TINY_CONN2 0x0520
2583 #define AFE_TINY_CONN3 0x0524
2584 #define AFE_TINY_CONN4 0x0528
2585 #define AFE_TINY_CONN5 0x052c
2586 #define PCM_INTF_CON1 0x0530
2587 #define PCM_INTF_CON2 0x0538
2588 #define PCM2_INTF_CON 0x053c
2589 #define AFE_TDM_CON1 0x0548
2590 #define AFE_TDM_CON2 0x054c
2591 #define AFE_I2S_CON6 0x0564
2592 #define AFE_I2S_CON7 0x0568
2593 #define AFE_I2S_CON8 0x056c
2594 #define AFE_I2S_CON9 0x0570
2595 #define AFE_CONN34 0x0580
2596 #define FPGA_CFG0 0x05b0
2597 #define FPGA_CFG1 0x05b4
2598 #define FPGA_CFG2 0x05c0
2599 #define FPGA_CFG3 0x05c4
2600 #define AUDIO_TOP_DBG_CON 0x05c8
2601 #define AUDIO_TOP_DBG_MON0 0x05cc
2602 #define AUDIO_TOP_DBG_MON1 0x05d0
2603 #define AFE_IRQ8_MCU_CNT_MON 0x05e4
2604 #define AFE_IRQ11_MCU_CNT_MON 0x05e8
2605 #define AFE_IRQ12_MCU_CNT_MON 0x05ec
2606 #define AFE_IRQ_MCU_CNT9 0x0600
2607 #define AFE_IRQ_MCU_CNT10 0x0604
2608 #define AFE_IRQ_MCU_CNT13 0x0608
2609 #define AFE_IRQ_MCU_CNT14 0x060c
2610 #define AFE_IRQ_MCU_CNT15 0x0610
2611 #define AFE_IRQ_MCU_CNT16 0x0614
2612 #define AFE_IRQ_MCU_CNT17 0x0618
2613 #define AFE_IRQ_MCU_CNT18 0x061c
2614 #define AFE_IRQ_MCU_CNT19 0x0620
2615 #define AFE_IRQ_MCU_CNT20 0x0624
2616 #define AFE_IRQ_MCU_CNT21 0x0628
2617 #define AFE_IRQ_MCU_CNT22 0x062c
2618 #define AFE_IRQ_MCU_CNT23 0x0630
2619 #define AFE_IRQ_MCU_CNT24 0x0634
2620 #define AFE_IRQ_MCU_CNT25 0x0638
2621 #define AFE_IRQ_MCU_CNT26 0x063c
2622 #define AFE_IRQ_MCU_CNT31 0x0640
2623 #define AFE_TINY_CONN6 0x0650
2624 #define AFE_TINY_CONN7 0x0654
2625 #define AFE_IRQ9_MCU_CNT_MON 0x0660
2626 #define AFE_IRQ10_MCU_CNT_MON 0x0664
2627 #define AFE_IRQ13_MCU_CNT_MON 0x0668
2628 #define AFE_IRQ14_MCU_CNT_MON 0x066c
2629 #define AFE_IRQ15_MCU_CNT_MON 0x0670
2630 #define AFE_IRQ16_MCU_CNT_MON 0x0674
2631 #define AFE_IRQ17_MCU_CNT_MON 0x0678
2632 #define AFE_IRQ18_MCU_CNT_MON 0x067c
2633 #define AFE_IRQ19_MCU_CNT_MON 0x0680
2634 #define AFE_IRQ20_MCU_CNT_MON 0x0684
2635 #define AFE_IRQ21_MCU_CNT_MON 0x0688
2636 #define AFE_IRQ22_MCU_CNT_MON 0x068c
2637 #define AFE_IRQ23_MCU_CNT_MON 0x0690
2638 #define AFE_IRQ24_MCU_CNT_MON 0x0694
2639 #define AFE_IRQ25_MCU_CNT_MON 0x0698
2640 #define AFE_IRQ26_MCU_CNT_MON 0x069c
2641 #define AFE_IRQ31_MCU_CNT_MON 0x06a0
2642 #define AFE_GENERAL_REG0 0x0800
2643 #define AFE_GENERAL_REG1 0x0804
2644 #define AFE_GENERAL_REG2 0x0808
2645 #define AFE_GENERAL_REG3 0x080c
2646 #define AFE_GENERAL_REG4 0x0810
2647 #define AFE_GENERAL_REG5 0x0814
2648 #define AFE_GENERAL_REG6 0x0818
2649 #define AFE_GENERAL_REG7 0x081c
2650 #define AFE_GENERAL_REG8 0x0820
2651 #define AFE_GENERAL_REG9 0x0824
2652 #define AFE_GENERAL_REG10 0x0828
2653 #define AFE_GENERAL_REG11 0x082c
2654 #define AFE_GENERAL_REG12 0x0830
2655 #define AFE_GENERAL_REG13 0x0834
2656 #define AFE_GENERAL_REG14 0x0838
2657 #define AFE_GENERAL_REG15 0x083c
2658 #define AFE_CBIP_CFG0 0x0840
2659 #define AFE_CBIP_MON0 0x0844
2660 #define AFE_CBIP_SLV_MUX_MON0 0x0848
2661 #define AFE_CBIP_SLV_DECODER_MON0 0x084c
2662 #define AFE_ADDA6_MTKAIF_MON0 0x0854
2663 #define AFE_ADDA6_MTKAIF_MON1 0x0858
2664 #define AFE_AWB_CON0 0x085c
2665 #define AFE_AWB_BASE_MSB 0x0860
2666 #define AFE_AWB_BASE 0x0864
2667 #define AFE_AWB_CUR_MSB 0x0868
2668 #define AFE_AWB_CUR 0x086c
2669 #define AFE_AWB_END_MSB 0x0870
2670 #define AFE_AWB_END 0x0874
2671 #define AFE_AWB2_CON0 0x0878
2672 #define AFE_AWB2_BASE_MSB 0x087c
2673 #define AFE_AWB2_BASE 0x0880
2674 #define AFE_AWB2_CUR_MSB 0x0884
2675 #define AFE_AWB2_CUR 0x0888
2676 #define AFE_AWB2_END_MSB 0x088c
2677 #define AFE_AWB2_END 0x0890
2678 #define AFE_DAI_CON0 0x0894
2679 #define AFE_DAI_BASE_MSB 0x0898
2680 #define AFE_DAI_BASE 0x089c
2681 #define AFE_DAI_CUR_MSB 0x08a0
2682 #define AFE_DAI_CUR 0x08a4
2683 #define AFE_DAI_END_MSB 0x08a8
2684 #define AFE_DAI_END 0x08ac
2685 #define AFE_DAI2_CON0 0x08b0
2686 #define AFE_DAI2_BASE_MSB 0x08b4
2687 #define AFE_DAI2_BASE 0x08b8
2688 #define AFE_DAI2_CUR_MSB 0x08bc
2689 #define AFE_DAI2_CUR 0x08c0
2690 #define AFE_DAI2_END_MSB 0x08c4
2691 #define AFE_DAI2_END 0x08c8
2692 #define AFE_MEMIF_CON0 0x08cc
2693 #define AFE_CONN0_1 0x0900
2694 #define AFE_CONN1_1 0x0904
2695 #define AFE_CONN2_1 0x0908
2696 #define AFE_CONN3_1 0x090c
2697 #define AFE_CONN4_1 0x0910
2698 #define AFE_CONN5_1 0x0914
2699 #define AFE_CONN6_1 0x0918
2700 #define AFE_CONN7_1 0x091c
2701 #define AFE_CONN8_1 0x0920
2702 #define AFE_CONN9_1 0x0924
2703 #define AFE_CONN10_1 0x0928
2704 #define AFE_CONN11_1 0x092c
2705 #define AFE_CONN12_1 0x0930
2706 #define AFE_CONN13_1 0x0934
2707 #define AFE_CONN14_1 0x0938
2708 #define AFE_CONN15_1 0x093c
2709 #define AFE_CONN16_1 0x0940
2710 #define AFE_CONN17_1 0x0944
2711 #define AFE_CONN18_1 0x0948
2712 #define AFE_CONN19_1 0x094c
2713 #define AFE_CONN20_1 0x0950
2714 #define AFE_CONN21_1 0x0954
2715 #define AFE_CONN22_1 0x0958
2716 #define AFE_CONN23_1 0x095c
2717 #define AFE_CONN24_1 0x0960
2718 #define AFE_CONN25_1 0x0964
2719 #define AFE_CONN26_1 0x0968
2720 #define AFE_CONN27_1 0x096c
2721 #define AFE_CONN28_1 0x0970
2722 #define AFE_CONN29_1 0x0974
2723 #define AFE_CONN30_1 0x0978
2724 #define AFE_CONN31_1 0x097c
2725 #define AFE_CONN32_1 0x0980
2726 #define AFE_CONN33_1 0x0984
2727 #define AFE_CONN34_1 0x0988
2728 #define AFE_CONN_RS_1 0x098c
2729 #define AFE_CONN_DI_1 0x0990
2730 #define AFE_CONN_24BIT_1 0x0994
2731 #define AFE_CONN_REG 0x0998
2732 #define AFE_CONN35 0x09a0
2733 #define AFE_CONN36 0x09a4
2734 #define AFE_CONN37 0x09a8
2735 #define AFE_CONN38 0x09ac
2736 #define AFE_CONN35_1 0x09b0
2737 #define AFE_CONN36_1 0x09b4
2738 #define AFE_CONN37_1 0x09b8
2739 #define AFE_CONN38_1 0x09bc
2740 #define AFE_CONN39 0x09c0
2741 #define AFE_CONN40 0x09c4
2742 #define AFE_CONN41 0x09c8
2743 #define AFE_CONN42 0x09cc
2744 #define AFE_SGEN_CON_SGEN32 0x09d0
2745 #define AFE_CONN39_1 0x09e0
2746 #define AFE_CONN40_1 0x09e4
2747 #define AFE_CONN41_1 0x09e8
2748 #define AFE_CONN42_1 0x09ec
2749 #define AFE_I2S_CON4 0x09f8
2750 #define AFE_ADDA6_TOP_CON0 0x0a80
2751 #define AFE_ADDA6_UL_SRC_CON0 0x0a84
2752 #define AFE_ADDA6_UL_SRC_CON1 0x0a88
2753 #define AFE_ADDA6_SRC_DEBUG 0x0a8c
2754 #define AFE_ADDA6_SRC_DEBUG_MON0 0x0a90
2755 #define AFE_ADDA6_ULCF_CFG_02_01 0x0aa0
2756 #define AFE_ADDA6_ULCF_CFG_04_03 0x0aa4
2757 #define AFE_ADDA6_ULCF_CFG_06_05 0x0aa8
2758 #define AFE_ADDA6_ULCF_CFG_08_07 0x0aac
2759 #define AFE_ADDA6_ULCF_CFG_10_09 0x0ab0
2760 #define AFE_ADDA6_ULCF_CFG_12_11 0x0ab4
2761 #define AFE_ADDA6_ULCF_CFG_14_13 0x0ab8
2762 #define AFE_ADDA6_ULCF_CFG_16_15 0x0abc
2763 #define AFE_ADDA6_ULCF_CFG_18_17 0x0ac0
2764 #define AFE_ADDA6_ULCF_CFG_20_19 0x0ac4
2765 #define AFE_ADDA6_ULCF_CFG_22_21 0x0ac8
2766 #define AFE_ADDA6_ULCF_CFG_24_23 0x0acc
2767 #define AFE_ADDA6_ULCF_CFG_26_25 0x0ad0
2768 #define AFE_ADDA6_ULCF_CFG_28_27 0x0ad4
2769 #define AFE_ADDA6_ULCF_CFG_30_29 0x0ad8
2770 #define AFE_ADD6A_UL_SRC_MON0 0x0ae4
2771 #define AFE_ADDA6_UL_SRC_MON1 0x0ae8
2772 #define AFE_TINY_CONN0 0x0af0
2773 #define AFE_TINY_CONN1 0x0af4
2774 #define AFE_CONN43 0x0af8
2775 #define AFE_CONN43_1 0x0afc
2776 #define AFE_MOD_DAI_CON0 0x0b00
2777 #define AFE_MOD_DAI_BASE_MSB 0x0b04
2778 #define AFE_MOD_DAI_BASE 0x0b08
2779 #define AFE_MOD_DAI_CUR_MSB 0x0b0c
2780 #define AFE_MOD_DAI_CUR 0x0b10
2781 #define AFE_MOD_DAI_END_MSB 0x0b14
2782 #define AFE_MOD_DAI_END 0x0b18
2783 #define AFE_HDMI_OUT_CON0 0x0b1c
2784 #define AFE_HDMI_OUT_BASE_MSB 0x0b20
2785 #define AFE_HDMI_OUT_BASE 0x0b24
2786 #define AFE_HDMI_OUT_CUR_MSB 0x0b28
2787 #define AFE_HDMI_OUT_CUR 0x0b2c
2788 #define AFE_HDMI_OUT_END_MSB 0x0b30
2789 #define AFE_HDMI_OUT_END 0x0b34
2790 #define AFE_AWB_RCH_MON 0x0b70
2791 #define AFE_AWB_LCH_MON 0x0b74
2792 #define AFE_VUL_RCH_MON 0x0b78
2793 #define AFE_VUL_LCH_MON 0x0b7c
2794 #define AFE_VUL12_RCH_MON 0x0b80
2795 #define AFE_VUL12_LCH_MON 0x0b84
2796 #define AFE_VUL2_RCH_MON 0x0b88
2797 #define AFE_VUL2_LCH_MON 0x0b8c
2798 #define AFE_DAI_DATA_MON 0x0b90
2799 #define AFE_MOD_DAI_DATA_MON 0x0b94
2800 #define AFE_DAI2_DATA_MON 0x0b98
2801 #define AFE_AWB2_RCH_MON 0x0b9c
2802 #define AFE_AWB2_LCH_MON 0x0ba0
2803 #define AFE_VUL3_RCH_MON 0x0ba4
2804 #define AFE_VUL3_LCH_MON 0x0ba8
2805 #define AFE_VUL4_RCH_MON 0x0bac
2806 #define AFE_VUL4_LCH_MON 0x0bb0
2807 #define AFE_VUL5_RCH_MON 0x0bb4
2808 #define AFE_VUL5_LCH_MON 0x0bb8
2809 #define AFE_VUL6_RCH_MON 0x0bbc
2810 #define AFE_VUL6_LCH_MON 0x0bc0
2811 #define AFE_DL1_RCH_MON 0x0bc4
2812 #define AFE_DL1_LCH_MON 0x0bc8
2813 #define AFE_DL2_RCH_MON 0x0bcc
2814 #define AFE_DL2_LCH_MON 0x0bd0
2815 #define AFE_DL12_RCH1_MON 0x0bd4
2816 #define AFE_DL12_LCH1_MON 0x0bd8
2817 #define AFE_DL12_RCH2_MON 0x0bdc
2818 #define AFE_DL12_LCH2_MON 0x0be0
2819 #define AFE_DL3_RCH_MON 0x0be4
2820 #define AFE_DL3_LCH_MON 0x0be8
2821 #define AFE_DL4_RCH_MON 0x0bec
2822 #define AFE_DL4_LCH_MON 0x0bf0
2823 #define AFE_DL5_RCH_MON 0x0bf4
2824 #define AFE_DL5_LCH_MON 0x0bf8
2825 #define AFE_DL6_RCH_MON 0x0bfc
2826 #define AFE_DL6_LCH_MON 0x0c00
2827 #define AFE_DL7_RCH_MON 0x0c04
2828 #define AFE_DL7_LCH_MON 0x0c08
2829 #define AFE_DL8_RCH_MON 0x0c0c
2830 #define AFE_DL8_LCH_MON 0x0c10
2831 #define AFE_VUL5_CON0 0x0c14
2832 #define AFE_VUL5_BASE_MSB 0x0c18
2833 #define AFE_VUL5_BASE 0x0c1c
2834 #define AFE_VUL5_CUR_MSB 0x0c20
2835 #define AFE_VUL5_CUR 0x0c24
2836 #define AFE_VUL5_END_MSB 0x0c28
2837 #define AFE_VUL5_END 0x0c2c
2838 #define AFE_VUL6_CON0 0x0c30
2839 #define AFE_VUL6_BASE_MSB 0x0c34
2840 #define AFE_VUL6_BASE 0x0c38
2841 #define AFE_VUL6_CUR_MSB 0x0c3c
2842 #define AFE_VUL6_CUR 0x0c40
2843 #define AFE_VUL6_END_MSB 0x0c44
2844 #define AFE_VUL6_END 0x0c48
2845 #define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c50
2846 #define AFE_ADDA_DL_SDM_TEST 0x0c54
2847 #define AFE_ADDA_DL_DC_COMP_CFG0 0x0c58
2848 #define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c
2849 #define AFE_ADDA_DL_SDM_FIFO_MON 0x0c60
2850 #define AFE_ADDA_DL_SRC_LCH_MON 0x0c64
2851 #define AFE_ADDA_DL_SRC_RCH_MON 0x0c68
2852 #define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c
2853 #define AFE_ADDA_DL_SDM_DITHER_CON 0x0c70
2854 #define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x0c74
2855 #define AFE_CONNSYS_I2S_CON 0x0c78
2856 #define AFE_CONNSYS_I2S_MON 0x0c7c
2857 #define AFE_ASRC_2CH_CON0 0x0c80
2858 #define AFE_ASRC_2CH_CON1 0x0c84
2859 #define AFE_ASRC_2CH_CON2 0x0c88
2860 #define AFE_ASRC_2CH_CON3 0x0c8c
2861 #define AFE_ASRC_2CH_CON4 0x0c90
2862 #define AFE_ASRC_2CH_CON5 0x0c94
2863 #define AFE_ASRC_2CH_CON6 0x0c98
2864 #define AFE_ASRC_2CH_CON7 0x0c9c
2865 #define AFE_ASRC_2CH_CON8 0x0ca0
2866 #define AFE_ASRC_2CH_CON9 0x0ca4
2867 #define AFE_ASRC_2CH_CON10 0x0ca8
2868 #define AFE_ASRC_2CH_CON12 0x0cb0
2869 #define AFE_ASRC_2CH_CON13 0x0cb4
2870 #define AFE_ADDA6_IIR_COEF_02_01 0x0ce0
2871 #define AFE_ADDA6_IIR_COEF_04_03 0x0ce4
2872 #define AFE_ADDA6_IIR_COEF_06_05 0x0ce8
2873 #define AFE_ADDA6_IIR_COEF_08_07 0x0cec
2874 #define AFE_ADDA6_IIR_COEF_10_09 0x0cf0
2875 #define AFE_SE_PROT_SIDEBAND 0x0d38
2876 #define AFE_SE_DOMAIN_SIDEBAND0 0x0d3c
2877 #define AFE_ADDA_PREDIS_CON2 0x0d40
2878 #define AFE_ADDA_PREDIS_CON3 0x0d44
2879 #define AFE_MEMIF_CONN 0x0d50
2880 #define AFE_SE_DOMAIN_SIDEBAND1 0x0d54
2881 #define AFE_SE_DOMAIN_SIDEBAND2 0x0d58
2882 #define AFE_SE_DOMAIN_SIDEBAND3 0x0d5c
2883 #define AFE_CONN44 0x0d70
2884 #define AFE_CONN45 0x0d74
2885 #define AFE_CONN46 0x0d78
2886 #define AFE_CONN47 0x0d7c
2887 #define AFE_CONN44_1 0x0d80
2888 #define AFE_CONN45_1 0x0d84
2889 #define AFE_CONN46_1 0x0d88
2890 #define AFE_CONN47_1 0x0d8c
2891 #define AFE_DL9_CUR_MSB 0x0dc0
2892 #define AFE_DL9_CUR 0x0dc4
2893 #define AFE_DL9_END_MSB 0x0dc8
2894 #define AFE_DL9_END 0x0dcc
2895 #define AFE_HD_ENGEN_ENABLE 0x0dd0
2896 #define AFE_ADDA_DL_NLE_FIFO_MON 0x0dfc
2897 #define AFE_ADDA_MTKAIF_CFG0 0x0e00
2898 #define AFE_ADDA_MTKAIF_SYNCWORD_CFG 0x0e14
2899 #define AFE_ADDA_MTKAIF_RX_CFG0 0x0e20
2900 #define AFE_ADDA_MTKAIF_RX_CFG1 0x0e24
2901 #define AFE_ADDA_MTKAIF_RX_CFG2 0x0e28
2902 #define AFE_ADDA_MTKAIF_MON0 0x0e34
2903 #define AFE_ADDA_MTKAIF_MON1 0x0e38
2904 #define AFE_AUD_PAD_TOP 0x0e40
2905 #define AFE_DL_NLE_R_CFG0 0x0e44
2906 #define AFE_DL_NLE_R_CFG1 0x0e48
2907 #define AFE_DL_NLE_L_CFG0 0x0e4c
2908 #define AFE_DL_NLE_L_CFG1 0x0e50
2909 #define AFE_DL_NLE_R_MON0 0x0e54
2910 #define AFE_DL_NLE_R_MON1 0x0e58
2911 #define AFE_DL_NLE_R_MON2 0x0e5c
2912 #define AFE_DL_NLE_L_MON0 0x0e60
2913 #define AFE_DL_NLE_L_MON1 0x0e64
2914 #define AFE_DL_NLE_L_MON2 0x0e68
2915 #define AFE_DL_NLE_GAIN_CFG0 0x0e6c
2916 #define AFE_ADDA6_MTKAIF_CFG0 0x0e70
2917 #define AFE_ADDA6_MTKAIF_RX_CFG0 0x0e74
2918 #define AFE_ADDA6_MTKAIF_RX_CFG1 0x0e78
2919 #define AFE_ADDA6_MTKAIF_RX_CFG2 0x0e7c
2920 #define AFE_GENERAL1_ASRC_2CH_CON0 0x0e80
2921 #define AFE_GENERAL1_ASRC_2CH_CON1 0x0e84
2922 #define AFE_GENERAL1_ASRC_2CH_CON2 0x0e88
2923 #define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c
2924 #define AFE_GENERAL1_ASRC_2CH_CON4 0x0e90
2925 #define AFE_GENERAL1_ASRC_2CH_CON5 0x0e94
2926 #define AFE_GENERAL1_ASRC_2CH_CON6 0x0e98
2927 #define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c
2928 #define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea0
2929 #define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea4
2930 #define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea8
2931 #define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb0
2932 #define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb4
2933 #define GENERAL_ASRC_MODE 0x0eb8
2934 #define GENERAL_ASRC_EN_ON 0x0ebc
2935 #define AFE_CONN48 0x0ec0
2936 #define AFE_CONN49 0x0ec4
2937 #define AFE_CONN50 0x0ec8
2938 #define AFE_CONN51 0x0ecc
2939 #define AFE_CONN52 0x0ed0
2940 #define AFE_CONN53 0x0ed4
2941 #define AFE_CONN54 0x0ed8
2942 #define AFE_CONN55 0x0edc
2943 #define AFE_CONN48_1 0x0ee0
2944 #define AFE_CONN49_1 0x0ee4
2945 #define AFE_CONN50_1 0x0ee8
2946 #define AFE_CONN51_1 0x0eec
2947 #define AFE_CONN52_1 0x0ef0
2948 #define AFE_CONN53_1 0x0ef4
2949 #define AFE_CONN54_1 0x0ef8
2950 #define AFE_CONN55_1 0x0efc
2951 #define AFE_GENERAL2_ASRC_2CH_CON0 0x0f00
2952 #define AFE_GENERAL2_ASRC_2CH_CON1 0x0f04
2953 #define AFE_GENERAL2_ASRC_2CH_CON2 0x0f08
2954 #define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c
2955 #define AFE_GENERAL2_ASRC_2CH_CON4 0x0f10
2956 #define AFE_GENERAL2_ASRC_2CH_CON5 0x0f14
2957 #define AFE_GENERAL2_ASRC_2CH_CON6 0x0f18
2958 #define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c
2959 #define AFE_GENERAL2_ASRC_2CH_CON8 0x0f20
2960 #define AFE_GENERAL2_ASRC_2CH_CON9 0x0f24
2961 #define AFE_GENERAL2_ASRC_2CH_CON10 0x0f28
2962 #define AFE_GENERAL2_ASRC_2CH_CON12 0x0f30
2963 #define AFE_GENERAL2_ASRC_2CH_CON13 0x0f34
2964 #define AFE_DL9_RCH_MON 0x0f38
2965 #define AFE_DL9_LCH_MON 0x0f3c
2966 #define AFE_DL5_CON0 0x0f4c
2967 #define AFE_DL5_BASE_MSB 0x0f50
2968 #define AFE_DL5_BASE 0x0f54
2969 #define AFE_DL5_CUR_MSB 0x0f58
2970 #define AFE_DL5_CUR 0x0f5c
2971 #define AFE_DL5_END_MSB 0x0f60
2972 #define AFE_DL5_END 0x0f64
2973 #define AFE_DL6_CON0 0x0f68
2974 #define AFE_DL6_BASE_MSB 0x0f6c
2975 #define AFE_DL6_BASE 0x0f70
2976 #define AFE_DL6_CUR_MSB 0x0f74
2977 #define AFE_DL6_CUR 0x0f78
2978 #define AFE_DL6_END_MSB 0x0f7c
2979 #define AFE_DL6_END 0x0f80
2980 #define AFE_DL7_CON0 0x0f84
2981 #define AFE_DL7_BASE_MSB 0x0f88
2982 #define AFE_DL7_BASE 0x0f8c
2983 #define AFE_DL7_CUR_MSB 0x0f90
2984 #define AFE_DL7_CUR 0x0f94
2985 #define AFE_DL7_END_MSB 0x0f98
2986 #define AFE_DL7_END 0x0f9c
2987 #define AFE_DL8_CON0 0x0fa0
2988 #define AFE_DL8_BASE_MSB 0x0fa4
2989 #define AFE_DL8_BASE 0x0fa8
2990 #define AFE_DL8_CUR_MSB 0x0fac
2991 #define AFE_DL8_CUR 0x0fb0
2992 #define AFE_DL8_END_MSB 0x0fb4
2993 #define AFE_DL8_END 0x0fb8
2994 #define AFE_DL9_CON0 0x0fbc
2995 #define AFE_DL9_BASE_MSB 0x0fc0
2996 #define AFE_DL9_BASE 0x0fc4
2997 #define AFE_SE_SECURE_CON 0x1004
2998 #define AFE_PROT_SIDEBAND_MON 0x1008
2999 #define AFE_DOMAIN_SIDEBAND0_MON 0x100c
3000 #define AFE_DOMAIN_SIDEBAND1_MON 0x1010
3001 #define AFE_DOMAIN_SIDEBAND2_MON 0x1014
3002 #define AFE_DOMAIN_SIDEBAND3_MON 0x1018
3003 #define AFE_SECURE_MASK_CONN0 0x1020
3004 #define AFE_SECURE_MASK_CONN1 0x1024
3005 #define AFE_SECURE_MASK_CONN2 0x1028
3006 #define AFE_SECURE_MASK_CONN3 0x102c
3007 #define AFE_SECURE_MASK_CONN4 0x1030
3008 #define AFE_SECURE_MASK_CONN5 0x1034
3009 #define AFE_SECURE_MASK_CONN6 0x1038
3010 #define AFE_SECURE_MASK_CONN7 0x103c
3011 #define AFE_SECURE_MASK_CONN8 0x1040
3012 #define AFE_SECURE_MASK_CONN9 0x1044
3013 #define AFE_SECURE_MASK_CONN10 0x1048
3014 #define AFE_SECURE_MASK_CONN11 0x104c
3015 #define AFE_SECURE_MASK_CONN12 0x1050
3016 #define AFE_SECURE_MASK_CONN13 0x1054
3017 #define AFE_SECURE_MASK_CONN14 0x1058
3018 #define AFE_SECURE_MASK_CONN15 0x105c
3019 #define AFE_SECURE_MASK_CONN16 0x1060
3020 #define AFE_SECURE_MASK_CONN17 0x1064
3021 #define AFE_SECURE_MASK_CONN18 0x1068
3022 #define AFE_SECURE_MASK_CONN19 0x106c
3023 #define AFE_SECURE_MASK_CONN20 0x1070
3024 #define AFE_SECURE_MASK_CONN21 0x1074
3025 #define AFE_SECURE_MASK_CONN22 0x1078
3026 #define AFE_SECURE_MASK_CONN23 0x107c
3027 #define AFE_SECURE_MASK_CONN24 0x1080
3028 #define AFE_SECURE_MASK_CONN25 0x1084
3029 #define AFE_SECURE_MASK_CONN26 0x1088
3030 #define AFE_SECURE_MASK_CONN27 0x108c
3031 #define AFE_SECURE_MASK_CONN28 0x1090
3032 #define AFE_SECURE_MASK_CONN29 0x1094
3033 #define AFE_SECURE_MASK_CONN30 0x1098
3034 #define AFE_SECURE_MASK_CONN31 0x109c
3035 #define AFE_SECURE_MASK_CONN32 0x10a0
3036 #define AFE_SECURE_MASK_CONN33 0x10a4
3037 #define AFE_SECURE_MASK_CONN34 0x10a8
3038 #define AFE_SECURE_MASK_CONN35 0x10ac
3039 #define AFE_SECURE_MASK_CONN36 0x10b0
3040 #define AFE_SECURE_MASK_CONN37 0x10b4
3041 #define AFE_SECURE_MASK_CONN38 0x10b8
3042 #define AFE_SECURE_MASK_CONN39 0x10bc
3043 #define AFE_SECURE_MASK_CONN40 0x10c0
3044 #define AFE_SECURE_MASK_CONN41 0x10c4
3045 #define AFE_SECURE_MASK_CONN42 0x10c8
3046 #define AFE_SECURE_MASK_CONN43 0x10cc
3047 #define AFE_SECURE_MASK_CONN44 0x10d0
3048 #define AFE_SECURE_MASK_CONN45 0x10d4
3049 #define AFE_SECURE_MASK_CONN46 0x10d8
3050 #define AFE_SECURE_MASK_CONN47 0x10dc
3051 #define AFE_SECURE_MASK_CONN48 0x10e0
3052 #define AFE_SECURE_MASK_CONN49 0x10e4
3053 #define AFE_SECURE_MASK_CONN50 0x10e8
3054 #define AFE_SECURE_MASK_CONN51 0x10ec
3055 #define AFE_SECURE_MASK_CONN52 0x10f0
3056 #define AFE_SECURE_MASK_CONN53 0x10f4
3057 #define AFE_SECURE_MASK_CONN54 0x10f8
3058 #define AFE_SECURE_MASK_CONN55 0x10fc
3059 #define AFE_SECURE_MASK_CONN56 0x1100
3060 #define AFE_SECURE_MASK_CONN57 0x1104
3061 #define AFE_SECURE_MASK_CONN0_1 0x1108
3062 #define AFE_SECURE_MASK_CONN1_1 0x110c
3063 #define AFE_SECURE_MASK_CONN2_1 0x1110
3064 #define AFE_SECURE_MASK_CONN3_1 0x1114
3065 #define AFE_SECURE_MASK_CONN4_1 0x1118
3066 #define AFE_SECURE_MASK_CONN5_1 0x111c
3067 #define AFE_SECURE_MASK_CONN6_1 0x1120
3068 #define AFE_SECURE_MASK_CONN7_1 0x1124
3069 #define AFE_SECURE_MASK_CONN8_1 0x1128
3070 #define AFE_SECURE_MASK_CONN9_1 0x112c
3071 #define AFE_SECURE_MASK_CONN10_1 0x1130
3072 #define AFE_SECURE_MASK_CONN11_1 0x1134
3073 #define AFE_SECURE_MASK_CONN12_1 0x1138
3074 #define AFE_SECURE_MASK_CONN13_1 0x113c
3075 #define AFE_SECURE_MASK_CONN14_1 0x1140
3076 #define AFE_SECURE_MASK_CONN15_1 0x1144
3077 #define AFE_SECURE_MASK_CONN16_1 0x1148
3078 #define AFE_SECURE_MASK_CONN17_1 0x114c
3079 #define AFE_SECURE_MASK_CONN18_1 0x1150
3080 #define AFE_SECURE_MASK_CONN19_1 0x1154
3081 #define AFE_SECURE_MASK_CONN20_1 0x1158
3082 #define AFE_SECURE_MASK_CONN21_1 0x115c
3083 #define AFE_SECURE_MASK_CONN22_1 0x1160
3084 #define AFE_SECURE_MASK_CONN23_1 0x1164
3085 #define AFE_SECURE_MASK_CONN24_1 0x1168
3086 #define AFE_SECURE_MASK_CONN25_1 0x116c
3087 #define AFE_SECURE_MASK_CONN26_1 0x1170
3088 #define AFE_SECURE_MASK_CONN27_1 0x1174
3089 #define AFE_SECURE_MASK_CONN28_1 0x1178
3090 #define AFE_SECURE_MASK_CONN29_1 0x117c
3091 #define AFE_SECURE_MASK_CONN30_1 0x1180
3092 #define AFE_SECURE_MASK_CONN31_1 0x1184
3093 #define AFE_SECURE_MASK_CONN32_1 0x1188
3094 #define AFE_SECURE_MASK_CONN33_1 0x118c
3095 #define AFE_SECURE_MASK_CONN34_1 0x1190
3096 #define AFE_SECURE_MASK_CONN35_1 0x1194
3097 #define AFE_SECURE_MASK_CONN36_1 0x1198
3098 #define AFE_SECURE_MASK_CONN37_1 0x119c
3099 #define AFE_SECURE_MASK_CONN38_1 0x11a0
3100 #define AFE_SECURE_MASK_CONN39_1 0x11a4
3101 #define AFE_SECURE_MASK_CONN40_1 0x11a8
3102 #define AFE_SECURE_MASK_CONN41_1 0x11ac
3103 #define AFE_SECURE_MASK_CONN42_1 0x11b0
3104 #define AFE_SECURE_MASK_CONN43_1 0x11b4
3105 #define AFE_SECURE_MASK_CONN44_1 0x11b8
3106 #define AFE_SECURE_MASK_CONN45_1 0x11bc
3107 #define AFE_SECURE_MASK_CONN46_1 0x11c0
3108 #define AFE_SECURE_MASK_CONN47_1 0x11c4
3109 #define AFE_SECURE_MASK_CONN48_1 0x11c8
3110 #define AFE_SECURE_MASK_CONN49_1 0x11cc
3111 #define AFE_SECURE_MASK_CONN50_1 0x11d0
3112 #define AFE_SECURE_MASK_CONN51_1 0x11d4
3113 #define AFE_SECURE_MASK_CONN52_1 0x11d8
3114 #define AFE_SECURE_MASK_CONN53_1 0x11dc
3115 #define AFE_SECURE_MASK_CONN54_1 0x11e0
3116 #define AFE_SECURE_MASK_CONN55_1 0x11e4
3117 #define AFE_SECURE_MASK_CONN56_1 0x11e8
3118 #define AFE_SECURE_MASK_TINY_CONN0 0x1200
3119 #define AFE_SECURE_MASK_TINY_CONN1 0x1204
3120 #define AFE_SECURE_MASK_TINY_CONN2 0x1208
3121 #define AFE_SECURE_MASK_TINY_CONN3 0x120c
3122 #define AFE_SECURE_MASK_TINY_CONN4 0x1210
3123 #define AFE_SECURE_MASK_TINY_CONN5 0x1214
3124 #define AFE_SECURE_MASK_TINY_CONN6 0x1218
3125 #define AFE_SECURE_MASK_TINY_CONN7 0x121c
3126
3127 #define AFE_MAX_REGISTER AFE_SECURE_MASK_TINY_CONN7
3128
3129 #define AFE_IRQ_STATUS_BITS 0x87FFFFFF
3130 #define AFE_IRQ_CNT_SHIFT 0
3131 #define AFE_IRQ_CNT_MASK 0x3ffff
3132
3133 #endif
3134
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