1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek 8365 AFE clock control
4 *
5 * Copyright (c) 2024 MediaTek Inc.
6 * Authors: Jia Zeng <jia.zeng@mediatek.com>
7 * Alexandre Mergnat <amergnat@baylibre.com>
8 */
9
10 #include "mt8365-afe-clk.h"
11 #include "mt8365-afe-common.h"
12 #include "mt8365-reg.h"
13 #include "../common/mtk-base-afe.h"
14 #include <linux/device.h>
15 #include <linux/mfd/syscon.h>
16
17 static const char *aud_clks[MT8365_CLK_NUM] = {
18 [MT8365_CLK_TOP_AUD_SEL] = "top_audio_sel",
19 [MT8365_CLK_AUD_I2S0_M] = "audio_i2s0_m",
20 [MT8365_CLK_AUD_I2S1_M] = "audio_i2s1_m",
21 [MT8365_CLK_AUD_I2S2_M] = "audio_i2s2_m",
22 [MT8365_CLK_AUD_I2S3_M] = "audio_i2s3_m",
23 [MT8365_CLK_ENGEN1] = "engen1",
24 [MT8365_CLK_ENGEN2] = "engen2",
25 [MT8365_CLK_AUD1] = "aud1",
26 [MT8365_CLK_AUD2] = "aud2",
27 [MT8365_CLK_I2S0_M_SEL] = "i2s0_m_sel",
28 [MT8365_CLK_I2S1_M_SEL] = "i2s1_m_sel",
29 [MT8365_CLK_I2S2_M_SEL] = "i2s2_m_sel",
30 [MT8365_CLK_I2S3_M_SEL] = "i2s3_m_sel",
31 [MT8365_CLK_CLK26M] = "top_clk26m_clk",
32 };
33
34 int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe)
35 {
36 size_t i;
37 struct mt8365_afe_private *afe_priv = afe->platform_priv;
38
39 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
40 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
41 if (IS_ERR(afe_priv->clocks[i])) {
42 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
43 __func__, aud_clks[i]);
44 return PTR_ERR(afe_priv->clocks[i]);
45 }
46 }
47 return 0;
48 }
49
50 void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
51 {
52 if (clk)
53 clk_disable_unprepare(clk);
54 }
55
56 int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
57 unsigned int rate)
58 {
59 int ret;
60
61 if (clk) {
62 ret = clk_set_rate(clk, rate);
63 if (ret) {
64 dev_err(afe->dev, "Failed to set rate\n");
65 return ret;
66 }
67 }
68 return 0;
69 }
70
71 int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
72 struct clk *parent)
73 {
74 int ret;
75
76 if (clk && parent) {
77 ret = clk_set_parent(clk, parent);
78 if (ret) {
79 dev_err(afe->dev, "Failed to set parent\n");
80 return ret;
81 }
82 }
83 return 0;
84 }
85
86 static unsigned int get_top_cg_reg(unsigned int cg_type)
87 {
88 switch (cg_type) {
89 case MT8365_TOP_CG_AFE:
90 case MT8365_TOP_CG_I2S_IN:
91 case MT8365_TOP_CG_22M:
92 case MT8365_TOP_CG_24M:
93 case MT8365_TOP_CG_INTDIR_CK:
94 case MT8365_TOP_CG_APLL2_TUNER:
95 case MT8365_TOP_CG_APLL_TUNER:
96 case MT8365_TOP_CG_SPDIF:
97 case MT8365_TOP_CG_TDM_OUT:
98 case MT8365_TOP_CG_TDM_IN:
99 case MT8365_TOP_CG_ADC:
100 case MT8365_TOP_CG_DAC:
101 case MT8365_TOP_CG_DAC_PREDIS:
102 case MT8365_TOP_CG_TML:
103 return AUDIO_TOP_CON0;
104 case MT8365_TOP_CG_I2S1_BCLK:
105 case MT8365_TOP_CG_I2S2_BCLK:
106 case MT8365_TOP_CG_I2S3_BCLK:
107 case MT8365_TOP_CG_I2S4_BCLK:
108 case MT8365_TOP_CG_DMIC0_ADC:
109 case MT8365_TOP_CG_DMIC1_ADC:
110 case MT8365_TOP_CG_DMIC2_ADC:
111 case MT8365_TOP_CG_DMIC3_ADC:
112 case MT8365_TOP_CG_CONNSYS_I2S_ASRC:
113 case MT8365_TOP_CG_GENERAL1_ASRC:
114 case MT8365_TOP_CG_GENERAL2_ASRC:
115 case MT8365_TOP_CG_TDM_ASRC:
116 return AUDIO_TOP_CON1;
117 default:
118 return 0;
119 }
120 }
121
122 static unsigned int get_top_cg_mask(unsigned int cg_type)
123 {
124 switch (cg_type) {
125 case MT8365_TOP_CG_AFE:
126 return AUD_TCON0_PDN_AFE;
127 case MT8365_TOP_CG_I2S_IN:
128 return AUD_TCON0_PDN_I2S_IN;
129 case MT8365_TOP_CG_22M:
130 return AUD_TCON0_PDN_22M;
131 case MT8365_TOP_CG_24M:
132 return AUD_TCON0_PDN_24M;
133 case MT8365_TOP_CG_INTDIR_CK:
134 return AUD_TCON0_PDN_INTDIR;
135 case MT8365_TOP_CG_APLL2_TUNER:
136 return AUD_TCON0_PDN_APLL2_TUNER;
137 case MT8365_TOP_CG_APLL_TUNER:
138 return AUD_TCON0_PDN_APLL_TUNER;
139 case MT8365_TOP_CG_SPDIF:
140 return AUD_TCON0_PDN_SPDIF;
141 case MT8365_TOP_CG_TDM_OUT:
142 return AUD_TCON0_PDN_TDM_OUT;
143 case MT8365_TOP_CG_TDM_IN:
144 return AUD_TCON0_PDN_TDM_IN;
145 case MT8365_TOP_CG_ADC:
146 return AUD_TCON0_PDN_ADC;
147 case MT8365_TOP_CG_DAC:
148 return AUD_TCON0_PDN_DAC;
149 case MT8365_TOP_CG_DAC_PREDIS:
150 return AUD_TCON0_PDN_DAC_PREDIS;
151 case MT8365_TOP_CG_TML:
152 return AUD_TCON0_PDN_TML;
153 case MT8365_TOP_CG_I2S1_BCLK:
154 return AUD_TCON1_PDN_I2S1_BCLK;
155 case MT8365_TOP_CG_I2S2_BCLK:
156 return AUD_TCON1_PDN_I2S2_BCLK;
157 case MT8365_TOP_CG_I2S3_BCLK:
158 return AUD_TCON1_PDN_I2S3_BCLK;
159 case MT8365_TOP_CG_I2S4_BCLK:
160 return AUD_TCON1_PDN_I2S4_BCLK;
161 case MT8365_TOP_CG_DMIC0_ADC:
162 return AUD_TCON1_PDN_DMIC0_ADC;
163 case MT8365_TOP_CG_DMIC1_ADC:
164 return AUD_TCON1_PDN_DMIC1_ADC;
165 case MT8365_TOP_CG_DMIC2_ADC:
166 return AUD_TCON1_PDN_DMIC2_ADC;
167 case MT8365_TOP_CG_DMIC3_ADC:
168 return AUD_TCON1_PDN_DMIC3_ADC;
169 case MT8365_TOP_CG_CONNSYS_I2S_ASRC:
170 return AUD_TCON1_PDN_CONNSYS_I2S_ASRC;
171 case MT8365_TOP_CG_GENERAL1_ASRC:
172 return AUD_TCON1_PDN_GENERAL1_ASRC;
173 case MT8365_TOP_CG_GENERAL2_ASRC:
174 return AUD_TCON1_PDN_GENERAL2_ASRC;
175 case MT8365_TOP_CG_TDM_ASRC:
176 return AUD_TCON1_PDN_TDM_ASRC;
177 default:
178 return 0;
179 }
180 }
181
182 static unsigned int get_top_cg_on_val(unsigned int cg_type)
183 {
184 return 0;
185 }
186
187 static unsigned int get_top_cg_off_val(unsigned int cg_type)
188 {
189 return get_top_cg_mask(cg_type);
190 }
191
192 int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
193 {
194 struct mt8365_afe_private *afe_priv = afe->platform_priv;
195 unsigned int reg = get_top_cg_reg(cg_type);
196 unsigned int mask = get_top_cg_mask(cg_type);
197 unsigned int val = get_top_cg_on_val(cg_type);
198 unsigned long flags;
199
200 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
201
202 afe_priv->top_cg_ref_cnt[cg_type]++;
203 if (afe_priv->top_cg_ref_cnt[cg_type] == 1)
204 regmap_update_bits(afe->regmap, reg, mask, val);
205
206 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
207
208 return 0;
209 }
210
211 int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
212 {
213 struct mt8365_afe_private *afe_priv = afe->platform_priv;
214 unsigned int reg = get_top_cg_reg(cg_type);
215 unsigned int mask = get_top_cg_mask(cg_type);
216 unsigned int val = get_top_cg_off_val(cg_type);
217 unsigned long flags;
218
219 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
220
221 afe_priv->top_cg_ref_cnt[cg_type]--;
222 if (afe_priv->top_cg_ref_cnt[cg_type] == 0)
223 regmap_update_bits(afe->regmap, reg, mask, val);
224 else if (afe_priv->top_cg_ref_cnt[cg_type] < 0)
225 afe_priv->top_cg_ref_cnt[cg_type] = 0;
226
227 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
228
229 return 0;
230 }
231
232 int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe)
233 {
234 struct mt8365_afe_private *afe_priv = afe->platform_priv;
235
236 clk_prepare_enable(afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
237 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);
238 mt8365_afe_enable_afe_on(afe);
239
240 return 0;
241 }
242
243 int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe)
244 {
245 struct mt8365_afe_private *afe_priv = afe->platform_priv;
246
247 mt8365_afe_disable_afe_on(afe);
248 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);
249 mt8365_afe_disable_clk(afe, afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
250
251 return 0;
252 }
253
254 int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe)
255 {
256 return 0;
257 }
258
259 int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe)
260 {
261 return 0;
262 }
263
264 int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe)
265 {
266 struct mt8365_afe_private *afe_priv = afe->platform_priv;
267 unsigned long flags;
268
269 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
270
271 afe_priv->afe_on_ref_cnt++;
272 if (afe_priv->afe_on_ref_cnt == 1)
273 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
274
275 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
276
277 return 0;
278 }
279
280 int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)
281 {
282 struct mt8365_afe_private *afe_priv = afe->platform_priv;
283 unsigned long flags;
284
285 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
286
287 afe_priv->afe_on_ref_cnt--;
288 if (afe_priv->afe_on_ref_cnt == 0)
289 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
290 else if (afe_priv->afe_on_ref_cnt < 0)
291 afe_priv->afe_on_ref_cnt = 0;
292
293 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
294
295 return 0;
296 }
297
298 static int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
299 {
300 if (apll1)
301 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
302 AFE_22M_PLL_EN, AFE_22M_PLL_EN);
303 else
304 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
305 AFE_24M_PLL_EN, AFE_24M_PLL_EN);
306
307 return 0;
308 }
309
310 static int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
311 {
312 if (apll1)
313 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
314 AFE_22M_PLL_EN, ~AFE_22M_PLL_EN);
315 else
316 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
317 AFE_24M_PLL_EN, ~AFE_24M_PLL_EN);
318
319 return 0;
320 }
321
322 int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
323 {
324 struct mt8365_afe_private *afe_priv = afe->platform_priv;
325
326 mutex_lock(&afe_priv->afe_clk_mutex);
327
328 afe_priv->apll_tuner_ref_cnt[apll]++;
329 if (afe_priv->apll_tuner_ref_cnt[apll] != 1) {
330 mutex_unlock(&afe_priv->afe_clk_mutex);
331 return 0;
332 }
333
334 if (apll == MT8365_AFE_APLL1) {
335 regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
336 AFE_APLL_TUNER_CFG_MASK, 0x432);
337 regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
338 AFE_APLL_TUNER_CFG_EN_MASK, 0x1);
339 } else {
340 regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
341 AFE_APLL_TUNER_CFG1_MASK, 0x434);
342 regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
343 AFE_APLL_TUNER_CFG1_EN_MASK, 0x1);
344 }
345
346 mutex_unlock(&afe_priv->afe_clk_mutex);
347 return 0;
348 }
349
350 int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
351 {
352 struct mt8365_afe_private *afe_priv = afe->platform_priv;
353
354 mutex_lock(&afe_priv->afe_clk_mutex);
355
356 afe_priv->apll_tuner_ref_cnt[apll]--;
357 if (afe_priv->apll_tuner_ref_cnt[apll] == 0) {
358 if (apll == MT8365_AFE_APLL1)
359 regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
360 AFE_APLL_TUNER_CFG_EN_MASK, 0x0);
361 else
362 regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
363 AFE_APLL_TUNER_CFG1_EN_MASK, 0x0);
364
365 } else if (afe_priv->apll_tuner_ref_cnt[apll] < 0) {
366 afe_priv->apll_tuner_ref_cnt[apll] = 0;
367 }
368
369 mutex_unlock(&afe_priv->afe_clk_mutex);
370 return 0;
371 }
372
373 int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
374 {
375 struct mt8365_afe_private *afe_priv = afe->platform_priv;
376
377 if (apll == MT8365_AFE_APLL1) {
378 if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN1])) {
379 dev_info(afe->dev, "%s Failed to enable ENGEN1 clk\n",
380 __func__);
381 return 0;
382 }
383 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_22M);
384 mt8365_afe_hd_engen_enable(afe, true);
385 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
386 mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
387 } else {
388 if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN2])) {
389 dev_info(afe->dev, "%s Failed to enable ENGEN2 clk\n",
390 __func__);
391 return 0;
392 }
393 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_24M);
394 mt8365_afe_hd_engen_enable(afe, false);
395 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
396 mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
397 }
398
399 return 0;
400 }
401
402 int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
403 {
404 struct mt8365_afe_private *afe_priv = afe->platform_priv;
405
406 if (apll == MT8365_AFE_APLL1) {
407 mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
408 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
409 mt8365_afe_hd_engen_disable(afe, true);
410 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_22M);
411 clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN1]);
412 } else {
413 mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
414 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
415 mt8365_afe_hd_engen_disable(afe, false);
416 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_24M);
417 clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN2]);
418 }
419
420 return 0;
421 }
422
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.