1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
4 *
5 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
6 * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
7 *
8 */
9
10 #ifndef _ROCKCHIP_I2S_TDM_H
11 #define _ROCKCHIP_I2S_TDM_H
12
13 /*
14 * TXCR
15 * transmit operation control register
16 */
17 #define I2S_TXCR_PATH_SHIFT(x) (23 + (x) * 2)
18 #define I2S_TXCR_PATH_MASK(x) (0x3 << I2S_TXCR_PATH_SHIFT(x))
19 #define I2S_TXCR_PATH(x, v) ((v) << I2S_TXCR_PATH_SHIFT(x))
20 #define I2S_TXCR_RCNT_SHIFT 17
21 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
22 #define I2S_TXCR_CSR_SHIFT 15
23 #define I2S_TXCR_CSR(x) ((x) << I2S_TXCR_CSR_SHIFT)
24 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
25 #define I2S_TXCR_HWT BIT(14)
26 #define I2S_TXCR_SJM_SHIFT 12
27 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
28 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
29 #define I2S_TXCR_FBM_SHIFT 11
30 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
31 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
32 #define I2S_TXCR_IBM_SHIFT 9
33 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
34 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
35 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
36 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
37 #define I2S_TXCR_PBM_SHIFT 7
38 #define I2S_TXCR_PBM_MODE(x) ((x) << I2S_TXCR_PBM_SHIFT)
39 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
40 #define I2S_TXCR_TFS_SHIFT 5
41 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
42 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
43 #define I2S_TXCR_TFS_TDM_PCM (2 << I2S_TXCR_TFS_SHIFT)
44 #define I2S_TXCR_TFS_TDM_I2S (3 << I2S_TXCR_TFS_SHIFT)
45 #define I2S_TXCR_TFS_MASK (3 << I2S_TXCR_TFS_SHIFT)
46 #define I2S_TXCR_VDW_SHIFT 0
47 #define I2S_TXCR_VDW(x) (((x) - 1) << I2S_TXCR_VDW_SHIFT)
48 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
49
50 /*
51 * RXCR
52 * receive operation control register
53 */
54 #define I2S_RXCR_PATH_SHIFT(x) (17 + (x) * 2)
55 #define I2S_RXCR_PATH_MASK(x) (0x3 << I2S_RXCR_PATH_SHIFT(x))
56 #define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x))
57 #define I2S_RXCR_CSR_SHIFT 15
58 #define I2S_RXCR_CSR(x) ((x) << I2S_RXCR_CSR_SHIFT)
59 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
60 #define I2S_RXCR_HWT BIT(14)
61 #define I2S_RXCR_SJM_SHIFT 12
62 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
63 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
64 #define I2S_RXCR_FBM_SHIFT 11
65 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
66 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
67 #define I2S_RXCR_IBM_SHIFT 9
68 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
69 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
70 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
71 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
72 #define I2S_RXCR_PBM_SHIFT 7
73 #define I2S_RXCR_PBM_MODE(x) ((x) << I2S_RXCR_PBM_SHIFT)
74 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
75 #define I2S_RXCR_TFS_SHIFT 5
76 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
77 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
78 #define I2S_RXCR_TFS_TDM_PCM (2 << I2S_RXCR_TFS_SHIFT)
79 #define I2S_RXCR_TFS_TDM_I2S (3 << I2S_RXCR_TFS_SHIFT)
80 #define I2S_RXCR_TFS_MASK (3 << I2S_RXCR_TFS_SHIFT)
81 #define I2S_RXCR_VDW_SHIFT 0
82 #define I2S_RXCR_VDW(x) (((x) - 1) << I2S_RXCR_VDW_SHIFT)
83 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
84
85 /*
86 * CKR
87 * clock generation register
88 */
89 #define I2S_CKR_TRCM_SHIFT 28
90 #define I2S_CKR_TRCM(x) ((x) << I2S_CKR_TRCM_SHIFT)
91 #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT)
92 #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT)
93 #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT)
94 #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT)
95 #define I2S_CKR_MSS_SHIFT 27
96 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
97 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
98 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
99 #define I2S_CKR_CKP_SHIFT 26
100 #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT)
101 #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT)
102 #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
103 #define I2S_CKR_RLP_SHIFT 25
104 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
105 #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT)
106 #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT)
107 #define I2S_CKR_TLP_SHIFT 24
108 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
109 #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT)
110 #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT)
111 #define I2S_CKR_MDIV_SHIFT 16
112 #define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT)
113 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
114 #define I2S_CKR_RSD_SHIFT 8
115 #define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT)
116 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
117 #define I2S_CKR_TSD_SHIFT 0
118 #define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT)
119 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
120
121 /*
122 * FIFOLR
123 * FIFO level register
124 */
125 #define I2S_FIFOLR_RFL_SHIFT 24
126 #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
127 #define I2S_FIFOLR_TFL3_SHIFT 18
128 #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
129 #define I2S_FIFOLR_TFL2_SHIFT 12
130 #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
131 #define I2S_FIFOLR_TFL1_SHIFT 6
132 #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
133 #define I2S_FIFOLR_TFL0_SHIFT 0
134 #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
135
136 /*
137 * DMACR
138 * DMA control register
139 */
140 #define I2S_DMACR_RDE_SHIFT 24
141 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
142 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
143 #define I2S_DMACR_RDL_SHIFT 16
144 #define I2S_DMACR_RDL(x) (((x) - 1) << I2S_DMACR_RDL_SHIFT)
145 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
146 #define I2S_DMACR_TDE_SHIFT 8
147 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
148 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
149 #define I2S_DMACR_TDL_SHIFT 0
150 #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
151 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
152
153 /*
154 * INTCR
155 * interrupt control register
156 */
157 #define I2S_INTCR_RFT_SHIFT 20
158 #define I2S_INTCR_RFT(x) (((x) - 1) << I2S_INTCR_RFT_SHIFT)
159 #define I2S_INTCR_RXOIC BIT(18)
160 #define I2S_INTCR_RXOIE_SHIFT 17
161 #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
162 #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
163 #define I2S_INTCR_RXFIE_SHIFT 16
164 #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
165 #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
166 #define I2S_INTCR_TFT_SHIFT 4
167 #define I2S_INTCR_TFT(x) (((x) - 1) << I2S_INTCR_TFT_SHIFT)
168 #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
169 #define I2S_INTCR_TXUIC BIT(2)
170 #define I2S_INTCR_TXUIE_SHIFT 1
171 #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
172 #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
173
174 /*
175 * INTSR
176 * interrupt status register
177 */
178 #define I2S_INTSR_TXEIE_SHIFT 0
179 #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
180 #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
181 #define I2S_INTSR_RXOI_SHIFT 17
182 #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
183 #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
184 #define I2S_INTSR_RXFI_SHIFT 16
185 #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
186 #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
187 #define I2S_INTSR_TXUI_SHIFT 1
188 #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
189 #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
190 #define I2S_INTSR_TXEI_SHIFT 0
191 #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
192 #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
193
194 /*
195 * XFER
196 * Transfer start register
197 */
198 #define I2S_XFER_RXS_SHIFT 1
199 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
200 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
201 #define I2S_XFER_TXS_SHIFT 0
202 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
203 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
204
205 /*
206 * CLR
207 * clear SCLK domain logic register
208 */
209 #define I2S_CLR_RXC BIT(1)
210 #define I2S_CLR_TXC BIT(0)
211
212 /*
213 * TXDR
214 * Transimt FIFO data register, write only.
215 */
216 #define I2S_TXDR_MASK (0xff)
217
218 /*
219 * RXDR
220 * Receive FIFO data register, write only.
221 */
222 #define I2S_RXDR_MASK (0xff)
223
224 /*
225 * TDM_CTRL
226 * TDM ctrl register
227 */
228 #define TDM_FSYNC_WIDTH_SEL1_MSK GENMASK(20, 18)
229 #define TDM_FSYNC_WIDTH_SEL1(x) (((x) - 1) << 18)
230 #define TDM_FSYNC_WIDTH_SEL0_MSK BIT(17)
231 #define TDM_FSYNC_WIDTH_HALF_FRAME 0
232 #define TDM_FSYNC_WIDTH_ONE_FRAME BIT(17)
233 #define TDM_SHIFT_CTRL_MSK GENMASK(16, 14)
234 #define TDM_SHIFT_CTRL(x) ((x) << 14)
235 #define TDM_SLOT_BIT_WIDTH_MSK GENMASK(13, 9)
236 #define TDM_SLOT_BIT_WIDTH(x) (((x) - 1) << 9)
237 #define TDM_FRAME_WIDTH_MSK GENMASK(8, 0)
238 #define TDM_FRAME_WIDTH(x) (((x) - 1) << 0)
239
240 /*
241 * CLKDIV
242 * Mclk div register
243 */
244 #define I2S_CLKDIV_TXM_SHIFT 0
245 #define I2S_CLKDIV_TXM(x) (((x) - 1) << I2S_CLKDIV_TXM_SHIFT)
246 #define I2S_CLKDIV_TXM_MASK (0xff << I2S_CLKDIV_TXM_SHIFT)
247 #define I2S_CLKDIV_RXM_SHIFT 8
248 #define I2S_CLKDIV_RXM(x) (((x) - 1) << I2S_CLKDIV_RXM_SHIFT)
249 #define I2S_CLKDIV_RXM_MASK (0xff << I2S_CLKDIV_RXM_SHIFT)
250
251 /* Clock divider id */
252 enum {
253 ROCKCHIP_DIV_MCLK = 0,
254 ROCKCHIP_DIV_BCLK,
255 };
256
257 /* channel select */
258 #define I2S_CSR_SHIFT 15
259 #define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
260 #define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
261 #define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
262 #define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
263
264 /* io direction cfg register */
265 #define I2S_IO_DIRECTION_MASK (7)
266 #define I2S_IO_8CH_OUT_2CH_IN (7)
267 #define I2S_IO_6CH_OUT_4CH_IN (3)
268 #define I2S_IO_4CH_OUT_6CH_IN (1)
269 #define I2S_IO_2CH_OUT_8CH_IN (0)
270
271 /* I2S REGS */
272 #define I2S_TXCR (0x0000)
273 #define I2S_RXCR (0x0004)
274 #define I2S_CKR (0x0008)
275 #define I2S_TXFIFOLR (0x000c)
276 #define I2S_DMACR (0x0010)
277 #define I2S_INTCR (0x0014)
278 #define I2S_INTSR (0x0018)
279 #define I2S_XFER (0x001c)
280 #define I2S_CLR (0x0020)
281 #define I2S_TXDR (0x0024)
282 #define I2S_RXDR (0x0028)
283 #define I2S_RXFIFOLR (0x002c)
284 #define I2S_TDM_TXCR (0x0030)
285 #define I2S_TDM_RXCR (0x0034)
286 #define I2S_CLKDIV (0x0038)
287
288 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
289
290 /* PX30 GRF CONFIGS */
291 #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)
292 #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)
293 #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
294 #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
295
296 #define PX30_I2S0_CLK_TXONLY \
297 (PX30_I2S0_MCLK_OUT_SRC_FROM_TX | PX30_I2S0_CLK_IN_SRC_FROM_TX)
298
299 #define PX30_I2S0_CLK_RXONLY \
300 (PX30_I2S0_MCLK_OUT_SRC_FROM_RX | PX30_I2S0_CLK_IN_SRC_FROM_RX)
301
302 /* RK1808 GRF CONFIGS */
303 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
304 #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
305 #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)
306 #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)
307
308 #define RK1808_I2S0_CLK_TXONLY \
309 (RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | RK1808_I2S0_CLK_IN_SRC_FROM_TX)
310
311 #define RK1808_I2S0_CLK_RXONLY \
312 (RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | RK1808_I2S0_CLK_IN_SRC_FROM_RX)
313
314 /* RK3308 GRF CONFIGS */
315 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10)
316 #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 10, 10)
317 #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 9, 9)
318 #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 9, 9)
319 #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 8, 8)
320 #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 8, 8)
321 #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
322 #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
323 #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 1, 1)
324 #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 1, 1)
325 #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 0, 0)
326 #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 0, 0)
327
328 #define RK3308_I2S0_CLK_TXONLY \
329 (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX | \
330 RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX | \
331 RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX)
332
333 #define RK3308_I2S0_CLK_RXONLY \
334 (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX | \
335 RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX | \
336 RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX)
337
338 #define RK3308_I2S1_CLK_TXONLY \
339 (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX | \
340 RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX | \
341 RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX)
342
343 #define RK3308_I2S1_CLK_RXONLY \
344 (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX | \
345 RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX | \
346 RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX)
347
348 /* RK3568 GRF CONFIGS */
349 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
350 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
351
352 #define RK3568_I2S1_CLK_TXONLY \
353 RK3568_I2S1_MCLK_OUT_SRC_FROM_TX
354
355 #define RK3568_I2S1_CLK_RXONLY \
356 RK3568_I2S1_MCLK_OUT_SRC_FROM_RX
357
358 #define RK3568_I2S3_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 15, 15)
359 #define RK3568_I2S3_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 15, 15)
360 #define RK3568_I2S3_SCLK_SRC_FROM_TX HIWORD_UPDATE(1, 7, 7)
361 #define RK3568_I2S3_SCLK_SRC_FROM_RX HIWORD_UPDATE(0, 7, 7)
362 #define RK3568_I2S3_LRCK_SRC_FROM_TX HIWORD_UPDATE(1, 6, 6)
363 #define RK3568_I2S3_LRCK_SRC_FROM_RX HIWORD_UPDATE(0, 6, 6)
364
365 #define RK3568_I2S3_MCLK_TXONLY \
366 RK3568_I2S3_MCLK_OUT_SRC_FROM_TX
367
368 #define RK3568_I2S3_CLK_TXONLY \
369 (RK3568_I2S3_SCLK_SRC_FROM_TX | \
370 RK3568_I2S3_LRCK_SRC_FROM_TX)
371
372 #define RK3568_I2S3_MCLK_RXONLY \
373 RK3568_I2S3_MCLK_OUT_SRC_FROM_RX
374
375 #define RK3568_I2S3_CLK_RXONLY \
376 (RK3568_I2S3_SCLK_SRC_FROM_RX | \
377 RK3568_I2S3_LRCK_SRC_FROM_RX)
378
379 #define RK3568_I2S3_MCLK_IE HIWORD_UPDATE(0, 3, 3)
380 #define RK3568_I2S3_MCLK_OE HIWORD_UPDATE(1, 3, 3)
381 #define RK3568_I2S2_MCLK_IE HIWORD_UPDATE(0, 2, 2)
382 #define RK3568_I2S2_MCLK_OE HIWORD_UPDATE(1, 2, 2)
383 #define RK3568_I2S1_MCLK_TX_IE HIWORD_UPDATE(0, 1, 1)
384 #define RK3568_I2S1_MCLK_TX_OE HIWORD_UPDATE(1, 1, 1)
385 #define RK3568_I2S1_MCLK_RX_IE HIWORD_UPDATE(0, 0, 0)
386 #define RK3568_I2S1_MCLK_RX_OE HIWORD_UPDATE(1, 0, 0)
387
388 /* RV1126 GRF CONFIGS */
389 #define RV1126_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 9, 9)
390 #define RV1126_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 9, 9)
391
392 #define RV1126_I2S0_CLK_TXONLY \
393 RV1126_I2S0_MCLK_OUT_SRC_FROM_TX
394
395 #define RV1126_I2S0_CLK_RXONLY \
396 RV1126_I2S0_MCLK_OUT_SRC_FROM_RX
397
398 #endif /* _ROCKCHIP_I2S_TDM_H */
399
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