1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2022 Intel Corporation
4 //
5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
6 //
7
8 /*
9 * Hardware interface for audio DSP on Meteorlake.
10 */
11
12 #include <linux/debugfs.h>
13 #include <linux/firmware.h>
14 #include <sound/sof/ipc4/header.h>
15 #include <trace/events/sof_intel.h>
16 #include "../ipc4-priv.h"
17 #include "../ops.h"
18 #include "hda.h"
19 #include "hda-ipc.h"
20 #include "../sof-audio.h"
21 #include "mtl.h"
22 #include "telemetry.h"
23
24 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = {
25 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
26 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
27 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
29 };
30
31 static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
32 {
33 /*
34 * clear busy interrupt to tell dsp controller this interrupt has been accepted,
35 * not trigger it again
36 */
37 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,
38 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY);
39 /*
40 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp
41 */
42 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,
43 MTL_DSP_REG_HFIPCXTDA_BUSY, 0);
44 }
45
46 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
47 {
48 /*
49 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it,
50 * don't send more reply to host
51 */
52 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,
53 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE);
54
55 /* unmask Done interrupt */
56 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
57 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE);
58 }
59
60 /* Check if an IPC IRQ occurred */
61 bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
62 {
63 u32 irq_status;
64 u32 hfintipptr;
65
66 if (sdev->dspless_mode_selected)
67 return false;
68
69 /* read Interrupt IP Pointer */
70 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
71 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
72
73 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
74
75 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC))
76 return true;
77
78 return false;
79 }
80 EXPORT_SYMBOL_NS(mtl_dsp_check_ipc_irq, SND_SOC_SOF_INTEL_MTL);
81
82 /* Check if an SDW IRQ occurred */
83 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
84 {
85 u32 irq_status;
86 u32 hfintipptr;
87
88 /* read Interrupt IP Pointer */
89 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
90 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
91
92 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW))
93 return true;
94
95 return false;
96 }
97
98 int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
99 {
100 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
101 struct sof_ipc4_msg *msg_data = msg->msg_data;
102
103 if (hda_ipc4_tx_is_busy(sdev)) {
104 hdev->delayed_ipc_tx_msg = msg;
105 return 0;
106 }
107
108 hdev->delayed_ipc_tx_msg = NULL;
109
110 /* send the message via mailbox */
111 if (msg_data->data_size)
112 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
113 msg_data->data_size);
114
115 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,
116 msg_data->extension);
117 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,
118 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY);
119
120 hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
121
122 return 0;
123 }
124 EXPORT_SYMBOL_NS(mtl_ipc_send_msg, SND_SOC_SOF_INTEL_MTL);
125
126 void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
127 {
128 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
129 const struct sof_intel_dsp_desc *chip = hda->desc;
130
131 if (sdev->dspless_mode_selected)
132 return;
133
134 /* enable IPC DONE and BUSY interrupts */
135 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
136 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE,
137 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE);
138 }
139
140 void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
141 {
142 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
143 const struct sof_intel_dsp_desc *chip = hda->desc;
144
145 if (sdev->dspless_mode_selected)
146 return;
147
148 /* disable IPC DONE and BUSY interrupts */
149 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
150 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);
151 }
152 EXPORT_SYMBOL_NS(mtl_disable_ipc_interrupts, SND_SOC_SOF_INTEL_MTL);
153
154 static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
155 {
156 u32 hipcie;
157 u32 mask;
158 u32 val;
159 int ret;
160
161 if (sdev->dspless_mode_selected)
162 return;
163
164 /* Enable/Disable SoundWire interrupt */
165 mask = MTL_DSP_REG_HfSNDWIE_IE_MASK;
166 if (enable)
167 val = mask;
168 else
169 val = 0;
170
171 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val);
172
173 /* check if operation was successful */
174 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
175 (hipcie & mask) == val,
176 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
177 if (ret < 0)
178 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n",
179 enable ? "enable" : "disable");
180 }
181
182 int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
183 {
184 u32 hfintipptr;
185 u32 irqinten;
186 u32 hipcie;
187 u32 mask;
188 u32 val;
189 int ret;
190
191 if (sdev->dspless_mode_selected)
192 return 0;
193
194 /* read Interrupt IP Pointer */
195 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
196
197 /* Enable/Disable Host IPC and SOUNDWIRE */
198 mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
199 if (enable)
200 val = mask;
201 else
202 val = 0;
203
204 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val);
205
206 /* check if operation was successful */
207 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
208 (irqinten & mask) == val,
209 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
210 if (ret < 0) {
211 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n",
212 enable ? "enable" : "disable");
213 return ret;
214 }
215
216 /* Enable/Disable Host IPC interrupt*/
217 mask = MTL_DSP_REG_HfHIPCIE_IE_MASK;
218 if (enable)
219 val = mask;
220 else
221 val = 0;
222
223 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val);
224
225 /* check if operation was successful */
226 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
227 (hipcie & mask) == val,
228 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
229 if (ret < 0) {
230 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n",
231 enable ? "enable" : "disable");
232 return ret;
233 }
234
235 return ret;
236 }
237 EXPORT_SYMBOL_NS(mtl_enable_interrupts, SND_SOC_SOF_INTEL_MTL);
238
239 /* pre fw run operations */
240 int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
241 {
242 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
243 u32 dsphfpwrsts;
244 u32 dsphfdsscs;
245 u32 cpa;
246 u32 pgs;
247 int ret;
248
249 /* Set the DSP subsystem power on */
250 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
251 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK);
252
253 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
254 usleep_range(1000, 1010);
255
256 /* poll with timeout to check if operation successful */
257 cpa = MTL_HFDSSCS_CPA_MASK;
258 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
259 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
260 HDA_DSP_RESET_TIMEOUT_US);
261 if (ret < 0) {
262 dev_err(sdev->dev, "failed to enable DSP subsystem\n");
263 return ret;
264 }
265
266 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
267 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
268 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
269
270 usleep_range(1000, 1010);
271
272 /* poll with timeout to check if operation successful */
273 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
274 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
275 (dsphfpwrsts & pgs) == pgs,
276 HDA_DSP_REG_POLL_INTERVAL_US,
277 HDA_DSP_RESET_TIMEOUT_US);
278 if (ret < 0)
279 dev_err(sdev->dev, "failed to power up gated DSP domain\n");
280
281 /* if SoundWire is used, make sure it is not power-gated */
282 if (hdev->info.handle && hdev->info.link_mask > 0)
283 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
284 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));
285
286 return ret;
287 }
288 EXPORT_SYMBOL_NS(mtl_dsp_pre_fw_run, SND_SOC_SOF_INTEL_MTL);
289
290 int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
291 {
292 int ret;
293
294 if (sdev->first_boot) {
295 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
296
297 ret = hda_sdw_startup(sdev);
298 if (ret < 0) {
299 dev_err(sdev->dev, "could not startup SoundWire links\n");
300 return ret;
301 }
302
303 /* Check if IMR boot is usable */
304 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) {
305 hdev->imrboot_supported = true;
306 debugfs_create_bool("skip_imr_boot",
307 0644, sdev->debugfs_root,
308 &hdev->skip_imr_boot);
309 }
310 }
311
312 hda_sdw_int_enable(sdev, true);
313 return 0;
314 }
315 EXPORT_SYMBOL_NS(mtl_dsp_post_fw_run, SND_SOC_SOF_INTEL_MTL);
316
317 void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
318 {
319 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
320 u32 fwsts;
321 u32 fwlec;
322
323 hda_dsp_get_state(sdev, level);
324 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
325 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
326
327 if (fwsts != 0xffffffff)
328 dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n",
329 fwsts, fwlec);
330
331 sof_ipc4_intel_dump_telemetry_state(sdev, flags);
332 }
333 EXPORT_SYMBOL_NS(mtl_dsp_dump, SND_SOC_SOF_INTEL_MTL);
334
335 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
336 {
337 int val;
338
339 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);
340 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK)
341 return true;
342
343 return false;
344 }
345
346 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
347 {
348 unsigned int cpa;
349 u32 dspcxctl;
350 int ret;
351
352 /* Only the primary core can be powered up by the host */
353 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))
354 return 0;
355
356 /* Program the owner of the IP & shim registers (10: Host CPU) */
357 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
358 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL,
359 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT);
360
361 /* enable SPA bit */
362 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
363 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK,
364 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK);
365
366 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
367 usleep_range(1000, 1010);
368
369 /* poll with timeout to check if operation successful */
370 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK;
371 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
372 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
373 HDA_DSP_RESET_TIMEOUT_US);
374 if (ret < 0) {
375 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",
376 __func__);
377 return ret;
378 }
379
380 /* set primary core mask and refcount to 1 */
381 sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE);
382 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1;
383
384 return 0;
385 }
386
387 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
388 {
389 u32 dspcxctl;
390 int ret;
391
392 /* Only the primary core can be powered down by the host */
393 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))
394 return 0;
395
396 /* disable SPA bit */
397 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
398 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0);
399
400 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
401 usleep_range(1000, 1010);
402
403 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
404 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK),
405 HDA_DSP_REG_POLL_INTERVAL_US,
406 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
407 if (ret < 0) {
408 dev_err(sdev->dev, "failed to power down primary core\n");
409 return ret;
410 }
411
412 sdev->enabled_cores_mask = 0;
413 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0;
414
415 return 0;
416 }
417
418 int mtl_power_down_dsp(struct snd_sof_dev *sdev)
419 {
420 u32 dsphfdsscs, cpa;
421 int ret;
422
423 /* first power down core */
424 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
425 if (ret) {
426 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
427 return ret;
428 }
429
430 /* Set the DSP subsystem power down */
431 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
432 MTL_HFDSSCS_SPA_MASK, 0);
433
434 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
435 usleep_range(1000, 1010);
436
437 /* poll with timeout to check if operation successful */
438 cpa = MTL_HFDSSCS_CPA_MASK;
439 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
440 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
441 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
442 HDA_DSP_RESET_TIMEOUT_US);
443 }
444 EXPORT_SYMBOL_NS(mtl_power_down_dsp, SND_SOC_SOF_INTEL_MTL);
445
446 int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
447 {
448 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
449 const struct sof_intel_dsp_desc *chip = hda->desc;
450 unsigned int status, target_status;
451 u32 ipc_hdr, flags;
452 char *dump_msg;
453 int ret;
454
455 /* step 1: purge FW request */
456 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
457 if (!imr_boot)
458 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
459
460 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
461
462 /* step 2: power up primary core */
463 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
464 if (ret < 0) {
465 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
466 dev_err(sdev->dev, "dsp core 0/1 power up failed\n");
467 goto err;
468 }
469
470 dev_dbg(sdev->dev, "Primary core power up successful\n");
471
472 /* step 3: wait for IPC DONE bit from ROM */
473 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status,
474 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask),
475 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_INIT_TIMEOUT_US);
476 if (ret < 0) {
477 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
478 dev_err(sdev->dev, "timeout waiting for purge IPC done\n");
479 goto err;
480 }
481
482 /* set DONE bit to clear the reply IPC message */
483 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask,
484 chip->ipc_ack_mask);
485
486 /* step 4: enable interrupts */
487 ret = mtl_enable_interrupts(sdev, true);
488 if (ret < 0) {
489 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
490 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__);
491 goto err;
492 }
493
494 mtl_enable_ipc_interrupts(sdev);
495
496 if (chip->rom_status_reg == MTL_DSP_ROM_STS) {
497 /*
498 * Workaround: when the ROM status register is pointing to
499 * the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch
500 * ROM_INIT_DONE because of a very short timing window.
501 * Follow the recommendations and skip target state waiting.
502 */
503 return 0;
504 }
505
506 /*
507 * step 7:
508 * - Cold/Full boot: wait for ROM init to proceed to download the firmware
509 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
510 */
511 if (imr_boot)
512 target_status = FSR_STATE_FW_ENTERED;
513 else
514 target_status = FSR_STATE_INIT_DONE;
515
516 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
517 chip->rom_status_reg, status,
518 (FSR_TO_STATE_CODE(status) == target_status),
519 HDA_DSP_REG_POLL_INTERVAL_US,
520 chip->rom_init_timeout *
521 USEC_PER_MSEC);
522
523 if (!ret)
524 return 0;
525
526 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
527 dev_err(sdev->dev,
528 "%s: timeout with rom_status_reg (%#x) read\n",
529 __func__, chip->rom_status_reg);
530
531 err:
532 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
533
534 /* after max boot attempts make sure that the dump is printed */
535 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
536 flags &= ~SOF_DBG_DUMP_OPTIONAL;
537
538 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
539 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
540 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
541 mtl_enable_interrupts(sdev, false);
542 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
543
544 kfree(dump_msg);
545 return ret;
546 }
547 EXPORT_SYMBOL_NS(mtl_dsp_cl_init, SND_SOC_SOF_INTEL_MTL);
548
549 irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
550 {
551 struct sof_ipc4_msg notification_data = {{ 0 }};
552 struct snd_sof_dev *sdev = context;
553 bool ack_received = false;
554 bool ipc_irq = false;
555 u32 hipcida;
556 u32 hipctdr;
557
558 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
559 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
560
561 /* reply message from DSP */
562 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) {
563 /* DSP received the message */
564 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
565 MTL_DSP_REG_HFIPCXCTL_DONE, 0);
566
567 mtl_ipc_dsp_done(sdev);
568
569 ipc_irq = true;
570 ack_received = true;
571 }
572
573 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) {
574 /* Message from DSP (reply or notification) */
575 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
576 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK;
577
578 /*
579 * ACE fw sends a new fw ipc message to host to
580 * notify the status of the last host ipc message
581 */
582 if (primary & SOF_IPC4_MSG_DIR_MASK) {
583 /* Reply received */
584 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
585 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
586
587 data->primary = primary;
588 data->extension = extension;
589
590 spin_lock_irq(&sdev->ipc_lock);
591
592 snd_sof_ipc_get_reply(sdev);
593 mtl_ipc_host_done(sdev);
594 snd_sof_ipc_reply(sdev, data->primary);
595
596 spin_unlock_irq(&sdev->ipc_lock);
597 } else {
598 dev_dbg_ratelimited(sdev->dev,
599 "IPC reply before FW_READY: %#x|%#x\n",
600 primary, extension);
601 }
602 } else {
603 /* Notification received */
604 notification_data.primary = primary;
605 notification_data.extension = extension;
606
607 sdev->ipc->msg.rx_data = ¬ification_data;
608 snd_sof_ipc_msgs_rx(sdev);
609 sdev->ipc->msg.rx_data = NULL;
610
611 mtl_ipc_host_done(sdev);
612 }
613
614 ipc_irq = true;
615 }
616
617 if (!ipc_irq) {
618 /* This interrupt is not shared so no need to return IRQ_NONE. */
619 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
620 }
621
622 if (ack_received) {
623 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
624
625 if (hdev->delayed_ipc_tx_msg)
626 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg);
627 }
628
629 return IRQ_HANDLED;
630 }
631 EXPORT_SYMBOL_NS(mtl_ipc_irq_thread, SND_SOC_SOF_INTEL_MTL);
632
633 int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
634 {
635 return MTL_DSP_MBOX_UPLINK_OFFSET;
636 }
637 EXPORT_SYMBOL_NS(mtl_dsp_ipc_get_mailbox_offset, SND_SOC_SOF_INTEL_MTL);
638
639 int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
640 {
641 return MTL_SRAM_WINDOW_OFFSET(id);
642 }
643 EXPORT_SYMBOL_NS(mtl_dsp_ipc_get_window_offset, SND_SOC_SOF_INTEL_MTL);
644
645 void mtl_ipc_dump(struct snd_sof_dev *sdev)
646 {
647 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
648
649 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR);
650 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY);
651 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
652 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
653 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
654 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA);
655 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL);
656
657 dev_err(sdev->dev,
658 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
659 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
660 }
661 EXPORT_SYMBOL_NS(mtl_ipc_dump, SND_SOC_SOF_INTEL_MTL);
662
663 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
664 {
665 mtl_enable_sdw_irq(sdev, false);
666 mtl_disable_ipc_interrupts(sdev);
667 return mtl_enable_interrupts(sdev, false);
668 }
669
670 int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
671 {
672 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
673
674 if (core == SOF_DSP_PRIMARY_CORE)
675 return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
676
677 if (pm_ops->set_core_state)
678 return pm_ops->set_core_state(sdev, core, true);
679
680 return 0;
681 }
682 EXPORT_SYMBOL_NS(mtl_dsp_core_get, SND_SOC_SOF_INTEL_MTL);
683
684 int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
685 {
686 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
687 int ret;
688
689 if (pm_ops->set_core_state) {
690 ret = pm_ops->set_core_state(sdev, core, false);
691 if (ret < 0)
692 return ret;
693 }
694
695 if (core == SOF_DSP_PRIMARY_CORE)
696 return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
697
698 return 0;
699 }
700 EXPORT_SYMBOL_NS(mtl_dsp_core_put, SND_SOC_SOF_INTEL_MTL);
701
702 /* Meteorlake ops */
703 struct snd_sof_dsp_ops sof_mtl_ops;
704
705 int sof_mtl_ops_init(struct snd_sof_dev *sdev)
706 {
707 struct sof_ipc4_fw_data *ipc4_data;
708
709 /* common defaults */
710 memcpy(&sof_mtl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
711
712 /* shutdown */
713 sof_mtl_ops.shutdown = hda_dsp_shutdown;
714
715 /* doorbell */
716 sof_mtl_ops.irq_thread = mtl_ipc_irq_thread;
717
718 /* ipc */
719 sof_mtl_ops.send_msg = mtl_ipc_send_msg;
720 sof_mtl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
721 sof_mtl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
722
723 /* debug */
724 sof_mtl_ops.debug_map = mtl_dsp_debugfs;
725 sof_mtl_ops.debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs);
726 sof_mtl_ops.dbg_dump = mtl_dsp_dump;
727 sof_mtl_ops.ipc_dump = mtl_ipc_dump;
728
729 /* pre/post fw run */
730 sof_mtl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
731 sof_mtl_ops.post_fw_run = mtl_dsp_post_fw_run;
732
733 /* parse platform specific extended manifest */
734 sof_mtl_ops.parse_platform_ext_manifest = NULL;
735
736 /* dsp core get/put */
737 sof_mtl_ops.core_get = mtl_dsp_core_get;
738 sof_mtl_ops.core_put = mtl_dsp_core_put;
739
740 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
741 if (!sdev->private)
742 return -ENOMEM;
743
744 ipc4_data = sdev->private;
745 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
746
747 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
748
749 ipc4_data->fw_context_save = true;
750
751 /* External library loading support */
752 ipc4_data->load_library = hda_dsp_ipc4_load_library;
753
754 /* set DAI ops */
755 hda_set_dai_drv_ops(sdev, &sof_mtl_ops);
756
757 sof_mtl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
758
759 return 0;
760 };
761
762 const struct sof_intel_dsp_desc mtl_chip_info = {
763 .cores_num = 3,
764 .init_core_mask = BIT(0),
765 .host_managed_cores_mask = BIT(0),
766 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
767 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
768 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
769 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
770 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
771 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
772 .rom_init_timeout = 300,
773 .ssp_count = MTL_SSP_COUNT,
774 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
775 .sdw_shim_base = SDW_SHIM_BASE_ACE,
776 .sdw_alh_base = SDW_ALH_BASE_ACE,
777 .d0i3_offset = MTL_HDA_VS_D0I3C,
778 .read_sdw_lcount = hda_sdw_check_lcount_common,
779 .enable_sdw_irq = mtl_enable_sdw_irq,
780 .check_sdw_irq = mtl_dsp_check_sdw_irq,
781 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
782 .sdw_process_wakeen = hda_sdw_process_wakeen_common,
783 .check_ipc_irq = mtl_dsp_check_ipc_irq,
784 .cl_init = mtl_dsp_cl_init,
785 .power_down_dsp = mtl_power_down_dsp,
786 .disable_interrupts = mtl_dsp_disable_interrupts,
787 .hw_ip_version = SOF_INTEL_ACE_1_0,
788 };
789
790 const struct sof_intel_dsp_desc arl_s_chip_info = {
791 .cores_num = 2,
792 .init_core_mask = BIT(0),
793 .host_managed_cores_mask = BIT(0),
794 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
795 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
796 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
797 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
798 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
799 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
800 .rom_init_timeout = 300,
801 .ssp_count = MTL_SSP_COUNT,
802 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
803 .sdw_shim_base = SDW_SHIM_BASE_ACE,
804 .sdw_alh_base = SDW_ALH_BASE_ACE,
805 .d0i3_offset = MTL_HDA_VS_D0I3C,
806 .read_sdw_lcount = hda_sdw_check_lcount_common,
807 .enable_sdw_irq = mtl_enable_sdw_irq,
808 .check_sdw_irq = mtl_dsp_check_sdw_irq,
809 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
810 .sdw_process_wakeen = hda_sdw_process_wakeen_common,
811 .check_ipc_irq = mtl_dsp_check_ipc_irq,
812 .cl_init = mtl_dsp_cl_init,
813 .power_down_dsp = mtl_power_down_dsp,
814 .disable_interrupts = mtl_dsp_disable_interrupts,
815 .hw_ip_version = SOF_INTEL_ACE_1_0,
816 };
817
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