1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2022 Intel Corporation
7 */
8
9 #ifndef __IPC4_FW_REG_H__
10 #define __IPC4_FW_REG_H__
11
12 #define SOF_IPC4_INVALID_STREAM_POSITION ULLONG_MAX
13
14 /**
15 * struct sof_ipc4_pipeline_registers - Pipeline start and end information in fw
16 * @stream_start_offset: Stream start offset (LPIB) reported by mixin
17 * module allocated on pipeline attached to Host Output Gateway when
18 * first data is being mixed to mixout module. When data is not mixed
19 * (right after creation/after reset) value "(u64)-1" is reported
20 * @stream_end_offset: Stream end offset (LPIB) reported by mixin
21 * module allocated on pipeline attached to Host Output Gateway
22 * during transition from RUNNING to PAUSED. When data is not mixed
23 * (right after creation or after reset) value "(u64)-1" is reported.
24 * When first data is mixed then value ""is reported.
25 */
26 struct sof_ipc4_pipeline_registers {
27 u64 stream_start_offset;
28 u64 stream_end_offset;
29 } __packed __aligned(4);
30
31 #define SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS 8
32
33 /**
34 * struct sof_ipc4_peak_volume_regs - Volume information in fw
35 * @peak_meter: Peak volume value in fw
36 * @current_volume: Current volume value in fw
37 * @target_volume: Target volume value in fw
38 */
39 struct sof_ipc4_peak_volume_regs {
40 u32 peak_meter[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS];
41 u32 current_volume[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS];
42 u32 target_volume[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS];
43 } __packed __aligned(4);
44
45 /**
46 * struct sof_ipc4_llp_reading - Llp information in fw
47 * @llp_l: Lower part of 64-bit LLP
48 * @llp_u: Upper part of 64-bit LLP
49 * @wclk_l: Lower part of 64-bit Wallclock
50 * @wclk_u: Upper part of 64-bit Wallclock
51 */
52 struct sof_ipc4_llp_reading {
53 u32 llp_l;
54 u32 llp_u;
55 u32 wclk_l;
56 u32 wclk_u;
57 } __packed __aligned(4);
58
59 /**
60 * struct of sof_ipc4_llp_reading_extended - Extended llp info
61 * @llp_reading: Llp information in memory window
62 * @tpd_low: Total processed data (low part)
63 * @tpd_high: Total processed data (high part)
64 */
65 struct sof_ipc4_llp_reading_extended {
66 struct sof_ipc4_llp_reading llp_reading;
67 u32 tpd_low;
68 u32 tpd_high;
69 } __packed __aligned(4);
70
71 /**
72 * struct sof_ipc4_llp_reading_slot - Llp slot information in memory window
73 * @node_id: Dai gateway node id
74 * @reading: Llp information in memory window
75 */
76 struct sof_ipc4_llp_reading_slot {
77 u32 node_id;
78 struct sof_ipc4_llp_reading reading;
79 } __packed __aligned(4);
80
81 /* ROM information */
82 #define SOF_IPC4_FW_FUSE_VALUE_MASK GENMASK(7, 0)
83 #define SOF_IPC4_FW_LOAD_METHOD_MASK BIT(8)
84 #define SOF_IPC4_FW_DOWNLINK_IPC_USE_DMA_MASK BIT(9)
85 #define SOF_IPC4_FW_LOAD_METHOD_REV_MASK GENMASK(11, 10)
86 #define SOF_IPC4_FW_REVISION_MIN_MASK GENMASK(15, 12)
87 #define SOF_IPC4_FW_REVISION_MAJ_MASK GENMASK(19, 16)
88 #define SOF_IPC4_FW_VERSION_MIN_MASK GENMASK(23, 20)
89 #define SOF_IPC4_FW_VERSION_MAJ_MASK GENMASK(27, 24)
90
91 /* Number of dsp core supported in FW Regs. */
92 #define SOF_IPC4_MAX_SUPPORTED_ADSP_CORES 8
93
94 /* Number of host pipeline registers slots in FW Regs. */
95 #define SOF_IPC4_MAX_PIPELINE_REG_SLOTS 16
96
97 /* Number of PeakVol registers slots in FW Regs. */
98 #define SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS 16
99
100 /* Number of GPDMA LLP Reading slots in FW Regs. */
101 #define SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS 24
102
103 /* Number of Aggregated SNDW Reading slots in FW Regs. */
104 #define SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS 15
105
106 /* Current ABI version of the Fw registers layout. */
107 #define SOF_IPC4_FW_REGS_ABI_VER 1
108
109 /**
110 * struct sof_ipc4_fw_registers - FW Registers exposes additional
111 * DSP / FW state information to the driver
112 * @fw_status: Current ROM / FW status
113 * @lec: Last ROM / FW error code
114 * @fps: Current DSP clock status
115 * @lnec: Last Native Error Code(from external library)
116 * @ltr: Copy of LTRC HW register value(FW only)
117 * @rsvd0: Reserved0
118 * @rom_info: ROM info
119 * @abi_ver: Version of the layout, set to the current FW_REGS_ABI_VER
120 * @slave_core_sts: Slave core states
121 * @rsvd2: Reserved2
122 * @pipeline_regs: State of pipelines attached to host output gateways
123 * @peak_vol_regs: State of PeakVol instances indexed by the PeakVol's instance_id
124 * @llp_gpdma_reading_slots: LLP Readings for single link gateways
125 * @llp_sndw_reading_slots: SNDW aggregated link gateways
126 * @llp_evad_reading_slot: LLP Readings for EVAD gateway
127 */
128 struct sof_ipc4_fw_registers {
129 u32 fw_status;
130 u32 lec;
131 u32 fps;
132 u32 lnec;
133 u32 ltr;
134 u32 rsvd0;
135 u32 rom_info;
136 u32 abi_ver;
137 u8 slave_core_sts[SOF_IPC4_MAX_SUPPORTED_ADSP_CORES];
138 u32 rsvd2[6];
139
140 struct sof_ipc4_pipeline_registers
141 pipeline_regs[SOF_IPC4_MAX_PIPELINE_REG_SLOTS];
142
143 struct sof_ipc4_peak_volume_regs
144 peak_vol_regs[SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS];
145
146 struct sof_ipc4_llp_reading_slot
147 llp_gpdma_reading_slots[SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS];
148
149 struct sof_ipc4_llp_reading_slot
150 llp_sndw_reading_slots[SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS];
151
152 struct sof_ipc4_llp_reading_slot llp_evad_reading_slot;
153 } __packed __aligned(4);
154
155 #endif
156
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.