1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tegra20_ac97.h - Definitions for the Tegra20 AC97 controller driver
4 *
5 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
6 *
7 * Partly based on code copyright/by:
8 *
9 * Copyright (c) 2011,2012 Toradex Inc.
10 */
11
12 #ifndef __TEGRA20_AC97_H__
13 #define __TEGRA20_AC97_H__
14
15 #include "tegra_pcm.h"
16
17 #define TEGRA20_AC97_CTRL 0x00
18 #define TEGRA20_AC97_CMD 0x04
19 #define TEGRA20_AC97_STATUS1 0x08
20 /* ... */
21 #define TEGRA20_AC97_FIFO1_SCR 0x1c
22 /* ... */
23 #define TEGRA20_AC97_FIFO_TX1 0x40
24 #define TEGRA20_AC97_FIFO_RX1 0x80
25
26 /* TEGRA20_AC97_CTRL */
27 #define TEGRA20_AC97_CTRL_STM2_EN (1 << 16)
28 #define TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN (1 << 11)
29 #define TEGRA20_AC97_CTRL_IO_CNTRL_EN (1 << 10)
30 #define TEGRA20_AC97_CTRL_HSET_DAC_EN (1 << 9)
31 #define TEGRA20_AC97_CTRL_LINE2_DAC_EN (1 << 8)
32 #define TEGRA20_AC97_CTRL_PCM_LFE_EN (1 << 7)
33 #define TEGRA20_AC97_CTRL_PCM_SUR_EN (1 << 6)
34 #define TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN (1 << 5)
35 #define TEGRA20_AC97_CTRL_LINE1_DAC_EN (1 << 4)
36 #define TEGRA20_AC97_CTRL_PCM_DAC_EN (1 << 3)
37 #define TEGRA20_AC97_CTRL_COLD_RESET (1 << 2)
38 #define TEGRA20_AC97_CTRL_WARM_RESET (1 << 1)
39 #define TEGRA20_AC97_CTRL_STM_EN (1 << 0)
40
41 /* TEGRA20_AC97_CMD */
42 #define TEGRA20_AC97_CMD_CMD_ADDR_SHIFT 24
43 #define TEGRA20_AC97_CMD_CMD_ADDR_MASK (0xff << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT)
44 #define TEGRA20_AC97_CMD_CMD_DATA_SHIFT 8
45 #define TEGRA20_AC97_CMD_CMD_DATA_MASK (0xffff << TEGRA20_AC97_CMD_CMD_DATA_SHIFT)
46 #define TEGRA20_AC97_CMD_CMD_ID_SHIFT 2
47 #define TEGRA20_AC97_CMD_CMD_ID_MASK (0x3 << TEGRA20_AC97_CMD_CMD_ID_SHIFT)
48 #define TEGRA20_AC97_CMD_BUSY (1 << 0)
49
50 /* TEGRA20_AC97_STATUS1 */
51 #define TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT 24
52 #define TEGRA20_AC97_STATUS1_STA_ADDR1_MASK (0xff << TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT)
53 #define TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT 8
54 #define TEGRA20_AC97_STATUS1_STA_DATA1_MASK (0xffff << TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT)
55 #define TEGRA20_AC97_STATUS1_STA_VALID1 (1 << 2)
56 #define TEGRA20_AC97_STATUS1_STANDBY1 (1 << 1)
57 #define TEGRA20_AC97_STATUS1_CODEC1_RDY (1 << 0)
58
59 /* TEGRA20_AC97_FIFO1_SCR */
60 #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT 27
61 #define TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT)
62 #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT 22
63 #define TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK (0x1f << TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT)
64 #define TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA (1 << 19)
65 #define TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA (1 << 18)
66 #define TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT (1 << 17)
67 #define TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT (1 << 16)
68 #define TEGRA20_AC97_FIFO_SCR_REC_FULL_EN (1 << 15)
69 #define TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN (1 << 14)
70 #define TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN (1 << 13)
71 #define TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN (1 << 12)
72 #define TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN (1 << 11)
73 #define TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN (1 << 10)
74 #define TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN (1 << 9)
75 #define TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN (1 << 8)
76
77 struct tegra20_ac97 {
78 struct clk *clk_ac97;
79 struct snd_dmaengine_dai_dma_data capture_dma_data;
80 struct snd_dmaengine_dai_dma_data playback_dma_data;
81 struct reset_control *reset;
82 struct regmap *regmap;
83 struct gpio_desc *reset_gpio;
84 struct gpio_desc *sync_gpio;
85 };
86 #endif /* __TEGRA20_AC97_H__ */
87
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