1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tegra210_i2s.h - Definitions for Tegra210 I2S driver
4 *
5 * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
6 *
7 */
8
9 #ifndef __TEGRA210_I2S_H__
10 #define __TEGRA210_I2S_H__
11
12 /* Register offsets from I2S*_BASE */
13 #define TEGRA210_I2S_RX_ENABLE 0x0
14 #define TEGRA210_I2S_RX_SOFT_RESET 0x4
15 #define TEGRA210_I2S_RX_STATUS 0x0c
16 #define TEGRA210_I2S_RX_INT_STATUS 0x10
17 #define TEGRA210_I2S_RX_INT_MASK 0x14
18 #define TEGRA210_I2S_RX_INT_SET 0x18
19 #define TEGRA210_I2S_RX_INT_CLEAR 0x1c
20 #define TEGRA210_I2S_RX_CIF_CTRL 0x20
21 #define TEGRA210_I2S_RX_CTRL 0x24
22 #define TEGRA210_I2S_RX_SLOT_CTRL 0x28
23 #define TEGRA210_I2S_RX_CLK_TRIM 0x2c
24 #define TEGRA210_I2S_RX_CYA 0x30
25 #define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34
26 #define TEGRA210_I2S_TX_ENABLE 0x40
27 #define TEGRA210_I2S_TX_SOFT_RESET 0x44
28 #define TEGRA210_I2S_TX_STATUS 0x4c
29 #define TEGRA210_I2S_TX_INT_STATUS 0x50
30 #define TEGRA210_I2S_TX_INT_MASK 0x54
31 #define TEGRA210_I2S_TX_INT_SET 0x58
32 #define TEGRA210_I2S_TX_INT_CLEAR 0x5c
33 #define TEGRA210_I2S_TX_CIF_CTRL 0x60
34 #define TEGRA210_I2S_TX_CTRL 0x64
35 #define TEGRA210_I2S_TX_SLOT_CTRL 0x68
36 #define TEGRA210_I2S_TX_CLK_TRIM 0x6c
37 #define TEGRA210_I2S_TX_CYA 0x70
38 #define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74
39 #define TEGRA210_I2S_ENABLE 0x80
40 #define TEGRA210_I2S_SOFT_RESET 0x84
41 #define TEGRA210_I2S_CG 0x88
42 #define TEGRA210_I2S_STATUS 0x8c
43 #define TEGRA210_I2S_INT_STATUS 0x90
44 #define TEGRA210_I2S_CTRL 0xa0
45 #define TEGRA210_I2S_TIMING 0xa4
46 #define TEGRA210_I2S_SLOT_CTRL 0xa8
47 #define TEGRA210_I2S_CLK_TRIM 0xac
48 #define TEGRA210_I2S_CYA 0xb0
49
50 /* Bit fields, shifts and masks */
51 #define I2S_DATA_SHIFT 8
52 #define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)
53
54 #define I2S_EN_SHIFT 0
55 #define I2S_EN_MASK BIT(I2S_EN_SHIFT)
56 #define I2S_EN BIT(I2S_EN_SHIFT)
57
58 #define I2S_FSYNC_WIDTH_SHIFT 24
59 #define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)
60
61 #define I2S_POS_EDGE 0
62 #define I2S_NEG_EDGE 1
63 #define I2S_EDGE_SHIFT 20
64 #define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)
65 #define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT)
66 #define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT)
67
68 #define I2S_FMT_LRCK 0
69 #define I2S_FMT_FSYNC 1
70 #define I2S_FMT_SHIFT 12
71 #define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT)
72 #define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT)
73 #define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT)
74
75 #define I2S_CTRL_MASTER_EN_SHIFT 10
76 #define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)
77 #define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT)
78
79 #define I2S_CTRL_LRCK_POL_SHIFT 9
80 #define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT)
81 #define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)
82 #define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT)
83
84 #define I2S_CTRL_LPBK_SHIFT 8
85 #define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT)
86 #define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT)
87
88 #define I2S_BITS_8 1
89 #define I2S_BITS_16 3
90 #define I2S_BITS_32 7
91 #define I2S_CTRL_BIT_SIZE_MASK 0x7
92
93 #define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff
94 #define I2S_TIMING_CH_BIT_CNT_SHIFT 0
95
96 #define I2S_SOFT_RESET_SHIFT 0
97 #define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT)
98 #define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT)
99
100 #define I2S_RX_FIFO_DEPTH 64
101 #define DEFAULT_I2S_RX_FIFO_THRESHOLD 3
102
103 #define DEFAULT_I2S_SLOT_MASK 0xffff
104
105 enum tegra210_i2s_path {
106 I2S_RX_PATH,
107 I2S_TX_PATH,
108 I2S_PATHS,
109 };
110
111 struct tegra210_i2s {
112 struct clk *clk_i2s;
113 struct clk *clk_sync_input;
114 struct regmap *regmap;
115 int client_sample_format;
116 unsigned int client_channels;
117 unsigned int stereo_to_mono[I2S_PATHS];
118 unsigned int mono_to_stereo[I2S_PATHS];
119 unsigned int dai_fmt;
120 unsigned int fsync_width;
121 unsigned int bclk_ratio;
122 unsigned int tx_mask;
123 unsigned int rx_mask;
124 unsigned int rx_fifo_th;
125 bool loopback;
126 };
127
128 #endif
129
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