1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tegra30_ahub.h - Definitions for Tegra30 AHUB driver
4 *
5 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #ifndef __TEGRA30_AHUB_H__
9 #define __TEGRA30_AHUB_H__
10
11 /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
12
13 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28
14 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf
15 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
16
17 #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24
18 #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f
19 #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
20
21 /* Channel count minus 1 */
22 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24
23 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7
24 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
25
26 /* Channel count minus 1 */
27 #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20
28 #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf
29 #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
30
31 /* Channel count minus 1 */
32 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16
33 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7
34 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
35
36 /* Channel count minus 1 */
37 #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16
38 #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf
39 #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
40
41 #define TEGRA30_AUDIOCIF_BITS_4 0
42 #define TEGRA30_AUDIOCIF_BITS_8 1
43 #define TEGRA30_AUDIOCIF_BITS_12 2
44 #define TEGRA30_AUDIOCIF_BITS_16 3
45 #define TEGRA30_AUDIOCIF_BITS_20 4
46 #define TEGRA30_AUDIOCIF_BITS_24 5
47 #define TEGRA30_AUDIOCIF_BITS_28 6
48 #define TEGRA30_AUDIOCIF_BITS_32 7
49
50 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12
51 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
52 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
53 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
54 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
55 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
56 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
57 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
58 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
59 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
60
61 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8
62 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
63 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
64 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
65 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
66 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
67 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
68 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
69 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
70 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
71
72 #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0
73 #define TEGRA30_AUDIOCIF_EXPAND_ONE 1
74 #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2
75
76 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6
77 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
78 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
79 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
80 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
81
82 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0
83 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1
84 #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2
85
86 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4
87 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
88 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
89 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
90 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
91
92 #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT 3
93
94 #define TEGRA30_AUDIOCIF_DIRECTION_TX 0
95 #define TEGRA30_AUDIOCIF_DIRECTION_RX 1
96
97 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2
98 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
99 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
100 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
101
102 #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0
103 #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1
104
105 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1
106 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
107 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
108 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
109
110 #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0
111 #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1
112
113 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0
114 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
115 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
116 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
117
118 /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */
119
120 /* TEGRA30_AHUB_CHANNEL_CTRL */
121
122 #define TEGRA30_AHUB_CHANNEL_CTRL 0x0
123 #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20
124 #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4
125 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31)
126 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30)
127 #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29)
128
129 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16
130 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff
131 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT)
132
133 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8
134 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff
135 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT)
136
137 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6)
138
139 #define TEGRA30_PACK_8_4 2
140 #define TEGRA30_PACK_16 3
141
142 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4
143 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3
144 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
145 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
146 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
147
148 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2)
149
150 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0
151 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3
152 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
153 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
154 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
155
156 /* TEGRA30_AHUB_CHANNEL_CLEAR */
157
158 #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4
159 #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20
160 #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4
161 #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31)
162 #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30)
163
164 /* TEGRA30_AHUB_CHANNEL_STATUS */
165
166 #define TEGRA30_AHUB_CHANNEL_STATUS 0x8
167 #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20
168 #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4
169 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24
170 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff
171 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT)
172 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16
173 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff
174 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT)
175 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1)
176 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0)
177
178 /* TEGRA30_AHUB_CHANNEL_TXFIFO */
179
180 #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc
181 #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20
182 #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4
183
184 /* TEGRA30_AHUB_CHANNEL_RXFIFO */
185
186 #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10
187 #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20
188 #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4
189
190 /* TEGRA30_AHUB_CIF_TX_CTRL */
191
192 #define TEGRA30_AHUB_CIF_TX_CTRL 0x14
193 #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20
194 #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4
195 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
196
197 /* TEGRA30_AHUB_CIF_RX_CTRL */
198
199 #define TEGRA30_AHUB_CIF_RX_CTRL 0x18
200 #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20
201 #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4
202 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
203
204 /* TEGRA30_AHUB_CONFIG_LINK_CTRL */
205
206 #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80
207 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28
208 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf
209 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT)
210 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16
211 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff
212 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT)
213 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4
214 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff
215 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT)
216 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2)
217 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1)
218 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0)
219
220 /* TEGRA30_AHUB_MISC_CTRL */
221
222 #define TEGRA30_AHUB_MISC_CTRL 0x84
223 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31)
224 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8)
225 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0
226 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT)
227
228 /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */
229
230 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88
231 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31)
232 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30)
233 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29)
234 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28)
235 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27)
236 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26)
237 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25)
238 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24)
239 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23)
240 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22)
241 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21)
242 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20)
243 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19)
244 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18)
245 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17)
246 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16)
247 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15)
248 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14)
249 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13)
250 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12)
251 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11)
252 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10)
253 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9)
254 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8)
255 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7)
256 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6)
257 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5)
258 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4)
259 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3)
260 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2)
261 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1)
262 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0)
263
264 /* TEGRA30_AHUB_I2S_LIVE_STATUS */
265
266 #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c
267 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29)
268 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28)
269 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27)
270 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26)
271 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25)
272 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24)
273 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23)
274 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22)
275 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21)
276 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20)
277 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19)
278 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18)
279 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17)
280 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16)
281 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15)
282 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14)
283 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13)
284 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12)
285 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11)
286 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10)
287 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9)
288 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8)
289 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7)
290 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6)
291 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5)
292 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4)
293 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3)
294 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2)
295 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1)
296 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0)
297
298 /* TEGRA30_AHUB_DAM0_LIVE_STATUS */
299
300 #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90
301 #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8
302 #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3
303 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26)
304 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25)
305 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24)
306 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15)
307 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9)
308 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8)
309 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7)
310 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1)
311 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0)
312
313 /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */
314
315 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8
316 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11)
317 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10)
318 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9)
319 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8)
320 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7)
321 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6)
322 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5)
323 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4)
324 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3)
325 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2)
326 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1)
327 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0)
328
329 /* TEGRA30_AHUB_I2S_INT_MASK */
330
331 #define TEGRA30_AHUB_I2S_INT_MASK 0xb0
332
333 /* TEGRA30_AHUB_DAM_INT_MASK */
334
335 #define TEGRA30_AHUB_DAM_INT_MASK 0xb4
336
337 /* TEGRA30_AHUB_SPDIF_INT_MASK */
338
339 #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc
340
341 /* TEGRA30_AHUB_APBIF_INT_MASK */
342
343 #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0
344
345 /* TEGRA30_AHUB_I2S_INT_STATUS */
346
347 #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8
348
349 /* TEGRA30_AHUB_DAM_INT_STATUS */
350
351 #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc
352
353 /* TEGRA30_AHUB_SPDIF_INT_STATUS */
354
355 #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4
356
357 /* TEGRA30_AHUB_APBIF_INT_STATUS */
358
359 #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8
360
361 /* TEGRA30_AHUB_I2S_INT_SOURCE */
362
363 #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0
364
365 /* TEGRA30_AHUB_DAM_INT_SOURCE */
366
367 #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4
368
369 /* TEGRA30_AHUB_SPDIF_INT_SOURCE */
370
371 #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec
372
373 /* TEGRA30_AHUB_APBIF_INT_SOURCE */
374
375 #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0
376
377 /* TEGRA30_AHUB_I2S_INT_SET */
378
379 #define TEGRA30_AHUB_I2S_INT_SET 0xf8
380
381 /* TEGRA30_AHUB_DAM_INT_SET */
382
383 #define TEGRA30_AHUB_DAM_INT_SET 0xfc
384
385 /* TEGRA30_AHUB_SPDIF_INT_SET */
386
387 #define TEGRA30_AHUB_SPDIF_INT_SET 0x100
388
389 /* TEGRA30_AHUB_APBIF_INT_SET */
390
391 #define TEGRA30_AHUB_APBIF_INT_SET 0x104
392
393 /* Registers within TEGRA30_AHUB_BASE */
394
395 #define TEGRA30_AHUB_AUDIO_RX 0x0
396 #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4
397 #define TEGRA30_AHUB_AUDIO_RX_COUNT 17
398 /* This register repeats once for each entry in enum tegra30_ahub_rxcif */
399 /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */
400
401 /*
402 * Terminology:
403 * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs,
404 * I2S controllers, SPDIF controllers, and DAMs.
405 * XBAR: The core cross-bar component of the AHUB.
406 * CIF: Client Interface; the HW module connecting an audio device to the
407 * XBAR.
408 * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams,
409 * possibly including sample-rate conversion.
410 *
411 * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
412 * transmitted by a particular TX CIF.
413 *
414 * This driver is currently very simplistic; many HW features are not
415 * exposed; DAMs are not supported, only 16-bit stereo audio is supported,
416 * etc.
417 */
418
419 enum tegra30_ahub_txcif {
420 TEGRA30_AHUB_TXCIF_APBIF_TX0,
421 TEGRA30_AHUB_TXCIF_APBIF_TX1,
422 TEGRA30_AHUB_TXCIF_APBIF_TX2,
423 TEGRA30_AHUB_TXCIF_APBIF_TX3,
424 TEGRA30_AHUB_TXCIF_I2S0_TX0,
425 TEGRA30_AHUB_TXCIF_I2S1_TX0,
426 TEGRA30_AHUB_TXCIF_I2S2_TX0,
427 TEGRA30_AHUB_TXCIF_I2S3_TX0,
428 TEGRA30_AHUB_TXCIF_I2S4_TX0,
429 TEGRA30_AHUB_TXCIF_DAM0_TX0,
430 TEGRA30_AHUB_TXCIF_DAM1_TX0,
431 TEGRA30_AHUB_TXCIF_DAM2_TX0,
432 TEGRA30_AHUB_TXCIF_SPDIF_TX0,
433 TEGRA30_AHUB_TXCIF_SPDIF_TX1,
434 };
435
436 enum tegra30_ahub_rxcif {
437 TEGRA30_AHUB_RXCIF_APBIF_RX0,
438 TEGRA30_AHUB_RXCIF_APBIF_RX1,
439 TEGRA30_AHUB_RXcIF_APBIF_RX2,
440 TEGRA30_AHUB_RXCIF_APBIF_RX3,
441 TEGRA30_AHUB_RXCIF_I2S0_RX0,
442 TEGRA30_AHUB_RXCIF_I2S1_RX0,
443 TEGRA30_AHUB_RXCIF_I2S2_RX0,
444 TEGRA30_AHUB_RXCIF_I2S3_RX0,
445 TEGRA30_AHUB_RXCIF_I2S4_RX0,
446 TEGRA30_AHUB_RXCIF_DAM0_RX0,
447 TEGRA30_AHUB_RXCIF_DAM0_RX1,
448 TEGRA30_AHUB_RXCIF_DAM1_RX0,
449 TEGRA30_AHUB_RXCIF_DAM2_RX1,
450 TEGRA30_AHUB_RXCIF_DAM3_RX0,
451 TEGRA30_AHUB_RXCIF_DAM3_RX1,
452 TEGRA30_AHUB_RXCIF_SPDIF_RX0,
453 TEGRA30_AHUB_RXCIF_SPDIF_RX1,
454 };
455
456 extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
457 char *dmachan, int dmachan_len,
458 dma_addr_t *fiforeg);
459 extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
460 extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
461 extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
462
463 extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
464 char *dmachan, int dmachan_len,
465 dma_addr_t *fiforeg);
466 extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
467 extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
468 extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
469
470 extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
471 enum tegra30_ahub_txcif txcif);
472 extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif);
473
474 struct tegra30_ahub_cif_conf {
475 unsigned int threshold;
476 unsigned int audio_channels;
477 unsigned int client_channels;
478 unsigned int audio_bits;
479 unsigned int client_bits;
480 unsigned int expand;
481 unsigned int stereo_conv;
482 unsigned int replicate;
483 unsigned int direction;
484 unsigned int truncate;
485 unsigned int mono_conv;
486 };
487
488 void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg,
489 struct tegra30_ahub_cif_conf *conf);
490 void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
491 struct tegra30_ahub_cif_conf *conf);
492
493 struct tegra30_ahub_soc_data {
494 unsigned int num_resets;
495 void (*set_audio_cif)(struct regmap *regmap,
496 unsigned int reg,
497 struct tegra30_ahub_cif_conf *conf);
498 /*
499 * FIXME: There are many more differences in HW, such as:
500 * - More APBIF channels.
501 * - Extra separate chunks of register address space to represent
502 * the extra APBIF channels.
503 * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif
504 * need expansion, coupled with there being more defined bits in
505 * the AHUB routing registers.
506 * However, the driver doesn't support those new features yet, so we
507 * don't represent them here yet.
508 */
509 };
510
511 struct tegra30_ahub {
512 const struct tegra30_ahub_soc_data *soc_data;
513 struct device *dev;
514 struct reset_control_bulk_data resets[21];
515 unsigned int nresets;
516 struct clk_bulk_data clocks[2];
517 unsigned int nclocks;
518 resource_size_t apbif_addr;
519 struct regmap *regmap_apbif;
520 struct regmap *regmap_ahub;
521 DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
522 DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
523 };
524
525 #endif
526
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